Инициализация репозитория.

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo.veo

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+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+MeasDataFifo your_instance_name (
+  .clk(clk),      // input wire clk
+  .srst(srst),    // input wire srst
+  .din(din),      // input wire [255 : 0] din
+  .wr_en(wr_en),  // input wire wr_en
+  .rd_en(rd_en),  // input wire rd_en
+  .dout(dout),    // output wire [255 : 0] dout
+  .full(full),    // output wire full
+  .empty(empty)  // output wire empty
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file MeasDataFifo.v when simulating
+// the core, MeasDataFifo. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo.vho

@@ -0,0 +1,89 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT MeasDataFifo
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : MeasDataFifo
+  PORT MAP (
+    clk => clk,
+    srst => srst,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file MeasDataFifo.vhd when simulating
+-- the core, MeasDataFifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

S5443_M/S5443.ip_user_files/mem_init_files/blk_mem_gen_0.mif

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S5443_M/S5443.ip_user_files/mem_init_files/fir_compiler_0.h

@@ -0,0 +1,115 @@
+
+//------------------------------------------------------------------------------
+// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------ 
+//
+// C Model configuration for the "fir_compiler_0" instance.
+//
+//------------------------------------------------------------------------------
+//
+// coefficients: 1283,-543,-4323,7716,8806,-34012,-178,131071,131071,-178,-34012,8806,7716,-4323,-543,1283
+// chanpats: 173
+// name: fir_compiler_0
+// filter_type: 0
+// rate_change: 0
+// interp_rate: 1
+// decim_rate: 1
+// zero_pack_factor: 1
+// coeff_padding: 0
+// num_coeffs: 16
+// coeff_sets: 1
+// reloadable: 0
+// is_halfband: 0
+// quantization: 0
+// coeff_width: 18
+// coeff_fract_width: 0
+// chan_seq: 0
+// num_channels: 1
+// num_paths: 1
+// data_width: 22
+// data_fract_width: 21
+// output_rounding_mode: 0
+// output_width: 41
+// output_fract_width: 21
+// config_method: 0
+
+const double fir_compiler_0_coefficients[16] = {1283,-543,-4323,7716,8806,-34012,-178,131071,131071,-178,-34012,8806,7716,-4323,-543,1283};
+
+const xip_fir_v7_2_pattern fir_compiler_0_chanpats[1] = {P_BASIC};
+
+static xip_fir_v7_2_config gen_fir_compiler_0_config() {
+  xip_fir_v7_2_config config;
+  config.name                = "fir_compiler_0";
+  config.filter_type         = 0;
+  config.rate_change         = XIP_FIR_INTEGER_RATE;
+  config.interp_rate         = 1;
+  config.decim_rate          = 1;
+  config.zero_pack_factor    = 1;
+  config.coeff               = &fir_compiler_0_coefficients[0];
+  config.coeff_padding       = 0;
+  config.num_coeffs          = 16;
+  config.coeff_sets          = 1;
+  config.reloadable          = 0;
+  config.is_halfband         = 0;
+  config.quantization        = XIP_FIR_INTEGER_COEFF;
+  config.coeff_width         = 18;
+  config.coeff_fract_width   = 0;
+  config.chan_seq            = XIP_FIR_BASIC_CHAN_SEQ;
+  config.num_channels        = 1;
+  config.init_pattern        = fir_compiler_0_chanpats[0];
+  config.num_paths           = 1;
+  config.data_width          = 22;
+  config.data_fract_width    = 21;
+  config.output_rounding_mode= XIP_FIR_FULL_PRECISION;
+  config.output_width        = 41;
+  config.output_fract_width  = 21,
+  config.config_method       = XIP_FIR_CONFIG_SINGLE;
+  return config;
+}
+
+const xip_fir_v7_2_config fir_compiler_0_config = gen_fir_compiler_0_config();
+

S5443_M/S5443.ip_user_files/mem_init_files/fir_compiler_0.mif

@@ -0,0 +1,8 @@
+00000503 0 0 0 0 0 0
+fffffde1 0 0 0 0 1 0
+ffffef1d 0 1 0 0 2 0
+00001e24 0 1 0 0 3 0
+00002266 0 2 0 0 4 0
+ffff7b24 0 2 0 0 5 0
+ffffff4e 0 3 0 0 6 0
+0001ffff 0 3 0 0 7 0

S5443_M/S5443.ip_user_files/mem_init_files/fir_filter.coe

@@ -0,0 +1,19 @@
+Radix = 10;
+Coefficient_Width = 18;
+Coefdata =
+1283,
+-543,
+-4323,
+7716,
+8806,
+-34012,
+-178,
+131071,
+131071,
+-178,
+-34012,
+8806,
+7716,
+-4323,
+-543,
+1283;

S5443_M/S5443.ip_user_files/mem_init_files/sincoscalues.coe

@@ -0,0 +1,402 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+011111111111111111000000000000000000,
+011111111111101111000000100000001010,
+011111111110111111000001000000010101,
+011111111101101110000001100000011110,
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+011111111111101111111111011111110110;

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.veo

@@ -0,0 +1,72 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+MeasDataFifo your_instance_name (
+  .clk(clk),      // input wire clk
+  .srst(srst),    // input wire srst
+  .din(din),      // input wire [255 : 0] din
+  .wr_en(wr_en),  // input wire wr_en
+  .rd_en(rd_en),  // input wire rd_en
+  .dout(dout),    // output wire [255 : 0] dout
+  .full(full),    // output wire full
+  .empty(empty)  // output wire empty
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file MeasDataFifo.v when simulating
+// the core, MeasDataFifo. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.vho

@@ -0,0 +1,89 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT MeasDataFifo
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : MeasDataFifo
+  PORT MAP (
+    clk => clk,
+    srst => srst,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file MeasDataFifo.vhd when simulating
+-- the core, MeasDataFifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xdc

@@ -0,0 +1,64 @@
+ 
+ 
+ 
+ 
+ 
+
+################################################################################
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+#------------------------------------------------------------------------------#
+#                         Native FIFO Constraints                              #
+#------------------------------------------------------------------------------#
+
+
+
+
+################################################################################
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_clocks.xdc

@@ -0,0 +1,69 @@
+################################################################################
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+#------------------------------------------------------------------------------#
+#                         Native FIFO Constraints                              #
+#------------------------------------------------------------------------------#
+
+#set wr_clock          [get_clocks -of_objects [get_ports wr_clk]]
+#set rd_clock          [get_clocks -of_objects [get_ports rd_clk]]
+#set wr_clk_period     [get_property PERIOD $wr_clock]
+#set rd_clk_period     [get_property PERIOD $rd_clock]
+#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
+
+
+# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
+
+## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
+## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
+
+## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
+## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
+#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
+#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
+################################################################################

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name clk [get_ports clk]
+
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Fri Nov 19 10:12:01 2021
+// Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
+//               MeasDataFifo_ MeasDataFifo_stub.v
+// Design      : MeasDataFifo
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7s25csga225-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *)
+module MeasDataFifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
+/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty" */;
+  input clk;
+  input srst;
+  input [255:0]din;
+  input wr_en;
+  input rd_en;
+  output [255:0]dout;
+  output full;
+  output empty;
+endmodule

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -0,0 +1,37 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Fri Nov 19 10:12:01 2021
+-- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
+--               MeasDataFifo_ MeasDataFifo_stub.vhdl
+-- Design      : MeasDataFifo
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7s25csga225-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity MeasDataFifo is
+  Port ( 
+    clk : in STD_LOGIC;
+    srst : in STD_LOGIC;
+    din : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    wr_en : in STD_LOGIC;
+    rd_en : in STD_LOGIC;
+    dout : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    full : out STD_LOGIC;
+    empty : out STD_LOGIC
+  );
+
+end MeasDataFifo;
+
+architecture stub of MeasDataFifo is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2";
+begin
+end;

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/doc/fifo_generator_v13_2_changelog.txt

@@ -0,0 +1,254 @@
+2020.2:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2020.1.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2.2:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2:
+ * Version 13.2 (Rev. 5)
+ * General: IP Waivers update in constraint files. No functional changes
+ * Revision change in one or more subcores
+
+2019.1.3:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1.2:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1.1:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1:
+ * Version 13.2 (Rev. 4)
+ * Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
+ * Other: IP Waivers added in constraint files. No functional changes
+ * Revision change in one or more subcores
+
+2018.3.1:
+ * Version 13.2 (Rev. 3)
+ * No changes
+
+2018.3:
+ * Version 13.2 (Rev. 3)
+ * Feature Enhancement: None
+ * Other: Reduced simulation warnings in Behavioral model. No functional changes
+ * Revision change in one or more subcores
+
+2018.2:
+ * Version 13.2 (Rev. 2)
+ * No changes
+
+2018.1:
+ * Version 13.2 (Rev. 2)
+ * Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected
+ * Bug Fix: REQP-1839 DRC warning removed from example test bench
+ * Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected
+ * Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled
+
+2017.4:
+ * Version 13.2 (Rev. 1)
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 13.2
+ * Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected
+ * Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected
+ * Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected
+ * Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected
+ * Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO
+
+2017.2:
+ * Version 13.1 (Rev. 4)
+ * No changes
+
+2017.1:
+ * Version 13.1 (Rev. 4)
+ * Bug Fix: FIFO Generator core was constructing the buit-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure
+ * Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop where it connects to
+ * Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC
+ * Other: Internal device family change, no functional changes
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 13.1 (Rev. 3)
+ * Port Change: None
+ * Bug Fix: Supported features table in the first page of GUI updated to reflect the asymmetry support for common clock BRAM FIFO
+ * Feature Enhancement: None
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 13.1 (Rev. 2)
+ * Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled
+ * Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO
+ * Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options
+ * Other: Added support for future devices
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 13.1 (Rev. 1)
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 13.1
+ * Delivering only Verilog behavioral model.
+ * Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
+ * Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
+ * Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
+ * Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
+ * Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 13.0 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 13.0 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 13.0 (Rev. 1)
+ * Fixed safety circuit related warnings in Behavioral model
+ * Revision change in one or more subcores
+
+2015.3:
+ * Version 13.0
+ * Additional safety circuit option provided for asynchronous reset configurations.
+ * Delivering only VHDL behavioral model.
+ * Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+
+2015.2.1:
+ * Version 12.0 (Rev. 4)
+ * No changes
+
+2015.2:
+ * Version 12.0 (Rev. 4)
+ * No changes
+
+2015.1:
+ * Version 12.0 (Rev. 4)
+ * Delivering  non encrypted behavioral models.
+ * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
+ * Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 12.0 (Rev. 3)
+ * No changes
+
+2014.4:
+ * Version 12.0 (Rev. 3)
+ * Reduced DRC warnings.
+ * Internal device family change, no functional changes
+ * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
+
+2014.3:
+ * Version 12.0 (Rev. 2)
+ * Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
+ * Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
+ * Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
+ * Added support for Low Latency Built-in FIFO for UltraScale devices.
+
+2014.2:
+ * Version 12.0 (Rev. 1)
+ * Repackaged to improve internal automation, no functional changes.
+
+2014.1:
+ * Version 12.0
+ * Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
+ * Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
+ * Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
+ * Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 11.0 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
+ * Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
+ * Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
+
+2013.3:
+ * Version 11.0
+ * AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
+ * AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
+ * Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
+ * Enhanced support for IP Integrator
+ * Reduced warnings in synthesis and simulation
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Improved GUI speed and responsiveness, no functional changes
+ * Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
+
+2013.2:
+ * Version 10.0 (Rev. 1)
+ * Constraints processing order changed
+
+2013.1:
+ * Version 10.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
+(c) Copyright 2002 - 2020 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/sim/MeasDataFifo.v

@@ -0,0 +1,520 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module MeasDataFifo (
+  clk,
+  srst,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 core_clk CLK" *)
+input wire clk;
+input wire srst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
+input wire [255 : 0] din;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
+input wire wr_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
+input wire rd_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
+output wire [255 : 0] dout;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
+output wire full;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
+output wire empty;
+
+  fifo_generator_v13_2_5 #(
+    .C_COMMON_CLOCK(1),
+    .C_SELECT_XPM(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(10),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(256),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(256),
+    .C_ENABLE_RLOCS(0),
+    .C_FAMILY("spartan7"),
+    .C_FULL_FLAGS_RST_VAL(0),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(0),
+    .C_HAS_SRST(1),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(0),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_MEMORY_TYPE(1),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(1),
+    .C_PRELOAD_REGS(0),
+    .C_PRIM_FIFO_TYPE("1kx36"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(1022),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(1021),
+    .C_PROG_FULL_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(10),
+    .C_RD_DEPTH(1024),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(10),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_PIPELINE_REG(0),
+    .C_POWER_SAVING_MODE(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(0),
+    .C_VALID_LOW(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(10),
+    .C_WR_DEPTH(1024),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(10),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_MSGON_VAL(1),
+    .C_ENABLE_RST_SYNC(1),
+    .C_EN_SAFETY_CKT(0),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_HAS_AXI_WR_CHANNEL(1),
+    .C_HAS_AXI_RD_CHANNEL(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_MASTER_CE(0),
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_LEN_WIDTH(8),
+    .C_AXI_LOCK_WIDTH(1),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_HAS_AXIS_TDATA(1),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TUSER(1),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_AXIS_TDATA_WIDTH(8),
+    .C_AXIS_TID_WIDTH(1),
+    .C_AXIS_TDEST_WIDTH(1),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(1),
+    .C_AXIS_TKEEP_WIDTH(1),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WRCH_TYPE(0),
+    .C_RACH_TYPE(0),
+    .C_RDCH_TYPE(0),
+    .C_AXIS_TYPE(0),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_PRIM_FIFO_TYPE_WACH("512x36"),
+    .C_PRIM_FIFO_TYPE_WDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_WRCH("512x36"),
+    .C_PRIM_FIFO_TYPE_RACH("512x36"),
+    .C_PRIM_FIFO_TYPE_RDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_AXIS("1kx18"),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_DIN_WIDTH_WACH(1),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_AXIS(0)
+  ) inst (
+    .backup(1'D0),
+    .backup_marker(1'D0),
+    .clk(clk),
+    .rst(1'D0),
+    .srst(srst),
+    .wr_clk(1'D0),
+    .wr_rst(1'D0),
+    .rd_clk(1'D0),
+    .rd_rst(1'D0),
+    .din(din),
+    .wr_en(wr_en),
+    .rd_en(rd_en),
+    .prog_empty_thresh(10'B0),
+    .prog_empty_thresh_assert(10'B0),
+    .prog_empty_thresh_negate(10'B0),
+    .prog_full_thresh(10'B0),
+    .prog_full_thresh_assert(10'B0),
+    .prog_full_thresh_negate(10'B0),
+    .int_clk(1'D0),
+    .injectdbiterr(1'D0),
+    .injectsbiterr(1'D0),
+    .sleep(1'D0),
+    .dout(dout),
+    .full(full),
+    .almost_full(),
+    .wr_ack(),
+    .overflow(),
+    .empty(empty),
+    .almost_empty(),
+    .valid(),
+    .underflow(),
+    .data_count(),
+    .rd_data_count(),
+    .wr_data_count(),
+    .prog_full(),
+    .prog_empty(),
+    .sbiterr(),
+    .dbiterr(),
+    .wr_rst_busy(),
+    .rd_rst_busy(),
+    .m_aclk(1'D0),
+    .s_aclk(1'D0),
+    .s_aresetn(1'D0),
+    .m_aclk_en(1'D0),
+    .s_aclk_en(1'D0),
+    .s_axi_awid(1'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awlock(1'B0),
+    .s_axi_awcache(4'B0),
+    .s_axi_awprot(3'B0),
+    .s_axi_awqos(4'B0),
+    .s_axi_awregion(4'B0),
+    .s_axi_awuser(1'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wid(1'B0),
+    .s_axi_wdata(64'B0),
+    .s_axi_wstrb(8'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wuser(1'B0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .m_axi_awid(),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awqos(),
+    .m_axi_awregion(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'D0),
+    .m_axi_wid(),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'D0),
+    .m_axi_bid(1'B0),
+    .m_axi_bresp(2'B0),
+    .m_axi_buser(1'B0),
+    .m_axi_bvalid(1'D0),
+    .m_axi_bready(),
+    .s_axi_arid(1'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arlock(1'B0),
+    .s_axi_arcache(4'B0),
+    .s_axi_arprot(3'B0),
+    .s_axi_arqos(4'B0),
+    .s_axi_arregion(4'B0),
+    .s_axi_aruser(1'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .m_axi_arid(),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arqos(),
+    .m_axi_arregion(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'D0),
+    .m_axi_rid(1'B0),
+    .m_axi_rdata(64'B0),
+    .m_axi_rresp(2'B0),
+    .m_axi_rlast(1'D0),
+    .m_axi_ruser(1'B0),
+    .m_axi_rvalid(1'D0),
+    .m_axi_rready(),
+    .s_axis_tvalid(1'D0),
+    .s_axis_tready(),
+    .s_axis_tdata(8'B0),
+    .s_axis_tstrb(1'B0),
+    .s_axis_tkeep(1'B0),
+    .s_axis_tlast(1'D0),
+    .s_axis_tid(1'B0),
+    .s_axis_tdest(1'B0),
+    .s_axis_tuser(4'B0),
+    .m_axis_tvalid(),
+    .m_axis_tready(1'D0),
+    .m_axis_tdata(),
+    .m_axis_tstrb(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(),
+    .axi_aw_injectsbiterr(1'D0),
+    .axi_aw_injectdbiterr(1'D0),
+    .axi_aw_prog_full_thresh(4'B0),
+    .axi_aw_prog_empty_thresh(4'B0),
+    .axi_aw_data_count(),
+    .axi_aw_wr_data_count(),
+    .axi_aw_rd_data_count(),
+    .axi_aw_sbiterr(),
+    .axi_aw_dbiterr(),
+    .axi_aw_overflow(),
+    .axi_aw_underflow(),
+    .axi_aw_prog_full(),
+    .axi_aw_prog_empty(),
+    .axi_w_injectsbiterr(1'D0),
+    .axi_w_injectdbiterr(1'D0),
+    .axi_w_prog_full_thresh(10'B0),
+    .axi_w_prog_empty_thresh(10'B0),
+    .axi_w_data_count(),
+    .axi_w_wr_data_count(),
+    .axi_w_rd_data_count(),
+    .axi_w_sbiterr(),
+    .axi_w_dbiterr(),
+    .axi_w_overflow(),
+    .axi_w_underflow(),
+    .axi_w_prog_full(),
+    .axi_w_prog_empty(),
+    .axi_b_injectsbiterr(1'D0),
+    .axi_b_injectdbiterr(1'D0),
+    .axi_b_prog_full_thresh(4'B0),
+    .axi_b_prog_empty_thresh(4'B0),
+    .axi_b_data_count(),
+    .axi_b_wr_data_count(),
+    .axi_b_rd_data_count(),
+    .axi_b_sbiterr(),
+    .axi_b_dbiterr(),
+    .axi_b_overflow(),
+    .axi_b_underflow(),
+    .axi_b_prog_full(),
+    .axi_b_prog_empty(),
+    .axi_ar_injectsbiterr(1'D0),
+    .axi_ar_injectdbiterr(1'D0),
+    .axi_ar_prog_full_thresh(4'B0),
+    .axi_ar_prog_empty_thresh(4'B0),
+    .axi_ar_data_count(),
+    .axi_ar_wr_data_count(),
+    .axi_ar_rd_data_count(),
+    .axi_ar_sbiterr(),
+    .axi_ar_dbiterr(),
+    .axi_ar_overflow(),
+    .axi_ar_underflow(),
+    .axi_ar_prog_full(),
+    .axi_ar_prog_empty(),
+    .axi_r_injectsbiterr(1'D0),
+    .axi_r_injectdbiterr(1'D0),
+    .axi_r_prog_full_thresh(10'B0),
+    .axi_r_prog_empty_thresh(10'B0),
+    .axi_r_data_count(),
+    .axi_r_wr_data_count(),
+    .axi_r_rd_data_count(),
+    .axi_r_sbiterr(),
+    .axi_r_dbiterr(),
+    .axi_r_overflow(),
+    .axi_r_underflow(),
+    .axi_r_prog_full(),
+    .axi_r_prog_empty(),
+    .axis_injectsbiterr(1'D0),
+    .axis_injectdbiterr(1'D0),
+    .axis_prog_full_thresh(10'B0),
+    .axis_prog_empty_thresh(10'B0),
+    .axis_data_count(),
+    .axis_wr_data_count(),
+    .axis_rd_data_count(),
+    .axis_sbiterr(),
+    .axis_dbiterr(),
+    .axis_overflow(),
+    .axis_underflow(),
+    .axis_prog_full(),
+    .axis_prog_empty()
+  );
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/AdcDataInterface.v

@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:47:44 07/11/2019 
+// design name: 
+// module name:    adc_data_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcDataInterface	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	ChNum			=	4,
+	parameter	Ratio			=	8
+)
+(
+	input	Clk_i,
+	input	RefClk_i,
+	input	Locked_i,
+	input	Rst_i,
+	
+	input	[AdcDataWidth-1:0]	testAdc,
+		
+	input	Adc1FclkP_i,		
+    input	Adc1FclkN_i,		
+	
+    input	Adc1DataDa0P_i,
+	input	Adc1DataDa0N_i,
+    input	Adc1DataDa1P_i,
+    input	Adc1DataDa1N_i,
+	
+	input	Adc1DataDb0P_i,
+    input	Adc1DataDb0N_i,
+    input	Adc1DataDb1P_i,
+    input	Adc1DataDb1N_i,
+		
+	input	Adc2FclkP_i,		
+    input	Adc2FclkN_i,		
+	
+	input	Adc2DataDa0P_i,
+    input	Adc2DataDa0N_i,
+    input	Adc2DataDa1P_i,
+    input	Adc2DataDa1N_i,
+	
+	input	Adc2DataDb0P_i,
+    input	Adc2DataDb0N_i,
+    input	Adc2DataDb1P_i,
+    input	Adc2DataDb1N_i,
+	
+	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
+	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire    [ChNum-1:0]    	adc1P;
+    wire    [ChNum-1:0]    	adc1N;
+    wire    [ChNum-1:0]    	adc2P;
+    wire    [ChNum-1:0]    	adc2N;
+	
+	reg	[AdcDataWidth*2-1:0]	adc1DataSyncPipe	[2:0];
+	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];
+
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1Dout;
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc2Dout;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChAData;
+	wire	[AdcDataWidth-1:0]	adc1ChBData;
+	wire	[AdcDataWidth-1:0]	adc2ChAData;
+	wire	[AdcDataWidth-1:0]	adc2ChBData;	
+	
+	reg		[AdcDataWidth-1:0]	adc1ChT1DataSyncR;	
+	reg		[AdcDataWidth-1:0]	adc1ChR1DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChT2DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChR2DataSyncR;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChT1DataSync;	
+	wire	[AdcDataWidth-1:0]	adc1ChR1DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChT2DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChR2DataSync;
+	
+	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
+	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
+	
+	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
+	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
+	
+	// assign	Adc1ChT1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc1ChR1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth-1-:14];
+	// assign	Adc2ChR2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc2ChT2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth-1-:14];
+	
+	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
+	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
+	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
+	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
+	
+	wire	idly_reset_int;
+	wire	rx_reset;
+	wire	rx2_cmt_locked;
+	wire	Adc1RxClk;
+	wire	Adc2RxClk;
+	
+//================================================================================
+//  instantiations
+//================================================================================
+
+top5x2_7to1_sdr_rx	Adc1Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc1FclkP_i),
+	.clkin1_n	(Adc1FclkN_i),	
+	.datain1_p	(adc1P),	
+	.datain1_n	(adc1N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc1Dout),
+	.DivClk_o	(Adc1RxClk)
+);
+
+top5x2_7to1_sdr_rx	Adc2Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc2FclkP_i),
+	.clkin1_n	(Adc2FclkN_i),	
+	.datain1_p	(adc2P),	
+	.datain1_n	(adc2N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc2Dout),
+	.DivClk_o	(Adc2RxClk)
+);
+
+
+AdcSync Adc1Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc1Dout),
+	
+	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
+);
+
+AdcSync Adc2Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc2Dout),
+	
+	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
+);
+
+// AdcSyncFifo	adc1SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc1RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc1Dout),
+	// .din		({testAdc,testAdc}),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc1ChT1DataSync, adc1ChR1DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+
+// AdcSyncFifo	adc2SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc2RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc2Dout),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc2ChR2DataSync, adc2ChT2DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+endmodule
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/AdcSync.v

@@ -0,0 +1,41 @@
+module AdcSync 
+#(	
+	parameter	AdcDataWidth	=	14
+)
+(
+    input	Clk_i,
+	input	Rst_i,
+	
+    input	[AdcDataWidth*2-1:0]	Data_i,
+	
+	output	[AdcDataWidth*2-1:0]	Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	reg	[AdcDataWidth*2-1:0]	adcDataSyncPipe	[2:0];
+	integer i;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Data_o	=	adcDataSyncPipe[2];
+//================================================================================
+//  CODING
+//================================================================================
+
+
+always @(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		adcDataSyncPipe[0]  <= Data_i;
+		for(i=1; i<3; i=i+1) begin
+			adcDataSyncPipe	[i]<=adcDataSyncPipe[i-1];
+		end
+	end	else	begin
+		adcDataSyncPipe	[i]	<=	0;
+	end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/delay_controller_wrap.v

@@ -0,0 +1,410 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: delay_controller_wrap.v
+//  /   /        Date Last Modified: 21JAN2015
+// /___/   /\    Date Created: 8JAN2013
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Controls delays on a per-bit basis
+//		Number of bits from each seres set via an attribute
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module delay_controller_wrap (m_datain, s_datain, enable_phase_detector, enable_monitor, reset, clk, c_delay_in, m_delay_out, s_delay_out, data_out, bt_val, results, m_delay_1hot, del_mech) ;
+
+parameter integer 	S = 4 ;   			// Set the number of bits
+
+input		[S-1:0]	m_datain ;			// Inputs from master serdes
+input		[S-1:0]	s_datain ;			// Inputs from slave serdes
+input			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the eye monitoring logic when high
+input			reset ;				// Reset line synchronous to clk 
+input			clk ;				// Global/Regional clock 
+input		[4:0]	c_delay_in ;			// delay value found on clock line
+output		[4:0]	m_delay_out ;			// Master delay control value
+output		[4:0]	s_delay_out ;			// Master delay control value
+output	reg	[S-1:0]	data_out ;			// Output data
+input		[4:0]	bt_val ;			// Calculated bit time value for slave devices
+output	reg	[31:0]	results ;			// eye monitor result data	
+output	reg	[31:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector	
+input			del_mech ;			// changes delay mechanism slightly at higher bit rates
+
+reg	[S-1:0]		mdataouta ;		
+reg			mdataoutb ;		
+reg	[S-1:0]		mdataoutc ;		
+reg	[S-1:0]		sdataouta ;		
+reg			sdataoutb ;		
+reg	[S-1:0]		sdataoutc ;		
+reg			s_ovflw ; 		
+reg	[1:0]		m_delay_mux ;				
+reg	[1:0]		s_delay_mux ;				
+reg			data_mux ;		
+reg			dec_run ;			
+reg			inc_run ;			
+reg			eye_run ;			
+reg	[4:0]		s_state ;					
+reg	[5:0]		pdcount ;					
+reg	[4:0]		m_delay_val_int ;	
+reg	[4:0]		s_delay_val_int ;	
+reg	[4:0]		s_delay_val_eye ;	
+reg			meq_max	;		
+reg			meq_min	;		
+reg			pd_max	;		
+reg			pd_min	;		
+reg			delay_change ;		
+wire	[S-1:0]		all_high ;		
+wire	[S-1:0]		all_low	;		
+wire	[7:0]		msxoria	;		
+wire	[7:0]		msxorda	;		
+reg	[1:0]		action	;		
+reg	[1:0]		msxor_cti ;
+reg	[1:0]		msxor_ctd ;
+reg	[1:0]		msxor_ctix ;
+reg	[1:0]		msxor_ctdx ;
+wire	[2:0]		msxor_ctiy ;
+wire	[2:0]		msxor_ctdy ;
+reg	[7:0]		match ;	
+reg	[31:0]		shifter ;	
+reg	[7:0]		pd_hold ;	
+	
+assign m_delay_out = m_delay_val_int ;
+assign s_delay_out = s_delay_val_int ;
+genvar i ;
+
+generate
+
+for (i = 0 ; i <= S-2 ; i = i+1) begin : loop0
+
+assign msxoria[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i]))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i+1])))) ; // early bits                   
+assign msxorda[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i])))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i+1]))) ;	// late bits
+end 
+endgenerate
+
+assign msxoria[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataoutb)    | (~mdataoutb & mdataouta[0] &  sdataoutb))) | 			// first early bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataouta[0]) | (~mdataoutb & mdataouta[0] &  sdataouta[0])))) ;
+assign msxorda[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataoutb)    | (~mdataoutb & mdataouta[0] & ~sdataoutb)))) | 			// first late bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataouta[0]) | (~mdataoutb & mdataouta[0] & ~sdataouta[0]))) ;
+
+always @ (posedge clk) begin				// generate number of incs or decs for low 4 bits
+	case (msxoria[3:0])
+		4'h0    : msxor_cti <= 2'h0 ;
+		4'h1    : msxor_cti <= 2'h1 ;
+		4'h2    : msxor_cti <= 2'h1 ;
+		4'h3    : msxor_cti <= 2'h2 ;
+		4'h4    : msxor_cti <= 2'h1 ;
+		4'h5    : msxor_cti <= 2'h2 ;
+		4'h6    : msxor_cti <= 2'h2 ;
+		4'h8    : msxor_cti <= 2'h1 ;
+		4'h9    : msxor_cti <= 2'h2 ;
+		4'hA    : msxor_cti <= 2'h2 ;
+		4'hC    : msxor_cti <= 2'h2 ;
+		default : msxor_cti <= 2'h3 ;
+	endcase
+	case (msxorda[3:0])
+		4'h0    : msxor_ctd <= 2'h0 ;
+		4'h1    : msxor_ctd <= 2'h1 ;
+		4'h2    : msxor_ctd <= 2'h1 ;
+		4'h3    : msxor_ctd <= 2'h2 ;
+		4'h4    : msxor_ctd <= 2'h1 ;
+		4'h5    : msxor_ctd <= 2'h2 ;
+		4'h6    : msxor_ctd <= 2'h2 ;
+		4'h8    : msxor_ctd <= 2'h1 ;
+		4'h9    : msxor_ctd <= 2'h2 ;
+		4'hA    : msxor_ctd <= 2'h2 ;
+		4'hC    : msxor_ctd <= 2'h2 ;
+		default : msxor_ctd <= 2'h3 ;
+	endcase
+	case (msxoria[7:4])				// generate number of incs or decs for high n bits, max 4
+		4'h0    : msxor_ctix <= 2'h0 ;
+		4'h1    : msxor_ctix <= 2'h1 ;
+		4'h2    : msxor_ctix <= 2'h1 ;
+		4'h3    : msxor_ctix <= 2'h2 ;
+		4'h4    : msxor_ctix <= 2'h1 ;
+		4'h5    : msxor_ctix <= 2'h2 ;
+		4'h6    : msxor_ctix <= 2'h2 ;
+		4'h8    : msxor_ctix <= 2'h1 ;
+		4'h9    : msxor_ctix <= 2'h2 ;
+		4'hA    : msxor_ctix <= 2'h2 ;
+		4'hC    : msxor_ctix <= 2'h2 ;
+		default : msxor_ctix <= 2'h3 ;
+	endcase
+	case (msxorda[7:4])
+		4'h0    : msxor_ctdx <= 2'h0 ;
+		4'h1    : msxor_ctdx <= 2'h1 ;
+		4'h2    : msxor_ctdx <= 2'h1 ;
+		4'h3    : msxor_ctdx <= 2'h2 ;
+		4'h4    : msxor_ctdx <= 2'h1 ;
+		4'h5    : msxor_ctdx <= 2'h2 ;
+		4'h6    : msxor_ctdx <= 2'h2 ;
+		4'h8    : msxor_ctdx <= 2'h1 ;
+		4'h9    : msxor_ctdx <= 2'h2 ;
+		4'hA    : msxor_ctdx <= 2'h2 ;
+		4'hC    : msxor_ctdx <= 2'h2 ;
+		default : msxor_ctdx <= 2'h3 ;
+	endcase
+end
+
+assign msxor_ctiy = {1'b0, msxor_cti} + {1'b0, msxor_ctix} ;
+assign msxor_ctdy = {1'b0, msxor_ctd} + {1'b0, msxor_ctdx} ;
+
+always @ (posedge clk) begin
+	if (msxor_ctiy == msxor_ctdy) begin
+		action <= 2'h0 ;
+	end
+	else if (msxor_ctiy > msxor_ctdy) begin
+		action <= 2'h1 ;
+	end 
+	else begin
+		action <= 2'h2 ;
+	end
+end
+		       	       
+generate
+for (i = 0 ; i <= S-1 ; i = i+1) begin : loop1
+assign all_high[i] = 1'b1 ;
+assign all_low[i] = 1'b0 ;
+end 
+endgenerate
+
+always @ (posedge clk) begin
+	mdataouta <= m_datain ;
+	mdataoutb <= mdataouta[S-1] ;
+	sdataouta <= s_datain ;
+	sdataoutb <= sdataouta[S-1] ;
+end
+	
+always @ (posedge clk) begin
+	if (reset == 1'b1) begin
+		s_ovflw <= 1'b0 ;
+		pdcount <= 6'b100000 ;
+		m_delay_val_int <= c_delay_in ; 			// initial master delay
+		s_delay_val_int <= c_delay_in ; 			// initial slave delay
+		data_mux <= 1'b0 ;
+		m_delay_mux <= 2'b01 ;
+		s_delay_mux <= 2'b01 ;
+		s_state <= 5'b00000 ;
+		inc_run <= 1'b0 ;
+		dec_run <= 1'b0 ;
+		eye_run <= 1'b0 ;
+		s_delay_val_eye <= 5'h00 ;
+		shifter <= 32'h00000001 ;
+		delay_change <= 1'b0 ;
+		results <= 32'h00000000 ;
+		pd_hold <= 8'h00 ;
+	end
+	else begin
+		case (m_delay_mux)
+			2'b00   : mdataoutc <= {mdataouta[S-2:0], mdataoutb} ;
+			2'b10   : mdataoutc <= {m_datain[0],      mdataouta[S-1:1]} ;
+			default : mdataoutc <= mdataouta ;
+		endcase 
+		case (s_delay_mux)  
+			2'b00   : sdataoutc <= {sdataouta[S-2:0], sdataoutb} ;
+			2'b10   : sdataoutc <= {s_datain[0],      sdataouta[S-1:1]} ;
+			default : sdataoutc <= sdataouta ;
+		endcase
+		if (m_delay_val_int == bt_val) begin
+			meq_max <= 1'b1 ;
+		end else begin 
+			meq_max <= 1'b0 ;
+		end 
+		if (m_delay_val_int == 5'h00) begin
+			meq_min <= 1'b1 ;
+		end else begin 
+			meq_min <= 1'b0 ;
+		end 
+		if (pdcount == 6'h3F && pd_max == 1'b0 && delay_change == 1'b0) begin
+			pd_max <= 1'b1 ;
+		end else begin 
+			pd_max <= 1'b0 ;
+		end 
+		if (pdcount == 6'h00 && pd_min == 1'b0 && delay_change == 1'b0) begin
+			pd_min <= 1'b1 ;
+		end else begin 
+			pd_min <= 1'b0 ;
+		end
+		if (delay_change == 1'b1 || inc_run == 1'b1 || dec_run == 1'b1 || eye_run == 1'b1) begin
+			pd_hold <= 8'hFF ;
+			pdcount <= 6'b100000 ; 
+		end													// increment filter count
+		else if (pd_hold[7] == 1'b1) begin
+			pdcount <= 6'b100000 ; 
+			pd_hold <= {pd_hold[6:0], 1'b0} ;
+		end
+		else if (action[0] == 1'b1 && pdcount != 6'b111111) begin 
+			pdcount <= pdcount + 6'h01 ; 
+		end													// decrement filter count
+		else if (action[1] == 1'b1 && pdcount != 6'b000000) begin 
+			pdcount <= pdcount - 6'h01 ; 
+		end
+		if ((enable_phase_detector == 1'b1 && pd_max == 1'b1 && delay_change == 1'b0) || inc_run == 1'b1) begin					// increment delays, check for master delay = max
+			delay_change <= 1'b1 ;
+			if (meq_max == 1'b0 && inc_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int + 5'h01 ;
+			end 
+			else begin											// master is max
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin inc_run <= 1'b1 ; s_delay_val_int <= bt_val ; end			// indicate state machine running and set slave delay to bit time 
+				4'b0110 : begin data_mux <= 1'b1 ; m_delay_val_int <= 5'b00000 ; end			// change data mux over to forward slave data and set master delay to zero
+				4'b1001 : begin m_delay_mux <= m_delay_mux - 2'h1 ; end 				// change delay mux over to forward with a 1-bit less advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; inc_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin inc_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if ((enable_phase_detector == 1'b1 && pd_min == 1'b1 && delay_change == 1'b0) || dec_run == 1'b1) begin				// decrement delays, check for master delay = 0
+			delay_change <= 1'b1 ;
+			if (meq_min == 1'b0 && dec_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int - 5'h01 ;
+			end
+			else begin 											// master is zero
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin dec_run <= 1'b1 ; s_delay_val_int <= 5'b00000 ; end			// indicate state machine running and set slave delay to zero 
+				4'b0110 : begin data_mux <= 1'b1 ;  m_delay_val_int <= bt_val ;	end			// change data mux over to forward slave data and set master delay to bit time 
+				4'b1001 : begin m_delay_mux <= m_delay_mux + 2'h1 ; end  				// change delay mux over to forward with a 1-bit more advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; dec_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin dec_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if (enable_monitor == 1'b1 && (eye_run == 1'b1 || delay_change == 1'b1)) begin
+			delay_change <= 1'b0 ;
+			s_state <= s_state + 5'h01 ;
+			case (s_state) 
+				5'b00000 : begin eye_run <= 1'b1 ; s_delay_val_int <= s_delay_val_eye ; end						// indicate state machine running and set slave delay to monitor value 
+				5'b10110 : begin 
+				           if (match == 8'hFF) begin results <= results | shifter ; end			//. set or clear result bit
+				           else begin results <= results & ~shifter ; end 							 
+				           if (s_delay_val_eye == bt_val) begin 					// only monitor active taps, ie as far as btval
+				          	shifter <= 32'h00000001 ; s_delay_val_eye <= 5'h00 ; end
+				           else begin shifter <= {shifter[30:0], shifter[31]} ; 
+				          	s_delay_val_eye <= s_delay_val_eye + 5'h01 ; end			// 
+				          	eye_run <= 1'b0 ; s_state <= 5'h00 ; end
+				default :  begin eye_run <= 1'b1 ; end
+			endcase 
+		end
+		else begin
+			delay_change <= 1'b0 ;
+			if (m_delay_val_int >= {1'b0, bt_val[4:1]} &&  del_mech == 1'b0) begin 						// set slave delay to 1/2 bit period beyond or behind the master delay
+				s_delay_val_int <= m_delay_val_int - {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b0 ;
+			end
+			else begin
+				s_delay_val_int <= m_delay_val_int + {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b1 ;
+			end 
+		end 
+		if (enable_phase_detector == 1'b0 && delay_change == 1'b0) begin
+			delay_change <= 1'b1 ;
+		end
+	end
+	if (enable_phase_detector == 1'b1) begin
+		if (data_mux == 1'b0) begin
+			data_out <= mdataoutc ;
+		end else begin 
+			data_out <= sdataoutc ;
+		end
+	end
+	else begin
+		data_out <= m_datain ;	
+	end
+end
+
+always @ (posedge clk) begin
+	if ((mdataouta == sdataouta)) begin
+		match <= {match[6:0], 1'b1} ;
+	end else begin
+		match <= {match[6:0], 1'b0} ;
+	end
+end
+
+always @ (m_delay_val_int) begin
+	case (m_delay_val_int)
+	    	5'b00000	: m_delay_1hot <= 32'h00000001 ;
+	    	5'b00001	: m_delay_1hot <= 32'h00000002 ;
+	    	5'b00010	: m_delay_1hot <= 32'h00000004 ;
+	    	5'b00011	: m_delay_1hot <= 32'h00000008 ;
+	    	5'b00100	: m_delay_1hot <= 32'h00000010 ;
+	    	5'b00101	: m_delay_1hot <= 32'h00000020 ;
+	    	5'b00110	: m_delay_1hot <= 32'h00000040 ;
+	    	5'b00111	: m_delay_1hot <= 32'h00000080 ;
+	    	5'b01000	: m_delay_1hot <= 32'h00000100 ;
+	    	5'b01001	: m_delay_1hot <= 32'h00000200 ;
+	    	5'b01010	: m_delay_1hot <= 32'h00000400 ;
+	    	5'b01011	: m_delay_1hot <= 32'h00000800 ;
+	    	5'b01100	: m_delay_1hot <= 32'h00001000 ;
+	    	5'b01101	: m_delay_1hot <= 32'h00002000 ;
+	    	5'b01110	: m_delay_1hot <= 32'h00004000 ;
+	    	5'b01111	: m_delay_1hot <= 32'h00008000 ;
+            	5'b10000	: m_delay_1hot <= 32'h00010000 ;
+            	5'b10001	: m_delay_1hot <= 32'h00020000 ;
+            	5'b10010	: m_delay_1hot <= 32'h00040000 ;
+            	5'b10011	: m_delay_1hot <= 32'h00080000 ;
+            	5'b10100	: m_delay_1hot <= 32'h00100000 ;
+            	5'b10101	: m_delay_1hot <= 32'h00200000 ;
+            	5'b10110	: m_delay_1hot <= 32'h00400000 ;
+            	5'b10111	: m_delay_1hot <= 32'h00800000 ;
+            	5'b11000	: m_delay_1hot <= 32'h01000000 ;
+            	5'b11001	: m_delay_1hot <= 32'h02000000 ;
+            	5'b11010	: m_delay_1hot <= 32'h04000000 ;
+            	5'b11011	: m_delay_1hot <= 32'h08000000 ;
+            	5'b11100	: m_delay_1hot <= 32'h10000000 ;
+            	5'b11101	: m_delay_1hot <= 32'h20000000 ;
+            	5'b11110	: m_delay_1hot <= 32'h40000000 ;
+            	default		: m_delay_1hot <= 32'h80000000 ; 
+         endcase
+end
+   	
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,169 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: n_x_serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Wrapper for multiple 1 to 7 SDR clock and data receiver using one PLL/MMCM for clock multiplication
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - Generate loop changed to correct problem when only one channel
+//    Rev 1.2 - Eye monitoring added, upated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module n_x_serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div, 
+                                          rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, eye_info, m_delay_1hot) ;
+
+parameter integer 	N = 8 ;				// Set the number of channels
+parameter integer 	D = 6 ;   			// Parameter to set the number of data lines per channel
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set pixel clock buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, overides SAMPL_CLOCK and INTER_CLOCK to be both BUFH
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 	[N-1:0]		clkin_p ;			// Input from LVDS clock receiver pin
+input 	[N-1:0]		clkin_n ;			// Input from LVDS clock receiver pin
+input 	[N*D-1:0]	datain_p ;			// Input from LVDS clock data pins
+input 	[N*D-1:0]	datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_d4
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_d4
+output 	[N-1:0]		rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[N*7-1:0]	clk_data ;	 		// Clock Data
+output 	[N*D*7-1:0]	rx_data ;	 		// Received Data
+output 	[(10*D+6)*N-1:0]debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, for example 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	[32*D*N-1:0]	eye_info ;			// Eye info
+output	[32*D*N-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire			rxclk_d4 ;
+wire			pd ;
+
+serdes_1_to_7_mmcm_idelay_sdr #(
+	.SAMPL_CLOCK		(SAMPL_CLOCK),
+	.PIXEL_CLOCK		(PIXEL_CLOCK),
+	.USE_PLL		(USE_PLL),
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.D			(D),				// Number of data lines
+      	.CLKIN_PERIOD		(CLKIN_PERIOD),			// Set input clock period
+      	.MMCM_MODE		(MMCM_MODE),			// Set mmcm vco, either 1 or 2
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rx0 (
+	.clkin_p   		(clkin_p[0]),
+	.clkin_n   		(clkin_n[0]),
+	.datain_p     		(datain_p[D-1:0]),
+	.datain_n     		(datain_n[D-1:0]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(rxclk_div),
+	.reset     		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs[0]),
+	.clk_data  		(clk_data[6:0]),
+	.rx_data		(rx_data[7*D-1:0]),
+	.bit_rate_value		(bit_rate_value),
+	.bit_time_value		(bit_time_value),
+	.status			(status),
+	.eye_info		(eye_info[32*D-1:0]),
+	.rst_iserdes		(rst_iserdes),
+	.m_delay_1hot		(m_delay_1hot[32*D-1:0]),
+	.debug			(debug[10*D+5:0])
+	);
+
+genvar i ;
+genvar j ;
+
+generate
+if (N > 1) begin
+for (i = 1 ; i <= (N-1) ; i = i+1)
+begin : loop0
+
+serdes_1_to_7_slave_idelay_sdr #(
+      	.D			(D),				// Number of data lines
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rxn (
+	.clkin_p   		(clkin_p[i]),
+	.clkin_n   		(clkin_n[i]),
+	.datain_p     		(datain_p[D*(i+1)-1:D*i]),
+	.datain_n     		(datain_n[D*(i+1)-1:D*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(),
+	.reset     		(~rx_mmcm_lckdps),
+	.bitslip_finished	(rx_mmcm_lckdpsbs[i]),
+	.clk_data  		(clk_data[7*i+6:7*i]),
+	.rx_data		(rx_data[(D*(i+1)*7)-1:D*i*7]),
+	.bit_time_value		(bit_time_value),
+	.eye_info		(eye_info[32*D*(i+1)-1:32*D*i]),
+	.m_delay_1hot		(m_delay_1hot[(32*D)*(i+1)-1:(32*D)*i]),
+	.rst_iserdes		(rst_iserdes),
+	.debug			(debug[(10*D+6)*(i+1)-1:(10*D+6)*i]));
+
+end
+end
+endgenerate
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,718 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+//
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver clock and data receiver using an MMCM for clock multiplication
+//		Data formatting is set by the DATA_FORMAT parameter.
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer:
+//
+//		This disclaimer is not a license and does not grant any rights to the materials
+//              distributed herewith. Except as otherwise provided in a valid license issued to you
+//              by Xilinx, and to the maximum extent permitted by applicable law:
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage
+//              of any kind or nature related to, arising under or in connection with these materials,
+//              including for any direct, or any indirect, special, incidental, or consequential loss
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
+//              as a result of any action brought by a third party) even if such damage or loss was
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application
+//		requiring fail-safe performance, such as life-support or safety devices or systems,
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div,
+                                      rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set final pixel buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, note, PLL does not support BUFIO and BUFR
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_div
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_div
+output 			rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status info
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, eg 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	reg		rst_iserdes ;			// serdes reset signal
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+reg	[1:0]		bsstate ;
+reg 			bslip ;
+reg	[3:0]		bcount ;
+wire 	[6:0] 		clk_iserdes_data ;
+reg 	[6:0] 		clk_iserdes_data_d ;
+reg 			enable ;
+reg 			flag1 ;
+reg 			flag2 ;
+reg 	[2:0] 		state2 ;
+reg 	[4:0] 		state2_count ;
+reg 	[5:0] 		scount ;
+reg 			locked_out ;
+reg			chfound ;
+reg			chfoundc ;
+reg			not_rx_mmcm_lckd_int ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		c_delay_in_target ;
+reg			c_delay_in_ud ;
+wire 	[D-1:0]		rx_data_in_p ;
+wire 	[D-1:0]		rx_data_in_n ;
+wire 	[D-1:0]		rx_data_in_m ;
+wire 	[D-1:0]		rx_data_in_s ;
+wire 	[D-1:0]		rx_data_in_md ;
+wire 	[D-1:0]		rx_data_in_sd ;
+wire	[(7*D)-1:0] 	mdataout ;
+wire	[(7*D)-1:0] 	mdataoutd ;
+wire	[(7*D)-1:0] 	sdataout ;
+reg			data_different ;
+reg			bs_finished ;
+reg			not_bs_finished ;
+reg	[4:0]		bt_val ;
+wire			mmcm_locked ;
+wire			rx_mmcmout_x1 ;
+wire			rx_mmcmout_xs ;
+reg			rstcserdes ;
+reg	[1:0]		c_loop_cnt ;
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign rx_mmcm_lckdpsbs = bs_finished & mmcm_locked ;
+assign rx_mmcm_lckd = ~not_rx_mmcm_lckd_int & mmcm_locked ;
+assign rx_mmcm_lckdps = ~not_rx_mmcm_lckd_int & locked_out & mmcm_locked ;
+assign bit_time_value = bt_val ;
+
+always @ (bit_rate_value) begin			// Generate tap number to be used for input bit rate
+	if      (bit_rate_value > 16'h1068) begin bt_val <= 5'h0C ; end
+	else if (bit_rate_value > 16'h0986) begin bt_val <= 5'h0D ; end
+	else if (bit_rate_value > 16'h0916) begin bt_val <= 5'h0E ; end
+	else if (bit_rate_value > 16'h0855) begin bt_val <= 5'h0F ; end
+	else if (bit_rate_value > 16'h0801) begin bt_val <= 5'h10 ; end
+	else if (bit_rate_value > 16'h0754) begin bt_val <= 5'h11 ; end
+	else if (bit_rate_value > 16'h0712) begin bt_val <= 5'h12 ; end
+	else if (bit_rate_value > 16'h0675) begin bt_val <= 5'h13 ; end
+	else if (bit_rate_value > 16'h0641) begin bt_val <= 5'h14 ; end
+	else if (bit_rate_value > 16'h0611) begin bt_val <= 5'h15 ; end
+	else if (bit_rate_value > 16'h0583) begin bt_val <= 5'h16 ; end
+	else if (bit_rate_value > 16'h0557) begin bt_val <= 5'h17 ; end
+	else if (bit_rate_value > 16'h0534) begin bt_val <= 5'h18 ; end
+	else if (bit_rate_value > 16'h0513) begin bt_val <= 5'h19 ; end
+	else if (bit_rate_value > 16'h0493) begin bt_val <= 5'h1A ; end
+	else if (bit_rate_value > 16'h0475) begin bt_val <= 5'h1B ; end
+	else if (bit_rate_value > 16'h0458) begin bt_val <= 5'h1C ; end
+	else if (bit_rate_value > 16'h0442) begin bt_val <= 5'h1D ; end
+	else if (bit_rate_value > 16'h0427) begin bt_val <= 5'h1E ; end
+	else                                begin bt_val <= 5'h1F ; end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1111111) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b0000000) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin
+     		   	bslip <= 1'b0 ;
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input
+
+IBUFGDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM),
+	.IBUF_LOW_PWR		("FALSE"))
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in_p),
+	.OB         		(rx_clk_in_n));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(
+	.DATAOUT		(rx_clkin_p_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in_p),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cs(
+	.DATAOUT		(rx_clk_in_n_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(~rx_clk_in_n),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		({1'b0, bt_val[4:1]}),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_n_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rstcserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());
+
+generate
+if (USE_PLL == "FALSE") begin : loop8					// use an MMCM
+assign status[6] = 1'b1 ;
+
+MMCME2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),  		
+      	.CLKFBOUT_MULT_F	(7*MMCM_MODE),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE_F	(1*MMCM_MODE),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+	.CLKOUT0_USE_FINE_PS	("FALSE"),
+      	.CLKOUT1_DIVIDE		(6*MMCM_MODE),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(22.5),
+	.CLKOUT1_USE_FINE_PS	("FALSE"),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+	.CLKOUT2_USE_FINE_PS	("FALSE"),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_mmcm_adv_inst (
+      	.CLKFBOUT		(rx_mmcmout_x1),
+      	.CLKFBOUTB		(),
+      	.CLKFBSTOPPED		(),
+      	.CLKINSTOPPED		(),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT0B		(),
+      	.CLKOUT1		(),
+      	.CLKOUT1B		(),
+      	.CLKOUT2		(),
+      	.CLKOUT2B		(),
+      	.CLKOUT3		(),
+      	.CLKOUT3B		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.CLKOUT6		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PSDONE			(),
+      	.PSCLK			(1'b0),
+      	.PSEN			(1'b0),
+      	.PSINCDEC		(1'b0),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(rxclk_div),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_mmcm_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_mmcm_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+else begin
+assign status[6] = 1'b0 ;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(42),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE		(3),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(21),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_plle2_adv_inst (
+      	.CLKFBOUT		(rx_mmcmFb),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT1		(rx_mmcmout_x1),
+      	.CLKOUT2		(),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(ClkFb),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+	  BUFG	bufg_pll_fb (.I(rx_mmcmFb), .O(ClkFb)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_pll_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_pll_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+endgenerate
+
+always @ (posedge rxclk_div) begin				//
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+end
+
+always @ (posedge rxclk_div) begin						// clock delay shift state machine
+	not_rx_mmcm_lckd_int <= ~(mmcm_locked & idelay_rdy) ;
+	rstcserdes <= not_rx_mmcm_lckd_int | rst_iserdes ;
+	if (not_rx_mmcm_lckd_int == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 5'h00 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		c_delay_in <= bt_val ;							// Start the delay line at the current bit period
+		rst_iserdes <= 1'b0 ;
+		c_loop_cnt <= 2'b00 ;
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			scount <= scount + 6'h01 ;
+		end
+		state2_count <= state2_count + 5'h01 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 5'h1F && scount[5] == 1'b1)) begin
+			case(state2)
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;
+					state2 <= 1 ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in_target <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in_target <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			2 	: begin
+				  if (c_delay_in == c_delay_in_target) begin
+				   	state2 <= 3 ;
+				  end
+				  else begin
+				   	if (c_delay_in_ud == 1'b1) begin		// move gently to end position to stop MMCM unlocking
+						c_delay_in <= c_delay_in + 5'h01 ;
+				   		c_delay_in_ud <= 1'b1 ;
+				   	end
+				   	else begin
+						c_delay_in <= c_delay_in - 5'h01 ;
+				   		c_delay_in_ud <= 1'b0 ;
+				   	end
+				  end
+				  end
+			3 	: begin rst_iserdes <= 1'b1 ; state2 <= 4 ; end		// remove serdes reset
+			default	: begin							// issue locked out signal
+				  rst_iserdes <= 1'b0 ;  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		({1'b0, bt_val[4:1]}),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM))
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("SLAVE"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v

@@ -0,0 +1,495 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_slave_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver slave data receiver
+//		Data formatting is set by the DATA_FORMAT parameter. 
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_slave_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, idelay_rdy, rxclk, reset, rxclk_div, 
+                                       bitslip_finished, clk_data, rx_data, debug, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input			idelay_rdy ;			// input delays are ready
+input 			reset ;				// Reset line
+input 			rxclk ;				// Global/BUFIO rx clock network
+input 			rxclk_div ;			// Global/Regional clock input
+output 			bitslip_finished ;	 	// bitslipping finished
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+input	[4:0]		bit_time_value ;		// Calculated bit time value from 'master'
+input			rst_iserdes ;			// reset serdes input
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+wire			rx_clk_in ;			
+reg	[1:0]		bsstate ;                 	
+reg 			bslip ;                 	
+reg 			bslipreq ;                 	
+reg 			bslipr ;                 	
+reg	[3:0]		bcount ;                 	
+wire 	[6:0] 		clk_iserdes_data ;      	
+reg 	[6:0] 		clk_iserdes_data_d ;    	
+reg 			enable ;                	
+reg 			flag1 ;                 	
+reg 			flag2 ;                 	
+reg 	[2:0] 		state2 ;			
+reg 	[3:0] 		state2_count ;			
+reg 	[5:0] 		scount ;			
+reg 			locked_out ;	
+reg 			locked_out_rt ;	
+reg			chfound ;	
+reg			chfoundc ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		old_c_delay_in ;
+reg			local_reset ;
+wire 	[D-1:0]		rx_data_in_p ;			
+wire 	[D-1:0]		rx_data_in_n ;			
+wire 	[D-1:0]		rx_data_in_m ;			
+wire 	[D-1:0]		rx_data_in_s ;		
+wire 	[D-1:0]		rx_data_in_md ;			
+wire 	[D-1:0]		rx_data_in_sd ;	
+wire	[(7*D)-1:0] 	mdataout ;						
+wire	[(7*D)-1:0] 	mdataoutd ;			
+wire	[(7*D)-1:0] 	sdataout ;						
+reg			bslip_ackr ;		
+reg			bslip_ack ;		
+reg	[1:0]		bstate ;
+reg			data_different ;		
+reg			bs_finished ;
+reg			not_bs_finished ;
+wire	[4:0]		bt_val ;
+reg	[D*4-1:0]	s_state ;                 			
+reg			retry ;
+reg			no_clock ;
+reg	[1:0]		c_loop_cnt ;  
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign bitslip_finished = bs_finished & ~reset ;
+assign bt_val = bit_time_value ;
+
+always @ (posedge rxclk_div or posedge reset) begin	// generate local sync (rxclk_div) reset
+if (reset == 1'b1 || retry == 1'b1) begin
+	local_reset <= 1'b1 ;
+end
+else begin
+	if (idelay_rdy == 1'b0) begin
+		local_reset <= 1'b1 ;
+	end
+	else begin
+		local_reset <= 1'b0 ;
+	end
+end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+	retry <= 1'b0 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin				
+     		   	bslip <= 1'b0 ; 
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input 
+
+IBUFGDS #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(               	
+	.DATAOUT		(rx_clk_in_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 				
+	.DATA_RATE      	("SDR"), 			
+	.SERDES_MODE    	("MASTER"), 			
+	.IOBDELAY	    	("IFD"), 			
+	.INTERFACE_TYPE 	("NETWORKING")) 		
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(local_reset),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());	
+
+always @ (posedge rxclk_div) begin				// 
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+	if ((clk_iserdes_data == 7'h00) || (clk_iserdes_data == 7'h7F)) begin
+		no_clock <= 1'b1 ;
+	end
+	else begin
+		no_clock <= 1'b0 ;
+	end
+end
+	
+always @ (posedge rxclk_div) begin					// clock delay shift state machine
+	if (local_reset == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 4'h0 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		chfound <= 1'b0 ;
+		c_delay_in <= bt_val ;						// Start the delay line at the current bit period
+		c_loop_cnt <= 2'b00 ;	
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			if (no_clock == 1'b0) begin
+				scount <= scount + 6'h01 ;
+			end
+			else begin
+				scount <= 6'h00 ;
+			end
+		end
+		state2_count <= state2_count + 4'h1 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 4'hF && scount[5] == 1'b1)) begin
+			case(state2) 					
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;				// change found
+					state2 <= 1 ;
+					c_delay_in <= old_c_delay_in ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					old_c_delay_in <= c_delay_in ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			default	: begin							// issue locked out signal
+				  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+			
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (                       
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		(c_delay_in),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers 
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(               	
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+		
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+	.SERDES_MODE    	("MASTER"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(               	
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+//	.SERDES_MODE    	("SLAVE"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end 
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/top5x2_7to1_sdr_rx.v

@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: top5x2_7to1_sdr_rx.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 2SEP2011
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7-Series
+//Purpose:  	SDR top level receiver example - 2 channels of 5-bits each
+//
+//Reference:	XAPP585.pdf
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - BUFG added to IDELAY reference clock
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module top5x2_7to1_sdr_rx 
+#(
+	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
+	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
+	parameter	DataWidth	=	14
+)
+(
+	input	reset,					// reset (active high)
+	input	refclkin,				// Reference clock for input delay control
+	input	Locked_i,				// Reference clock for input delay control
+	input	clkin1_p,	
+	input	clkin1_n,			// lvds channel 1 clock input
+	input	[D-1:0]	datain1_p,
+	input	[D-1:0]	datain1_n,			// lvds channel 1 data inputs
+	input	clkin2_p,	
+	input	clkin2_n,			// lvds channel 2 clock input
+	input	[D-1:0]	datain2_p,	
+	input	[D-1:0]	datain2_n,			// lvds channel 2 data inputs
+	output	reg	dummy,
+	output	[27:0]	dout,
+	output	DivClk_o
+	// output	[DataWidth-1:0]	dout
+);// Dummy output for test
+			
+		
+wire	refclkint; 		
+wire	rx_mmcm_lckdps;		
+wire	[1:0]	rx_mmcm_lckdpsbs;	
+wire	rxclk_div;		
+wire	clkin_p;			
+wire	clkin_n;			
+wire	[D*N-1:0]	datain_p;		
+wire	[D*N-1:0]	datain_n;		
+// wire	[N*DataWidth-1:0]	rxdall;			
+wire	[27:0]	rxdall;			
+wire	delay_ready;		
+wire	rx_mmcm_lckd;	
+
+IDELAYCTRL	icontrol 
+(              			// Instantiate input delay control block
+	.REFCLK	(refclkin),
+	.RST	(~Locked_i),
+	.RDY	(delay_ready)
+);
+
+// Input clock and data for 2 channels
+assign	clkin_p		=	clkin1_p;
+assign	clkin_n		=	clkin1_n;
+assign	datain_p	=	datain1_p;
+assign	datain_n	=	datain1_n;
+
+assign	dout		=	rxdall;
+assign	DivClk_o	=	rxclk_div;
+
+n_x_serdes_1_to_7_mmcm_idelay_sdr 
+#(
+	.N	(N),
+	.SAMPL_CLOCK	("BUF_G"),
+	.PIXEL_CLOCK	("BUF_G"),
+	.USE_PLL		("TRUE"),
+	.HIGH_PERFORMANCE_MODE	("FALSE"),
+	.D	(D),				// Number of data lines
+	.CLKIN_PERIOD	(40.000),			// Set input clock period
+	.MMCM_MODE		(4),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+	.DIFF_TERM		("TRUE"),
+	// .DATA_FORMAT	("PER_CLOCK")
+	.DATA_FORMAT	("PER_CHANL")
+) 			// PER_CLOCK or PER_CHANL data formatting
+ReceiverModule	
+(                          
+	.clkin_p	(clkin_p),
+	.clkin_n	(clkin_n),
+	.datain_p	(datain_p),
+	.datain_n	(datain_n),
+	.enable_phase_detector	(1'b0),
+	.rxclk		(),
+	.idelay_rdy	(delay_ready),
+	.rxclk_div	(rxclk_div),
+	.reset		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
+	.clk_data	(),
+	.rx_data	(rxdall),
+	.bit_rate_value		(16'h0350),			// required bit rate value
+	.bit_time_value		(),
+	.status		(),
+	.debug		()
+);
+      	
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/AdcInitInterface.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:56:45 07/11/2019 
+// design name: 
+// module name:    adc_init_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcInitInterface	
+#(
+	parameter	DelayValue		=	24000,
+	parameter	LengthWidth		=	2000,
+	parameter	DataWidth		=	24,
+	parameter	DataNum			=	26
+)
+(
+    input	wire	Clk_i,
+	input	wire	Rst_i,
+	
+	output	wire	AdcMosi_o,
+	output	wire	AdcClk_o,
+	output	wire	AdcCs_o,
+	output	wire	AdcRst_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire			adcRstDone;
+	wire			adcFilteredRst;
+//================================================================================
+//  instantiations
+//================================================================================	
+
+ResetFilter #(
+    .STAGE_NUM      (4),
+    .RESET_FRONT    ("RISING")
+) 
+adcResetFilter 
+(
+    .clk_i          (Clk_i),
+    .rst_i          (Rst_i),
+    .perm_i         (1'b0),
+    .filtered_rst_o (adcFilteredRst)
+);
+
+AdcInitRst
+#(
+	.DELAY_VALUE    (DelayValue),	//задержка перед выдачей reset'а
+	.LENGTH_WIDTH   (LengthWidth)		//длительность сигнала reset
+) 
+AdcInitRst 
+(
+	.clk_i      (Clk_i),
+	.rst_i      (adcFilteredRst),
+	.signal_o   (AdcRst_o),
+	.done_o     (adcRstDone)
+);
+
+PeriphSpiInit 
+#(
+	.DATA_WIDTH             (DataWidth),
+	.DATA_NUM               (DataNum), 
+	.ROM_INIT_FILE          ("C:/Users/User/Desktop/4portCompact/S5443/S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt"),
+	.FILE_DATA_BASE         ("HEX"),
+	.SPI_CLK_DIVISOR_POWER  (4),
+	.SPI_CPOL               (0),
+	.SPI_CPHA               (0),
+	.SPI_DATA_DIRECTION     ("MSB"),
+	.SPI_EN_START_DELAY     ("YES")
+) 
+PeriphSpiInitController 
+(
+	.clk_i                  (Clk_i),
+	.rst_i                  (adcFilteredRst),
+	.enable_i               (adcRstDone),
+	.mosi_o                 (AdcMosi_o),
+	.sck_o                  (AdcClk_o),
+	.ss_o                   (AdcCs_o),
+	.done_o                 ()
+);
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/AdcInitRst.v

@@ -0,0 +1,130 @@
+module AdcInitRst (
+    clk_i,
+    rst_i,
+
+    signal_o,
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 24000;
+    parameter   LENGTH_WIDTH    = 2;
+
+    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    output  reg     signal_o;
+    output  reg     done_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [1:0]   SM_RST_S    = 2'b00;
+    localparam  [1:0]   SM_DELAY_S  = 2'b01;
+    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
+    localparam  [1:0]   SM_DONE_S   = 2'b11;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               curr_state;
+    reg     [1:0]               next_state;
+
+    reg     [DELAY_CNT_W-1:0]   delay_cnt;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
+    reg                         signal_next;
+    reg                         done_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        curr_state  <= SM_RST_S;
+        delay_cnt   <= {DELAY_CNT_W{1'b0}};
+        signal_o    <= 1'b0;
+        done_o      <= 1'b0;
+    end else begin
+        curr_state  <= next_state;
+        delay_cnt   <= delay_cnt_next;
+        signal_o    <= signal_next;
+        done_o      <= done_next;
+    end
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+    signal_next     = 1'b0;
+    done_next       = 1'b0;
+    case(curr_state)
+        SM_RST_S    : begin
+            next_state  = SM_DELAY_S;
+        end
+
+        SM_DELAY_S  : begin
+            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+            end else begin
+                next_state      = SM_DELAY_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_SIGNAL_S : begin
+            signal_next = 1'b1;
+            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_DONE_S   : begin
+            done_next   = 1'b1;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/PeriphSpiInit.v

@@ -0,0 +1,217 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :   16.05.2019
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   0.01 - File Created
+// Additional Comments      :
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module PeriphSpiInit (
+    clk_i,
+    rst_i,
+
+    enable_i,
+
+    mosi_o,
+    sck_o,
+    ss_o,
+
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DATA_WIDTH              = 24;
+    parameter   DATA_NUM                = 26; 
+    parameter   ROM_INIT_FILE           = "./initFiles/AdcInitData.txt";
+    parameter   FILE_DATA_BASE          = "HEX";
+    parameter   SPI_CLK_DIVISOR_POWER   = 4;
+    parameter   SPI_CPOL                = 0;
+    parameter   SPI_CPHA                = 0;
+    parameter   SPI_DATA_DIRECTION      = "MSB";   //  MSB or LSB
+    parameter   SPI_EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  ROM_ADDR_WIDTH          = bit_num(DATA_NUM);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [7:0]   SM_RST_S        = 8'd0;
+    localparam  [7:0]   SM_SEND_DATA_S  = 8'd2;
+    localparam  [7:0]   SM_READ_DATA_S  = 8'd3;
+    localparam  [7:0]   SM_WAIT_SPI_S   = 8'd4;
+    localparam  [7:0]   SM_DONE_S       = 8'd5;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input       clk_i;
+    input       rst_i;
+    input       enable_i;
+    output      mosi_o;
+    output      sck_o;
+    output      ss_o;
+    output      done_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr;
+    reg                             rom_valid;
+    wire    [DATA_WIDTH-1:0]        rom_data;
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr_next;
+    wire                            spi_ready;
+    reg     [7:0]                   sm_curr_state;
+    reg     [7:0]                   sm_next_state;
+    wire                            data_end_flag;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  data_end_flag   = (rom_addr == DATA_NUM);
+    assign  done_o          = sm_curr_state == SM_DONE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+SpiMaster #(
+    .CLK_DIVISOR_POWER  (SPI_CLK_DIVISOR_POWER),
+    .DATA_WIDTH         (DATA_WIDTH),
+    .CPOL               (SPI_CPOL),
+    .CPHA               (SPI_CPHA),
+    .DATA_DIRECTION     (SPI_DATA_DIRECTION),
+    .EN_START_DELAY     (SPI_EN_START_DELAY)
+) SpiMaster (
+    .clk_i      (clk_i),
+    .rst_i      (rst_i),
+
+    .data_i     (rom_data),
+    .valid_i    (rom_valid),
+    .ready_o    (spi_ready),
+    .mosi_o     (mosi_o),
+    .sck_o      (sck_o),
+    .ss_o       (ss_o)
+);
+
+SinglePortRom #(
+    .DATA_WIDTH     (DATA_WIDTH), 
+    .ADDR_WIDTH     (ROM_ADDR_WIDTH),
+    .INIT_FILE_NAME (ROM_INIT_FILE),
+    .DATA_BASE      (FILE_DATA_BASE)
+) Rom (
+    .clk_i  (clk_i),
+    .addr_i (rom_addr),
+    .q_o    (rom_data)
+    );
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        rom_addr        <= SM_RST_S;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        rom_addr        <= rom_addr_next;
+    end
+end
+
+always @(*) begin
+    sm_next_state   = 0;
+    rom_addr_next   = rom_addr;
+    rom_valid       = 1'b0;
+    case(sm_curr_state)
+        SM_RST_S        :   begin
+            if (enable_i) begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end else begin
+                sm_next_state   = SM_RST_S;
+            end
+        end
+
+        SM_SEND_DATA_S  :   begin
+            rom_valid       = 1'b1;
+            sm_next_state   = SM_SEND_DATA_S;
+            if (spi_ready) begin
+                rom_addr_next   = rom_addr + {{(ROM_ADDR_WIDTH-1){1'b0}}, 1'b1};
+                sm_next_state   = SM_READ_DATA_S;
+            end
+        end
+
+        SM_READ_DATA_S  :   begin
+            if (data_end_flag) begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end else begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end
+        end
+
+        SM_WAIT_SPI_S   : begin
+            if (spi_ready) begin
+                sm_next_state   = SM_DONE_S;
+            end else begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end
+        end
+
+        SM_DONE_S       :   begin
+            sm_next_state   = SM_DONE_S;
+        end
+
+    endcase
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/Power2ClkDivider.v

@@ -0,0 +1,90 @@
+`timescale 1ns / 1ps
+module Power2ClkDivider (
+    clk_i,
+    rst_i,
+    valid_i,
+    signal_o,
+    rising_edge_o,
+    falling_edge_o
+);
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DIVISOR_POWER   = 2;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    input           valid_i;
+    output  reg     signal_o;
+    output  reg     rising_edge_o;
+    output  reg     falling_edge_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    wire    clk_div_flag;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//initial begin
+//    if (DIVISOR_POWER < 1) begin
+//        $error("parameter DIVISOR_POWER of module power2_clk_divider must be greater then 0");
+//        $stop;
+//    end
+//end
+
+generate
+    if (DIVISOR_POWER < 2) begin
+        assign  clk_div_flag    = 1'b1;
+    end else begin
+        reg     [DIVISOR_POWER-2:0] clk_div_cnt;
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end else if (valid_i) begin
+                clk_div_cnt <= clk_div_cnt + 1;
+            end else begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end
+        end
+
+        assign  clk_div_flag    = &clk_div_cnt;
+    end
+endgenerate
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end else if (valid_i) begin
+        if (clk_div_flag) begin
+            signal_o    <= ~signal_o;
+        end
+        rising_edge_o   <= ~signal_o & clk_div_flag;
+        falling_edge_o  <= signal_o & clk_div_flag;
+    end else begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/ResetFilter.v

@@ -0,0 +1,60 @@
+module ResetFilter (
+    clk_i,
+    rst_i,
+    perm_i,
+    filtered_rst_o
+);
+
+    parameter   STAGE_NUM   = 1;
+    parameter   RESET_FRONT = "RISING"; //  FALLING
+
+    input   clk_i;
+    input   rst_i;
+    input   perm_i;
+    output  filtered_rst_o;
+
+    reg [STAGE_NUM-1:0] rst_filter;
+
+    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];
+
+generate
+    if (RESET_FRONT == "RISING") begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end
+    end else begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end    
+    end
+endgenerate
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/SinglePortRom.v

@@ -0,0 +1,30 @@
+module SinglePortRom (
+    clk_i, 
+    addr_i,
+    q_o
+);
+
+    parameter   DATA_WIDTH      = 16; 
+    parameter   ADDR_WIDTH      = 5;
+    parameter   INIT_FILE_NAME  = "./initFiles/AdcInitData.txt";
+    parameter   DATA_BASE       = "HEX";    //  HEX or BIN
+
+    input                                   clk_i;
+    input           [(ADDR_WIDTH-1):0]      addr_i;
+    output  reg     [(DATA_WIDTH-1):0]      q_o;
+
+    reg     [DATA_WIDTH-1:0]    rom[2**ADDR_WIDTH-1:0];
+
+initial begin
+    if (DATA_BASE == "HEX") begin
+        $readmemh(INIT_FILE_NAME, rom);
+    end else begin
+        $readmemb(INIT_FILE_NAME, rom);
+    end
+end
+
+always @ (posedge clk_i) begin
+    q_o <=  rom[addr_i];
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/SpiMaster.v

@@ -0,0 +1,273 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   1.0 - It only send data (no miso port)
+// Additional Comments      :   MISO port need to be add. What about multiple slave select?
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module SpiMaster (
+    clk_i,
+    rst_i,
+
+    data_i,
+    valid_i,
+    ready_o,
+
+    mosi_o,
+    sck_o,
+    ss_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   CLK_DIVISOR_POWER   = 4; //WAS 2 !! DONT FORGET TO CHANGE!
+    parameter   DATA_WIDTH          = 24;
+    parameter   CPOL                = 0;
+    parameter   CPHA                = 0;
+    parameter   DATA_DIRECTION      = "MSBT";   //  MSB or LSB
+    parameter   EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  BIT_CNT_W           = bit_num(DATA_WIDTH);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  SM_IDLE_S   = 2'b00;
+    localparam  SM_START_S  = 2'b01;
+    localparam  SM_DATA_S   = 2'b10;
+    localparam  SM_STOP_S   = 2'b11;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input                               clk_i;
+    input                               rst_i;
+
+    input           [DATA_WIDTH-1:0]    data_i;
+    input                               valid_i;
+    output                              ready_o;
+
+    output  reg                         mosi_o;
+    output  reg                         sck_o;
+    output  reg                         ss_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               sm_curr_state;
+    reg     [1:0]               sm_next_state;
+
+    reg                         sm_clk_div_en;
+
+    //  Clock divider outputs
+
+    wire                        clk_divider_redge;
+    wire                        clk_divider_fedge;
+
+    //  Bits counter
+
+    reg     [BIT_CNT_W-1:0]     bit_cnt_r;
+    reg     [BIT_CNT_W-1:0]     bit_cnt_next;
+
+    //  Data buffers
+
+    reg     [DATA_WIDTH-1:0]    tx_buffer_r;
+    reg     [DATA_WIDTH-1:0]    tx_buffer_next;
+    wire    [DATA_WIDTH-1:0]    tx_buffer_shifted;
+    wire                        tx_curr_bit;
+
+    //  Output data next
+    reg                         mosi_next;
+    reg                         sck_next;
+    reg                         ss_next;
+
+    //  Edges
+
+    wire                        mosi_shift_edge;
+
+    wire                        ss_start_edge;
+    wire                        ss_stop_edge;
+
+    wire                        sck_leading_edge;
+    wire                        sck_trailing_edge;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  mosi_shift_edge     = (CPHA[0] == 1'b1) && (EN_START_DELAY != "YES") || (CPHA[0] == 1'b0) && (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_start_edge       = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_stop_edge        = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_leading_edge    = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_trailing_edge   = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  tx_buffer_shifted   = (DATA_DIRECTION == "MSB") ? tx_buffer_r << 1 : tx_buffer_r >> 1;
+    assign  tx_curr_bit         = (DATA_DIRECTION == "MSB") ? tx_buffer_r[DATA_WIDTH-1] : tx_buffer_r[0];
+
+    assign  ready_o             = sm_curr_state == SM_IDLE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//  Sequential logic
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        tx_buffer_r     <= {DATA_WIDTH{1'b0}};
+        bit_cnt_r       <= {BIT_CNT_W{1'b0}};
+        mosi_o          <= 1'b0;
+        sck_o           <= CPOL[0];
+        ss_o            <= 1'b1;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        tx_buffer_r     <= tx_buffer_next;
+        bit_cnt_r       <= bit_cnt_next;
+        mosi_o          <= mosi_next;
+        sck_o           <= sck_next;
+        ss_o            <= ss_next;
+    end
+end
+
+//  Combinational logic
+
+always @(*) begin
+    sm_next_state   = SM_IDLE_S;
+    tx_buffer_next  = tx_buffer_r;
+    mosi_next       = mosi_o;
+    sck_next        = sck_o;
+    ss_next         = ss_o;
+    sm_clk_div_en   = 1'b1;
+    bit_cnt_next    = bit_cnt_r;
+
+    case(sm_curr_state)
+
+        SM_IDLE_S   : begin
+            if (valid_i) begin
+                sm_next_state   = SM_START_S;
+            end else begin
+                sm_next_state   = SM_IDLE_S;
+            end
+            tx_buffer_next  = data_i;
+            sm_clk_div_en   = 1'b0;
+            bit_cnt_next    = {BIT_CNT_W{1'b0}};
+        end
+
+        SM_START_S  : begin
+            if (ss_start_edge) begin
+                sm_next_state   = SM_DATA_S;
+                ss_next         = 1'b0;
+                if (!CPHA[0]) begin
+                    mosi_next       = tx_curr_bit;
+                    tx_buffer_next  = tx_buffer_shifted;
+                    bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+                end
+            end else begin
+                sm_next_state   = SM_START_S;
+            end
+        end
+
+        SM_DATA_S   : begin
+            sm_next_state   = SM_DATA_S;
+            if (sck_leading_edge) begin
+                sck_next    = ~CPOL[0];
+            end
+
+            if  (sck_trailing_edge) begin
+                sck_next    = CPOL[0];
+                if (bit_cnt_r == DATA_WIDTH[BIT_CNT_W-1:0]) begin
+                    sm_next_state   = SM_STOP_S;
+                end
+            end
+
+            if (mosi_shift_edge) begin
+                mosi_next       = tx_curr_bit;
+                tx_buffer_next  = tx_buffer_shifted;
+                bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+            end
+
+        end
+
+        SM_STOP_S   : begin
+            if (ss_stop_edge) begin
+                if (CPHA[0]) begin
+                    mosi_next   = tx_curr_bit;
+                end
+                sm_next_state   = SM_IDLE_S;
+                ss_next         = 1'b1;
+            end else begin
+                sm_next_state   = SM_STOP_S;
+            end
+        end
+
+    endcase
+end
+
+//  Clock divider
+
+Power2ClkDivider #(
+    .DIVISOR_POWER      (CLK_DIVISOR_POWER)
+) ClkDividerInst (
+    .clk_i              (clk_i),
+    .rst_i              (rst_i),
+    .valid_i            (sm_clk_div_en),
+    .signal_o           (),
+    .rising_edge_o      (clk_divider_redge),
+    .falling_edge_o     (clk_divider_fedge)
+);
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt

@@ -0,0 +1,26 @@
+400601
+40013C
+400300
+400400
+400533
+400602 
+400700
+400900
+400A02
+400B20
+400ED1
+400FD4
+401300
+401500
+402500
+402700
+441D00
+442202
+443428
+443908
+451D00
+452202
+453428
+453908
+460800
+470A00

S5443_M/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -0,0 +1,86 @@
+module Clk200Gen 
+(
+    input	Clk_i,
+    input	Rst_i,
+	output	Clk200_o,
+	output	Clk10Timers_o,
+	output	Clk100_o,
+	
+	output	Locked_o
+);
+
+wire	ClkFb;
+wire	rxFb;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(24),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(20),
+      	.CLKIN2_PERIOD		(),
+      	.CLKOUT0_DIVIDE		(6),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(120),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0.0),
+      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(120),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+CommonPll (
+      	.CLKFBOUT		(ClkFb),
+      	.CLKOUT0		(rx_mmcmout_200),
+      	.CLKOUT1		(rx_mmcmout_10),
+      	.CLKOUT2		(rx_mmcmout_100),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO				(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(Locked_o),
+      	.CLKFBIN		(rxFb),
+      	.CLKIN1			(Clk_i),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI				(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(1'b0)
+) ;
+
+
+BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
+
+BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
+BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
+BUFG	ctrlClk100 (.I(rx_mmcmout_100), .O(Clk100_o)) ;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/DitherGen/DitherGen.v

@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DitherGen
+#(	
+	parameter	CmdDataRegWith		=	24,
+	parameter	FrAmpWordWidth		=	8
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[CmdDataRegWith-1:0]	DitherCmd_i,
+	output	DitherCtrlT2R2_o,
+	output	DitherCtrlT1R1_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
+	wire	[FrAmpWordWidth-1:0]	ditherAmp	=	DitherCmd_i[CmdDataRegWith-FrAmpWordWidth-1-:FrAmpWordWidth];
+
+	wire	ditherT2R2	=	DitherCmd_i[1];
+	wire	ditherT1R1	=	DitherCmd_i[0];
+	
+	reg	[FrAmpWordWidth-1:0]	freqCnt;
+	reg	[FrAmpWordWidth-1:0]	ampCnt;
+	
+	wire	DitherReg	=	((freqCnt<=ditherFreq/2)&&(ampCnt<=ditherAmp))?	1'b1:1'b0;
+	
+	wire	ClkDiv	=	(freqCnt<=ditherFreq/2)?	1'b1:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	DitherCtrlT2R2_o	=	(ditherT2R2)?	DitherReg:1'b0;
+	assign	DitherCtrlT1R1_o	=	(ditherT1R1)?	DitherReg:1'b0;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(freqCnt!=ditherFreq-1)	begin
+			freqCnt<=freqCnt+1;
+		end	else	begin
+			freqCnt<=0;
+		end
+	end	else	begin
+		freqCnt<=0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(ampCnt!=ditherFreq-1)	begin
+			ampCnt<=ampCnt+1;
+		end	else	begin
+			ampCnt<=0;
+		end
+	end	else	begin
+		ampCnt<=0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/DitherGen/DitherGenv2.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DitherGenv2
+#(	
+	parameter	CmdDataRegWith		=	24,
+	parameter	FrAmpWordWidth		=	8,
+	parameter	RefFreqDiv			=	5
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[CmdDataRegWith-1:0]	DitherCmd_i,
+	output	DitherCtrlT2R2_o,
+	output	DitherCtrlT1R1_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
+	
+	wire	[4-1:0]	ditherAmpT2R2	=	DitherCmd_i[15:12];
+	wire	[4-1:0]	ditherAmpT1R1	=	DitherCmd_i[11:8];
+	wire	[4-1:0]	rampLimit		=	DitherCmd_i[7:4];
+	
+	wire	ditherEnT2R2	=	DitherCmd_i[1];
+	wire	ditherEnT1R1	=	DitherCmd_i[0];
+	
+	wire	[3:0]	ncoArray	[15:0];
+	
+	assign	ncoArray	[0]		=	0;
+	assign	ncoArray	[1]		=	1;
+	assign	ncoArray	[2]		=	2;
+	assign	ncoArray	[3]		=	3;
+	assign	ncoArray	[4]		=	4;
+	assign	ncoArray	[5]		=	5;
+	assign	ncoArray	[6]		=	6;
+	assign	ncoArray	[7]		=	7;
+	assign	ncoArray	[8]		=	8;
+	assign	ncoArray	[9]		=	7;
+	assign	ncoArray	[10]	=	6;
+	assign	ncoArray	[11]	=	5;
+	assign	ncoArray	[12]	=	4;
+	assign	ncoArray	[13]	=	3;
+	assign	ncoArray	[14]	=	2;
+	assign	ncoArray	[15]	=	1;
+	
+	reg	[3:0]	sawCnt;
+	
+	reg	[FrAmpWordWidth-1:0]	currStateT2R2;
+	reg	[FrAmpWordWidth-1:0]	currStateT1R1;
+	
+	wire	[3:0]	ncoSignalT2R2	=	ncoArray[currStateT2R2[FrAmpWordWidth-1-:4]];
+	wire	[3:0]	ncoSignalT1R1	=	ncoArray[currStateT1R1[FrAmpWordWidth-1-:4]];
+
+	wire	dithGenT2R2	=	((ncoSignalT2R2>>ditherAmpT2R2)>sawCnt)	?	1'b1:1'b0;
+	wire	dithGenT1R1	=	((ncoSignalT1R1>>ditherAmpT1R1)>sawCnt)	?	1'b1:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	DitherCtrlT2R2_o	=	(ditherEnT2R2)	?	dithGenT2R2:1'b0;
+	assign	DitherCtrlT1R1_o	=	(ditherEnT1R1)	?	dithGenT1R1:1'b0;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	!=	rampLimit)	begin
+			sawCnt	<=	sawCnt	+1;
+		end	else	begin
+			sawCnt	<=	0;
+		end
+	end	else	begin
+		sawCnt	<=	0;
+	end
+end
+
+wire	Clk5=(sawCnt<=10/2-1)?	1'b1:1'b0;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	==rampLimit)	begin
+			currStateT2R2	<=	currStateT2R2+ditherFreq;
+			currStateT1R1	<=	currStateT1R1+ditherFreq;
+		end
+	end	else	begin
+		currStateT2R2	<=0;
+		currStateT1R1	<=0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DataMuxer.v

@@ -0,0 +1,73 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DataMuxer	
+#(	
+	parameter	DataWidth	=	256,
+	parameter	CmdWidth	=	3
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	[CmdWidth-1:0]	MuxCtrl_i,
+	
+	input	[DataWidth-1:0]	MeasData_i,
+	input	[DataWidth-1:0]	OscData_i,
+	
+	input	MeasDataVal_i,
+	input	OscDataVal_i,
+	
+	output	reg	[DataWidth-1:0]	MuxDataOut_o,
+	output	reg	MuxedVal_o
+);	
+
+//================================================================================
+//  CODING
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(MuxCtrl_i==1)	begin
+				MuxDataOut_o	<=	OscData_i;
+				MuxedVal_o		<=	OscDataVal_i;
+			end	else	begin
+				MuxDataOut_o	<=	MeasData_i;
+				MuxedVal_o		<=	MeasDataVal_i;
+			end
+		end	else	begin
+			MuxDataOut_o	<=	0;
+			MuxedVal_o		<=	0;
+		end
+	end
+	
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -0,0 +1,327 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DspInterface
+#(	
+	parameter	AdcDataWidth	=	14,	
+	parameter	ExtAdcDataWidth	=	16,	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40,
+	parameter	ChNum			=	16,
+	parameter	CmdRegWidth		=	32,
+	parameter	CmdDataRegWith	=	24,
+	parameter	HeaderWidth		=	7,
+	parameter	DataCntWidth	=	5,
+	parameter	CmdWidth		=	3
+)
+(
+	input	Clk_i,
+	input	ClkPpiOut_i,
+	input	Rst_i,
+	input	OscWind_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	
+	input	Mode_i,
+	input	[CmdWidth-2:0]		PortSel_i,
+	input	[CmdWidth-1:0]		DecimFactor_i,
+	
+	input	[CmdRegWidth-1:0]	IfFtwL_i,
+	input	[CmdRegWidth-1:0]   IfFtwH_i,
+	
+	output	OscDataRdFlag_o,
+	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	
+	
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	input	Miso_i,
+	output	Miso_o,
+	
+	output	[CmdRegWidth-1:0]	CmdDataReg_o,
+	output	CmdDataVal_o,
+	
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	output	[HeaderWidth-1:0]		AnsAddr_o,	
+
+	output	LpOutFs_o,
+	output	LpOutClk_o,
+	output	[ODataWidth-1:0]	LpOutData_o,
+	
+	input	[ResultWidth-1:0]	Adc1T1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1T1ReResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	
+	
+	input	[ResultWidth-1:0]	Adc2R2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2R2ReResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ReResult_i,
+	input	[ChNum-1:0]			ServiseRegData_i,
+
+	input	LpOutStart_i
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	fftDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	bypassDataBus;
+	
+	reg		[ResultWidth*(ChNum*2)-1:0]	dataForFifo;
+	reg		dataForFifoVal;
+	
+	wire	fftDataBusVal;
+	wire	bypassDataBusVal;
+	
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBusTx;
+	wire	measDataValTx;
+	
+	wire	ppiBusy;
+	
+	reg	signed	[15:0]	adc1ChT1DataExt;	
+	reg	signed	[15:0]	adc1ChR1DataExt;	
+	reg	signed	[15:0]	adc2ChR2DataExt;	
+	reg	signed	[15:0]	adc2ChT2DataExt;
+	
+	reg		signed	[AdcDataWidth-1:0]	currDataChannel;
+	wire	signed	[AdcDataWidth-1:0]	testData;
+	
+	wire	signed	[15:0]	filteredDecimDataI;
+	wire	signed	[15:0]	filteredDecimDataQ;
+	wire	filteredDecimDataVal;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+	assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	Adc1T1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	Adc1T1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	Adc1R1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	Adc1R1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	Adc2T2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	Adc2T2ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
+	
+	assign	OscDataRdFlag_o	=	measDataValTx;
+	
+//================================================================================
+//	CODING
+//================================================================================
+
+reg	oscWindR;
+reg	[15:0]	testPatternData;
+
+wire	oscWindNeg	=	(!OscWind_i&oscWindR);
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		oscWindR	<=	OscWind_i;
+	end	else	begin
+		oscWindR	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(oscWindNeg)	begin
+			testPatternData	<=	~testPatternData;
+		end
+	end	else	begin
+		testPatternData	<=	16'h1fff;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(PortSel_i)
+			0:	begin
+					// currDataChannel	<=	testPatternData;
+					currDataChannel	<=	Adc1ChT1Data_i;
+				end
+			1:	begin
+					currDataChannel	<=	Adc1ChR1Data_i;
+				end
+			2:	begin
+					currDataChannel	<=	Adc2ChT2Data_i;
+				end
+			3:	begin
+					currDataChannel	<=	Adc2ChR2Data_i;
+				end
+		endcase
+	end	else	begin
+		currDataChannel	<=	0;
+	end
+end
+
+
+SlaveSpi
+#(	
+	.CmdRegWidth	(CmdRegWidth),
+	.DataCntWidth	(DataCntWidth),
+	.HeaderWidth	(HeaderWidth)
+)
+DspSlaveSpi
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i),
+
+	.Data_o		(CmdDataReg_o),
+	.Val_o		(CmdDataVal_o),
+	
+	.Mosi_i		(Mosi_i),
+	.Sck_i		(Sck_i),
+	.Ss_i		(Ss_i),
+	
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o),
+	.Ss0_o		(Ss0_o),
+	.Ss1_o		(Ss1_o),
+	
+	.AnsAddr_o	(AnsAddr_o),
+	.AnsReg_i	(AnsReg_i),
+	
+	.Miso_i		(Miso_i),
+	.Miso_o		(Miso_o)
+);
+
+DecimFilterWrapper	DecimFilter
+(
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.OscWind_i		(OscWind_i),
+	.DecimFactor_i	(DecimFactor_i),
+	
+	.IfFtwL_i		(IfFtwL_i),
+	.IfFtwH_i		(IfFtwH_i),
+	
+	.AdcData_i		(currDataChannel),
+	// .TestData_o		(testData),
+	
+	.FilteredAdcDataI_o	(filteredDecimDataI),
+	.FilteredAdcDataQ_o	(filteredDecimDataQ),
+	.FilteredDataVal_o	(filteredDecimDataVal)
+);
+
+FftDataFormer	FftDataFormerInst
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i),	
+	.OscWind_i			(OscWind_i),
+	.MeasNum_i			(MeasNum_i),
+	
+	.AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+	// .AdcData_i			({testPatternData,testPatternData}),
+	.AdcDataVal_i		(filteredDecimDataVal),
+	
+	.OscDataBus_o		(fftDataBus),
+	.OscDataBusVal_o	(fftDataBusVal)
+);
+
+OscDataFormer	BypassDataFormer
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i),	
+	.OscWind_i			(OscWind_i),
+	.MeasNum_i			(MeasNum_i),
+	
+	.AdcData_i			(currDataChannel),	
+	
+	.OscDataBus_o		(bypassDataBus),
+	.OscDataBusVal_o	(bypassDataBusVal)
+);
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i)	begin
+			if	(DecimFactor_i	==	0)	begin
+				dataForFifo		<=	bypassDataBus;
+				dataForFifoVal	<=	bypassDataBusVal;
+			end	else	begin
+				dataForFifo		<=	fftDataBus;
+				dataForFifoVal	<=	fftDataBusVal;
+			end
+		end	else	begin
+			dataForFifo		<=	measDataBus;
+			dataForFifoVal	<=	LpOutStart_i;
+		end
+	end	else	begin
+		dataForFifo		<=	0;
+		dataForFifoVal	<=	0;
+	end
+end
+
+MeasDataFifoWrapper		
+#(	
+	.DataWidth	(ResultWidth),
+	.ChNum		(ChNum)
+)
+MeasDataFifoInst
+(
+	.Clk_i			(Clk_i), 
+	.ClkPpiOut_i	(ClkPpiOut_i), 
+	.Rst_i			(Rst_i),	
+	.PpiBusy_i		(ppiBusy),	
+	// .MeasDataBus_i	(measDataBus),
+	.MeasDataBus_i	(dataForFifo),
+	// .MeasDataVal_i	(LpOutStart_i),	
+	.MeasDataVal_i	(dataForFifoVal),	
+	
+	.MeasDataBus_o	(measDataBusTx),
+	.MeasDataVal_o	(measDataValTx)
+);
+
+DspPpiOut	
+#(	
+	.ODataWidth		(ODataWidth),	
+	.ResultWidth	(ResultWidth), 
+	.ChNum			(ChNum)
+)
+MeasDataPpiOut
+(
+	.Rst_i				(Rst_i),	
+	.Clk_i				(Clk_i),		
+	
+	.MeasDataBus_i		(measDataBusTx),
+	.ServiseRegData_i	(ServiseRegData_i),
+	
+	.PpiBusy_o			(ppiBusy),
+	.LpOutStart_i		(measDataValTx),
+	
+	.LpOutClk_o			(LpOutClk_o),
+	.LpOutFs_o			(LpOutFs_o),
+	.LpOutData_o		(LpOutData_o)
+);
+
+endmodule
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterfaceTb.v

@@ -0,0 +1,122 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DspInterfaceTb
+();
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	reg		Clk_i;
+	reg		Rst_i;
+	reg		start;
+
+	reg	[31:0]	MeasDataPattern1;
+	reg	[31:0]	MeasDataPattern2;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	#10 Clk_i	=	~Clk_i;
+
+initial begin
+	Clk_i	=	1'b1;
+	Rst_i	=	1'b1;
+	start	=	1'b0;
+	MeasDataPattern1	=	32'hAAAAAAAA;
+	MeasDataPattern2	=	32'hBBBBBBBB;
+#100;
+	Rst_i	=	1'b0;
+#200;
+	start	=	1'b1;
+#20;
+	start	=	1'b0;
+#100;
+	MeasDataPattern1	=	32'hCCCCCCCC;
+	MeasDataPattern2	=	32'hDDDDDDDD;
+#1000;
+	start	=	1'b1;
+#20;
+	start	=	1'b0;
+end	
+
+DspInterface
+#(	
+	.ODataWidth		(16),	
+	.ResultWidth	(32),
+	.ChNum			(4),
+	.CmdRegWidth	(32),
+	.CmdDataRegWith	(24),
+	.HeaderWidth	(7),
+	.DataCntWidth	(5)
+)
+DspInterfaceInst
+(
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	
+	.Mosi_i				(1'b0),
+	.Sck_i				(1'b0),
+	.Ss_i				(1'b0),
+	
+	.Mosi_o				(),
+	.Sck_o				(),
+	.Ss0_o				(),
+	.Ss1_o				(),
+	.Miso_i				(1'b0),
+	.Miso_o				(),
+	
+	.CmdDataReg_o		(),
+	.CmdDataVal_o		(),
+	
+	.AnsReg_i			(32'b0),
+	.AnsAddr_o			(),
+
+
+	.LpOutFs_o			(),
+	.LpOutClk_o			(),
+	.LpOutData_o		(),
+	
+	.Adc1T1ImResult_i	(MeasDataPattern1),
+	.Adc1T1ReResult_i	(MeasDataPattern2),
+	.Adc1R1ImResult_i	(MeasDataPattern1),
+	.Adc1R1ReResult_i	(MeasDataPattern2),	
+	
+	.Adc2R2ImResult_i	(MeasDataPattern1),
+	.Adc2R2ReResult_i	(MeasDataPattern2),
+	.Adc2T2ImResult_i	(MeasDataPattern1),
+	.Adc2T2ReResult_i	(MeasDataPattern2),
+	.ServiseRegData_i	(32'h8),
+
+	.LpOutStart_i		(start)
+);
+endmodule
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspPpiOut.v

@@ -0,0 +1,160 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DspPpiOut
+#(	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40, 
+	parameter	ChNum			=	8,
+	localparam	DataBusWidth	=	((ChNum*2)+1)*ResultWidth,
+	localparam	ServisePattern	=	32'hABCD
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[ChNum-1:0]	ServiseRegData_i,
+	input	[ResultWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	
+	input	LpOutStart_i,
+	output	PpiBusy_o,
+	
+	output	LpOutClk_o,
+	output	LpOutFs_o,
+	output	[ODataWidth-1:0]	LpOutData_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	lpDataRst;
+	reg	[5:0]	txCnt	=	6'd0;	
+	reg	[DataBusWidth-1:0]	lpDataBuf;
+	reg	dataShEn;
+	reg	dataValid;
+	
+	reg	lpOutFs;
+	reg	ppiBusy;
+	
+	wire	oddrCe = (txCnt	<=	6'd19 && dataValid)	?	1'b1:1'b0;
+	
+	wire	[7:0]	ampEnT1	=	{{7{1'b0}},ServiseRegData_i[0]};
+	wire	[7:0]	ampEnR1	=	{{7{1'b0}},ServiseRegData_i[1]};
+	wire	[7:0]	ampEnR2	=	{{7{1'b0}},ServiseRegData_i[2]};
+	wire	[7:0]	ampEnT2	=	{{7{1'b0}},ServiseRegData_i[3]};
+	
+	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
+	
+	wire	outDataVal	=	(txCnt	<=	18	&&	txCnt	!=	0);
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	LpOutData_o	=	lpDataBuf[ODataWidth-1:0];
+	assign	LpOutFs_o	=	lpOutFs;
+	assign	PpiBusy_o	=	ppiBusy;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin
+			ppiBusy	<=	1'b1;
+		end	else	if	(!dataValid)	begin
+			ppiBusy	<=	1'b0;
+		end
+	end	else	begin
+		ppiBusy	<=	1'b0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin	
+			txCnt	<=	6'd19;
+		end	else	if	(dataValid)	begin
+			txCnt	<=	txCnt	-	6'd1;
+		end
+	end	else	begin
+		txCnt	<=	6'd0;
+	end
+end
+
+always	@(*)	begin
+	case (txCnt)
+		6'd19:	begin
+					dataShEn	=	1'b0;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd18:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b1;
+				end
+		6'd17:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd0:	begin	
+					dataShEn	=	1'b0;
+					dataValid	=	1'b0;
+					lpOutFs		=	1'b0;
+				end	
+		default: 
+			begin
+				dataShEn	=	1'b1;
+				dataValid	=	1'b1;
+				lpOutFs		=	1'b0;
+			end
+	endcase
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(txCnt	==	6'd19)	begin
+			lpDataBuf	<=	{serviceData,MeasDataBus_i};
+		end	else	if	(dataShEn)	begin
+			lpDataBuf	<=	{{ODataWidth{1'b0}},lpDataBuf[DataBusWidth-1:ODataWidth]};
+		end
+	end	else	begin
+		lpDataBuf	<=	{DataBusWidth{1'b0}};
+	end
+end
+//================================================================================
+//  INSTANTIATIONS
+//================================================================================		
+ODDR2
+#(
+	.DDR_ALIGNMENT("NONE"),
+	.INIT	(1'b0),
+	.SRTYPE	("SYNC")
+) clk_i10OutInst (
+	.Q		(LpOutClk_o),
+	.C0		(Clk_i),
+	.C1		(~Clk_i),
+	.CE		(1'b1),
+	.D0		(1'b1),
+	.D1		(1'b0),
+	.R		(1'b0),
+	.S		(1'b0)
+);		
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspPpiOutTb.v

@@ -0,0 +1,90 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DspPpiOutTb
+();
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	reg		Clk_i;
+	reg		Rst_i;
+	reg		start;
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	#10 Clk_i	=	~Clk_i;
+
+initial begin
+	Clk_i	=	1'b1;
+	Rst_i	=	1'b1;
+	start	=	1'b0;
+#100;
+	Rst_i	=	1'b0;
+#100;
+	start	=	1'b1;
+#20;
+	start	=	1'b0;
+end	
+
+DspPpiOut	
+#(	
+	.ODataWidth		(16),	
+	.ResultWidth	(32), 
+	.ChNum			(8)
+)
+MeasDataPpiOut
+(
+	.Rst_i				(Rst_i),	
+	.Clk_i				(Clk_i),	
+	//adc1
+	.Adc1T1ImResult_i	(32'd1),
+	.Adc1T1ReResult_i	(32'd0),
+	.Adc1R1ImResult_i	(32'd1),
+	.Adc1R1ReResult_i	(32'd0),
+	//adc2
+	.Adc2T2ImResult_i	(32'd1),
+	.Adc2T2ReResult_i	(32'd0),
+	.Adc2R2ImResult_i	(32'd1),
+	.Adc2R2ReResult_i	(32'd0),
+	//sts data reg
+	.ServiseRegData_i	(32'd3),
+	
+	.LpOutStart_i		(start),
+	
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),
+	.LpOutData_o		()
+);
+endmodule
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/SlaveSpi.v

@@ -0,0 +1,213 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	SlaveSpi
+#(	
+	parameter	CmdRegWidth			=	32,
+	parameter	DataCntWidth		=	6,
+	parameter	HeaderWidth			=	7,
+	parameter	CmdDataRegWith		=	24,
+	parameter	Adc0DirAccessAddr	=	7'h13,
+	parameter	Adc1DirAccessAddr	=	7'h14
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	output	reg	[CmdRegWidth-1:0]	Data_o,
+	output	reg	Val_o,
+	
+	//-----------------------------------
+	//input Spi lines from ext. Dsp
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	//-----------------------------------
+	
+	//-----------------------------------
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	//-----------------------------------
+	
+	output	[HeaderWidth-1:0]		AnsAddr_o,
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	
+	input	Miso_i,
+	output	Miso_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	reg	[CmdRegWidth-1:0]		dataCaptReg;
+	reg	[DataCntWidth-1:0]		dataCnt;
+	reg	[HeaderWidth-1:0]		ansAddr;
+	reg	spiMode;
+	wire	directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
+	reg	txWind;
+	reg	[4:0]	txCnt;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	Mosi_o		=	(!spiMode&directTransit)?	Mosi_i:1'b1;
+	assign	Sck_o		=	(directTransit)?	Sck_i:1'b0;
+	assign	Ss0_o		=	(directTransit&&(ansAddr==Adc0DirAccessAddr))?	Ss_i:1'b1;
+	assign	Ss1_o		=	(directTransit&&(ansAddr==Adc1DirAccessAddr))?	Ss_i:1'b1;
+	assign	AnsAddr_o	=	ansAddr;
+	assign	Miso_o		=	txWind?	AnsReg_i[txCnt]:1'b0;
+//================================================================================
+//	CODING
+//================================================================================
+always	@(posedge	Sck_i)	begin
+	if	(~Ss_i)	begin
+		dataCaptReg	<=	{dataCaptReg[CmdRegWidth-2:0],Mosi_i};
+	end	else	begin
+		dataCaptReg	<=	dataCaptReg;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			dataCnt	<=	dataCnt	+	5'd1;
+		end
+	end	else	begin
+		dataCnt	<=	0;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(dataCnt	==	5'd1)	begin
+			if	(dataCaptReg[CmdRegWidth-CmdRegWidth])	begin
+				spiMode	<=	1'b1;
+			end	else	begin
+				spiMode	<=	1'b0;
+			end
+		end
+	end	else	begin
+		spiMode	<=	1'b0;
+	end
+end
+
+always	@(negedge Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			if	(dataCnt	==	5'd8)	begin
+				ansAddr	<=	dataCaptReg[CmdRegWidth-26-:HeaderWidth];
+			end	else	if	(dataCnt	==	5'd0)	begin
+				ansAddr	<=	7'h7F;
+			end
+		end	else	begin
+			ansAddr	<=	7'h7F;	
+		end
+	end	else	begin
+		ansAddr	<=	7'h7F;	
+	end
+end
+
+//================================================================================
+//	Generating output signals
+//================================================================================
+reg	ssReg;
+reg	ssRegR;
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+reg	ssPos;
+
+always	@(posedge	Clk_i)	begin
+	ssPos	<=	ssReg&!ssRegR;
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!directTransit&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Val_o	<=	1'b1;
+		end	else	begin
+			Val_o	<=	0;
+		end
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(((ansAddr	!=	Adc0DirAccessAddr)|(ansAddr	!=	Adc1DirAccessAddr))&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Data_o	<=	dataCaptReg;
+		end	
+	end
+end
+
+always	@(*)	begin
+	if	(spiMode	&	!Ss_i)	begin
+		if	(dataCnt	>=5'd8|dataCnt	==	0)	begin
+			txWind	=	1'b1;
+		end	else	begin
+			txWind	=	1'b0;
+		end
+	end	else	begin
+		txWind	=	1'b0;
+	end
+end
+
+always	@(negedge	Sck_i)	begin
+	if	(txWind)	begin
+		if	(~Ss_i	&	txWind	&	txCnt!=	0)	begin
+			txCnt	<=	txCnt	-	5'd1;
+		end	else	begin
+			txCnt	<=	5'd24;
+		end
+	end	else	begin
+		txCnt	<=	5'd24;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapper.v

@@ -0,0 +1,202 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DecimFilterWrapper
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	N	=	4,
+	parameter	M	=	1,
+	parameter	FilteredDataWidth	=	21,
+	parameter	FirOutDataWidth		=	48,
+	parameter	FirOutCutBit		=	42
+)
+(
+	input	Clk_i,
+	input	[2:0]	DecimFactor_i,
+	input	Rst_i,
+	input	OscWind_i,
+	
+	input	[24-1:0]	IfFtwL_i,
+	input	[24-1:0]	IfFtwH_i,
+	
+	input	signed	[AdcDataWidth-1:0]	AdcData_i,
+	
+	output	signed	[AdcDataWidth+1:0]	FilteredAdcDataI_o,
+	output	signed	[AdcDataWidth+1:0]	FilteredAdcDataQ_o,
+	output	FilteredDataVal_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	signed	[FilteredDataWidth-1:0]	decimDataI;
+	wire	signed	[FilteredDataWidth-1:0]	decimDataQ;
+	wire	decimDataValI;
+	wire	decimDataValQ;
+	
+	wire	signed	[FirOutDataWidth-1:0]	firDataOut;
+	wire	firDataOutVal;
+	
+	wire	[AdcDataWidth-1:0]	ncoCos;
+	wire	[AdcDataWidth-1:0]	ncoSin;
+	
+	wire	[FilteredDataWidth-1:0]	adcSinResult;
+	wire	adcSinVal;
+	wire	[FilteredDataWidth-1:0]	adcCosResult;
+	wire	adcCosVal;
+	
+	reg		[24-1:0]	ifFtwLReg;
+	reg		[24-1:0]	ifFtwHReg;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+	assign	FilteredAdcDataI_o		=	decimDataI[FilteredDataWidth-1-:AdcDataWidth+2];
+	assign	FilteredAdcDataQ_o		=	decimDataQ[FilteredDataWidth-1-:AdcDataWidth+2];
+	assign	FilteredDataVal_o		=	decimDataValI&decimDataValQ;
+	
+//================================================================================
+//	CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		ifFtwLReg	<=	IfFtwL_i;
+		ifFtwHReg	<=	IfFtwH_i;
+	end	else	begin
+		ifFtwLReg	<=	0;
+		ifFtwHReg	<=	0;
+	end
+end
+
+CordicNco		
+#(	
+	.ODatWidth	(14),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(1)
+)
+ncoInst
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(1'b1),
+	.PhaseInc_i	({ifFtwHReg[0+:32-24],ifFtwLReg}),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin),
+	.Cos_o		(ncoCos),
+	.Val_o		()
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcDataWidth),
+	.FactorBWidth	(AdcDataWidth),
+	.OutputWidth	(FilteredDataWidth)
+)
+AdcNcoSinMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(1'b1),
+	.FactorA_i	(ncoSin),
+	.FactorB_i	(ncoSin),	
+	.Result_o	(adcSinResult),
+	.ResultVal_o(adcSinVal)
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcDataWidth),
+	.FactorBWidth	(AdcDataWidth),
+	.OutputWidth	(FilteredDataWidth)
+)
+AdcNcoCosMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(1'b1),
+	.FactorA_i	(ncoCos),
+	.FactorB_i	(ncoSin),
+	.Result_o	(adcCosResult),
+	.ResultVal_o(adcCosVal)
+);
+
+cicFilter 
+#(
+	.N (N),	//filter order
+	.M (M),	//comb delay
+	.filteredDataWidth	(FilteredDataWidth),
+	.inOutDataWidth		(FilteredDataWidth),
+	.decimCntWidth		(7)
+)
+cicFilterInstI
+(
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.DecimFactor_i	(DecimFactor_i),
+	// .Data_i			({{7{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	.Data_i			(adcCosResult),
+	.DataNd_i		(OscWind_i),
+	.Data_o			(decimDataI),
+	.DataValid_o	(decimDataValI)
+);
+
+cicFilter 
+#(
+	.N (N),	//filter order
+	.M (M),	//comb delay
+	.filteredDataWidth	(FilteredDataWidth),
+	.inOutDataWidth		(FilteredDataWidth),
+	.decimCntWidth		(7)
+)
+cicFilterInstQ
+(
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.DecimFactor_i	(DecimFactor_i),
+	// .Data_i			(AdcData_i),
+	// .Data_i			({{7{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	.Data_i			(adcSinResult),
+	.DataNd_i		(OscWind_i),
+	.Data_o			(decimDataQ),
+	.DataValid_o	(decimDataValQ)
+);
+  
+// fir_compiler_0 firCompensator 
+// (
+	// .aclk	(Clk_i),
+	// .s_axis_data_tvalid	(decimDataVal),
+	// .s_axis_data_tready	(),
+	// .s_axis_data_tdata	({{3{decimData[FilteredDataWidth-1]}},decimData}),
+	// .m_axis_data_tvalid	(firDataOutVal),
+	// .m_axis_data_tdata	(firDataOut)
+// );
+
+endmodule
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/cicFilter.v

@@ -0,0 +1,100 @@
+module cicFilter 
+#(
+	parameter N = 2,	//filter order
+	parameter M = 1,	//comb delay
+	// parameter R = 4,	//decim fartor
+	parameter	filteredDataWidth	=	24,
+	parameter	inOutDataWidth	=	16,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [2:0]	DecimFactor_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+	
+wire	[filteredDataWidth-1:0]	inData	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	intFilteredData	[N-1:0];
+wire	intFilteredDataValid	[N-1:0];
+wire	intDataVal	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	decimIntData;
+wire	decimIntDataValid;
+
+wire	[filteredDataWidth-1:0]	combFilteredData	[N-1:0];
+wire	[filteredDataWidth-1:0]	combInData	[N-1:0];
+wire	combDataVal	[N-1:0];
+wire	combFilteredDataVal	[N-1:0];
+
+genvar i,j;
+generate 
+	for (i=0; i<N; i=i+1)	begin: IntFilterGen
+	
+		// assign	inData	[i]		=	(i==0)?{{filteredDataWidth-inOutDataWidth{Data_i[inOutDataWidth-1]}},Data_i}:intFilteredData[i-1][filteredDataWidth-1-:filteredDataWidth];
+		assign	inData	[i]		=	(i==0)?Data_i:intFilteredData[i-1];
+		assign	intDataVal[i]	=	(i==0)?DataNd_i:intFilteredDataValid[i-1];
+		
+		intFilterWrapper
+		#(
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(filteredDataWidth)
+		)
+		intFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Data_i		(inData[i]),
+			.DataNd_i	(intDataVal[i]),
+			.Data_o		(intFilteredData[i]),
+			.DataValid_o(intFilteredDataValid[i])
+		);
+	end
+	
+		decimBlock
+		#(	
+			// .R	(R),
+			.inOutDataWidth	(filteredDataWidth),
+			.decimCntWidth	(decimCntWidth)
+		)
+		decimBlockInst
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.DecimFactor_i	(DecimFactor_i),
+			.Data_i			(intFilteredData[N-1]),
+			.DataNd_i		(intFilteredDataValid[N-1]),
+			.Data_o			(decimIntData),
+			.DataValid_o	(decimIntDataValid)
+		);	
+
+	
+	for (j=0; j<N; j=j+1)	begin: CombFilterGen
+	
+		assign	combInData	[j]	=	(j==0)?decimIntData:combFilteredData[j-1];
+		assign	combDataVal	[j]	=	(j==0)?decimIntDataValid:combFilteredDataVal[j-1];
+		
+		combFilterWrapper
+		#(
+			.M (M),
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(filteredDataWidth)
+		)
+		combFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Rst_i		(Rst_i),
+			.Data_i		(combInData[j]),
+			.DataNd_i	(combDataVal[j]),
+			.Data_o		(combFilteredData[j]),
+			.DataValid_o(combFilteredDataVal[j])
+		);
+	end
+endgenerate
+
+assign	Data_o	=	combFilteredData[N-1];
+assign	DataValid_o	=	combFilteredDataVal[N-1];
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/combFilterBlock.v

@@ -0,0 +1,63 @@
+module combFilterBlock 
+#(
+	parameter	M=4,
+	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg ndReg;
+reg	signed	[inOutDataWidth-1:0]	inReg;
+reg signed	[inOutDataWidth-1:0]	sumResult;
+reg	dataValid;
+reg	signed	[inOutDataWidth-1:0] delData	[M-1:0];
+
+	always	@(posedge Clk_i)	begin
+		if	(!Rst_i)	begin
+			ndReg <= DataNd_i;
+			if	(DataNd_i)	begin
+				inReg	<=	Data_i;
+			end
+		end	else	begin
+			ndReg	<=	0;
+			inReg	<=	0;
+		end
+	end
+
+genvar i;
+generate 
+	for (i=0; i<M; i=i+1)	begin:combGen
+		always	@(posedge	Clk_i)	begin
+			if	(i==0)	begin
+				delData	[i]	<=	inReg;
+			end	else	begin
+				delData	[i]	<=	delData[i-1];
+			end
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(ndReg)	begin
+				sumResult	<=	inReg+-delData[M-1];
+				dataValid	<=	1'b1;
+			end	else	begin
+				dataValid	<=	1'b0;
+			end
+		end	else	begin
+			sumResult	<=	0;
+			dataValid	<=	1'b0;
+		end
+	end
+endgenerate
+
+assign	Data_o	=	sumResult;
+assign	DataValid_o	=	dataValid;
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/combFilterWrapper.v

@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module combFilterWrapper
+#(
+	parameter	M = 4,
+	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] combOutData;
+	wire combOutDataValid;
+	
+	combFilterBlock 
+	#(	.M(M),
+		.filteredDataWidth	(filteredDataWidth),
+		.inOutDataWidth	(inOutDataWidth)
+	)
+	combFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Rst_i(Rst_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+	
+	
+	// roundSymmetric 
+	// #( 
+		// .inDataWidth(inOutDataWidth),
+		// .outDataWidth(inOutDataWidth)
+	// )
+	// combRoundInst
+	// (
+		// .Rst_i(1'b0),
+		// .Clk_i(Clk_i),
+		// .Data_i(combOutData),
+		// .DataNd_i(combOutDataValid),
+		// .Data_o(Data_o),
+		// .DataValid_o(DataValid_o)
+	// );
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/decimBlock.v

@@ -0,0 +1,73 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:42:08 10/27/2020 
+// Design Name: 
+// Module Name:    decimBlock 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module decimBlock
+#(	
+	// parameter	R	=	2,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [2:0]	DecimFactor_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg	[decimCntWidth-1:0]	decimCnt;
+reg	[inOutDataWidth-1:0]	dataReg;
+reg	valReg;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(DataNd_i)	begin
+			if	(decimCnt	==	DecimFactor_i-1)	begin
+				decimCnt	<=	{decimCntWidth{1'b0}};
+				valReg		<=	1'b1;
+			end	else	begin
+				decimCnt	<=	decimCnt+7'd1;
+				valReg		<=	1'b0;
+			end
+		end	else	begin
+			decimCnt	<=	{decimCntWidth{1'b0}};
+			valReg		<=	1'b0;
+		end
+	end	else	begin
+		decimCnt	<=	{decimCntWidth{1'b0}};
+		valReg		<=	1'b0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(decimCnt	==	DecimFactor_i-1)	begin
+			dataReg	<=	Data_i;
+		end	
+	end	else	begin
+		dataReg	<=	0;
+	end
+end
+
+assign	Data_o	=	dataReg;
+assign	DataValid_o	=	valReg;
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/intFilterBlock.v

@@ -0,0 +1,38 @@
+module intFilterBlock 
+#(	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	reg [1:0] ndShReg;
+	
+	always @ (posedge Clk_i)
+		ndShReg <= {ndShReg[0:0], DataNd_i};
+	
+	reg signed [inOutDataWidth-1:0] inReg;
+	reg signed [filteredDataWidth-1:0] sumResult;
+	
+	always	@(posedge	Clk_i)	begin
+		if (DataNd_i)	begin
+			inReg <= Data_i;
+		end
+	end
+	
+	always @ (posedge Clk_i)	begin
+		if (ndShReg[0])	begin
+			sumResult <= inReg + sumResult;
+		end	else	begin
+			sumResult <= 0;
+		end
+	end
+
+	assign Data_o = sumResult;
+	assign DataValid_o = ndShReg[1];
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/intFilterWrapper.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module intFilterWrapper
+#(	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] intOutData;
+	wire intOutDataValid;
+	
+	intFilterBlock 
+	#(	.inOutDataWidth	(inOutDataWidth),
+		.filteredDataWidth	(filteredDataWidth)
+	)
+	intFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+	
+	// roundSymmetric 
+	// #( 
+		// .inDataWidth(filteredDataWidth),
+		// .outDataWidth(inOutDataWidth)
+	// )
+	// intRoundInst
+	// (
+		// .Rst_i(1'b0),
+		// .Clk_i(Clk_i),
+		// .Data_i(intOutData),
+		// .DataNd_i(intOutDataValid),
+		// .Data_o(Data_o),
+		// .DataValid_o(DataValid_o)
+	// );	
+endmodule

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/roundSymmetric.v

@@ -0,0 +1,36 @@
+module roundSymmetric 
+#( 
+	parameter inDataWidth = 35,
+	parameter outDataWidth = 17
+)
+(
+	input Rst_i,
+	input Clk_i,
+	input [inDataWidth-1 : 0] Data_i,
+	input DataNd_i,
+	output [outDataWidth-1 : 0] Data_o,
+	output DataValid_o
+);
+	
+	parameter [inDataWidth-1 : 0] addPositive = 2**(inDataWidth-outDataWidth-1);
+	parameter [inDataWidth-1 : 0] addNegative = 2**(inDataWidth-outDataWidth-1)-1;
+	
+	reg [inDataWidth-1 : 0] corrData;
+	always @ (posedge Clk_i or posedge Rst_i)
+		if (Rst_i)
+			corrData <= 0;
+		else if (DataNd_i)
+			begin
+				if (Data_i[inDataWidth-1])
+					corrData <= Data_i + addNegative;
+				else 
+					corrData <= Data_i + addPositive;
+			end
+			
+	assign Data_o = corrData[inDataWidth-1 : inDataWidth-outDataWidth];
+	
+	reg outDataValidReg;
+	always @ (posedge Clk_i) outDataValidReg <= DataNd_i;
+	assign DataValid_o = outDataValidReg;
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/GainOverloadControl/AdcTb.v

@@ -0,0 +1,707 @@
+`timescale 1ps/1ps
+
+module AdcTb;
+
+    `include "tb.vh"
+
+    parameter           CLOCK_PERIOD_24             = 41666;
+    parameter           CLOCK_PERIOD_50             = 20000;
+    parameter           UUT_CLOCK_PERIOD            = 10000;    //  100 MHz
+    parameter           ADC_DATA_CLOCK              = 1428;
+
+    localparam          TOP_BULK_PACKET_WIDTH       = 16;           //  Packet width
+    localparam          TOP_FX3_DQ_W                = 16;           //  FX3 bus width
+    localparam          TOP_FX3_CONTROL_BIT_SIZE    = 2*8192;       //  FX3 control endpoint bit size
+    localparam          TOP_FX3_BULK_BIT_SIZE       = 8192;         //  FX3 bulk endpoint bit size
+    localparam          TOP_FX3_WR_WATERMARK        = 4;            //  FX3 write watermark value
+    localparam          TOP_FX3_RD_WATERMARK        = 4;            //  FX3 read watermark value
+    localparam  [1:0]   TOP_FX3_RD_ID0_ADDR         = 2'b00;        //  FX3 bus address for bulk ep. transfer
+    localparam  [1:0]   TOP_FX3_RD_ID1_ADDR         = 2'b11;        //  FX3 bus address for control ep. transfer
+    localparam          TOP_CMD_NUM                 = 32;           //  Must be equal to power of 2
+    localparam          TOP_CONTROL_CMD_NUM         = 32;           //  Must be equal to power of 2
+    localparam          TOP_CMD_ID_NORM             = 224;
+    localparam          TOP_AUX_IN_TRIG_NUM         = 1;            //  Number of aux. input triggers
+    localparam          TOP_AUX_OUT_TRIG_NUM        = 1;            //  Number of aux. output triggers
+    localparam          TOP_MODULATOR_NUM           = 3;            //  Number of modulators
+    localparam          TOP_PULSE_GEN_NUM           = 3;            //  Number of pulse generators
+    localparam  [1:0]   TOP_FX3_WR_ID0_ADDR         = 2'b01;        //  FX3 bus address for bulk ep. transfer
+    localparam  [1:0]   TOP_FX3_WR_ID1_ADDR         = 2'b10;        //  FX3 bus address for control ep. transfe
+    localparam  [6:0]   ADC_CLOCK_PATTERN           = 7'b1111110;
+
+    localparam          TOP_DSP_CH_NUM              = 8;            //  Number of input data channels
+    localparam          TOP_DSP_IDAT_W              = 14;           //  Input data width
+    localparam          TOP_DSP_IQ_W                = 14;           //  I and Q width
+    localparam          TOP_DSP_OMULT_W             = 16;           //  sin window nultiplier output width
+    localparam          TOP_DSP_ODAT_W              = 48;           //  Output data width
+    localparam          TOP_DSP_EN_DEBUG            = "YES";        //  YES or NO
+
+    reg                 test_clk_24mhz;
+    reg                 test_clk_50mhz;
+
+    wire                adc1_ctrl_sck_o;
+    wire                adc1_ctrl_sdata_o;
+    wire                adc1_ctrl_ss_o;
+    wire                adc1_ctrl_reset_o;
+
+    wire                adc2_ctrl_sck_o;
+    wire                adc2_ctrl_sdata_o;
+    wire                adc2_ctrl_ss_o;
+    wire                adc2_ctrl_reset_o;
+
+    wire                adc3_ctrl_sck_o;
+    wire                adc3_ctrl_sdata_o;
+    wire                adc3_ctrl_ss_o;
+    wire                adc3_ctrl_reset_o;
+
+    wire                adc4_ctrl_sck_o;
+    wire                adc4_ctrl_sdata_o;
+    wire                adc4_ctrl_ss_o;
+    wire                adc4_ctrl_reset_o;
+
+    wire                ref_clk_lmx_cs_o;
+    wire                ref_clk_lmk_cs_o;
+    wire                ref_clk_sck_o;
+    wire                ref_clk_sdata_o;
+    wire                ref_clk_lmx_lock_i;
+    wire                ref_clk_switch_o;
+
+    wire    [15:0]      mcb5_dram_dq;
+    wire    [12:0]      mcb5_dram_a;
+    wire    [2:0]       mcb5_dram_ba;
+    wire                mcb5_dram_ras_n;
+    wire                mcb5_dram_cas_n;
+    wire                mcb5_dram_we_n;
+    wire                mcb5_dram_odt;
+    wire                mcb5_dram_reset_n;
+    wire                mcb5_dram_cke;
+    wire                mcb5_dram_dm;
+    wire                mcb5_dram_udqs;
+    wire                mcb5_dram_udqs_n;
+    wire                mcb5_rzq;
+    wire                mcb5_zio;
+    wire                mcb5_dram_udm;
+    wire                mcb5_dram_dqs;
+    wire                mcb5_dram_dqs_n;
+    wire                mcb5_dram_ck;
+    wire                mcb5_dram_ck_n;
+    wire    [15:0]      mcb1_dram_dq;
+    wire    [12:0]      mcb1_dram_a;
+    wire    [2:0]       mcb1_dram_ba;
+    wire                mcb1_dram_ras_n;
+    wire                mcb1_dram_cas_n;
+    wire                mcb1_dram_we_n;
+    wire                mcb1_dram_odt;
+    wire                mcb1_dram_reset_n;
+    wire                mcb1_dram_cke;
+    wire                mcb1_dram_dm;
+    wire                mcb1_dram_udqs;
+    wire                mcb1_dram_udqs_n;
+    wire                mcb1_rzq;
+    wire                mcb1_zio;
+    wire                mcb1_dram_udm;
+    wire                mcb1_dram_dqs;
+    wire                mcb1_dram_dqs_n;
+    wire                mcb1_dram_ck;
+    wire                mcb1_dram_ck_n;
+
+    //  Cypress FX3
+
+    wire                        fx3_pclk_o;
+    wire                        fx3_slcs_o;
+    wire                        fx3_slrd_o;
+    wire                        fx3_slwr_o;
+    wire                        fx3_sloe_o;
+    wire                        fx3_pktend_o; 
+    wire                        fx3_flaga_i;
+    wire                        fx3_flagb_i;
+    wire    [1:0]               fx3_addr_o;
+    wire    [TOP_FX3_DQ_W-1:0]  fx3_dq_io;
+
+    wire                        lo_sdata1_o;
+    wire                        lo_sdata2_o;
+    wire                        lo_cs_o;
+    wire                        lo_sck_o;
+    wire                        rf1_sdata1_o;
+    wire                        rf1_sdata2_o;
+    wire                        rf1_cs_o;
+    wire                        rf1_sck_o;
+    wire                        rf2_sdata1_o;
+    wire                        rf2_sdata2_o;
+    wire                        rf2_cs_o;
+    wire                        rf2_sck_o;
+
+    reg     [TOP_FX3_DQ_W-1:0]  fx3_ram_rd0_data_i;
+    reg                         fx3_ram_rd0_val_i;
+    wire                        fx3_ram_rd0_rdy_o;
+    reg                         fx3_ram_rd0_eop_i;
+
+    reg     [TOP_FX3_DQ_W-1:0]  fx3_ram_rd1_data_i;
+    reg                         fx3_ram_rd1_val_i;
+    wire                        fx3_ram_rd1_rdy_o;
+    reg                         fx3_ram_rd1_eop_i;
+
+    wire    [TOP_FX3_DQ_W-1:0]  fx3_ram_wr0_data_o;
+    wire                        fx3_ram_wr0_val_o;
+    reg                         fx3_ram_wr0_rdy_i;
+
+    wire    [TOP_FX3_DQ_W-1:0]  fx3_ram_wr1_data_o;
+    wire                        fx3_ram_wr1_val_o;
+    reg                         fx3_ram_wr1_rdy_i;
+
+    wire                        ext_clk_24mhz_gbl       = uut.ext_clk_24mhz_gbl;
+    wire                        init_rst_signal         = uut.init_rst_signal;
+    wire                        lmx_lmk_filtered_rst    = uut.lmx_lmk_filtered_rst;
+    wire                        ddr3_mic_filtered_rst   = uut.ddr3_mic_filtered_rst;
+    wire                        adc_done                = uut.adc_done;
+    wire                        adc_rst                 = uut.adc_rst;
+    wire                        adc_rst_done            = uut.adc_rst_done;
+    wire                        adc_filtered_rst        = uut.adc_filtered_rst;
+    wire                        adc_init_valid          = uut.adc_init_valid;
+    wire                        main_pll_100_mhz_locked = uut.main_pll_100_mhz_locked;
+    wire                        main_pll_rst_signal     = uut.main_pll_rst_signal;
+
+    wire                        main_pll_100mhz         = uut.main_pll_100mhz;
+    wire                        main_pll_locked         = uut.main_pll_locked;
+    wire                        c1_calib_done           = uut.c1_calib_done;
+    wire                        c5_calib_done           = uut.c5_calib_done;
+    wire                        cmd_handler_ready       = uut.cmd_handler_ready;
+/*
+    wire    [735:0]             ddr3_mic_wrapper_data_i     = uut.ddr3_mic_wrapper_data_i ;
+    wire    [22:0]              ddr3_mic_wrapper_valid_i    = uut.ddr3_mic_wrapper_valid_i;
+    wire    [22:0]              ddr3_mic_wrapper_ready_o    = uut.ddr3_mic_wrapper_ready_o;
+
+    wire    [31:0]              ch1_i                       = ddr3_mic_wrapper_data_i[703:672];       
+    wire    [31:0]              ch1_q                       = ddr3_mic_wrapper_data_i[671:640];
+    
+    wire    [31:0]              ch2_i                       = ddr3_mic_wrapper_data_i[639:608];       
+    wire    [31:0]              ch2_q                       = ddr3_mic_wrapper_data_i[607:576];       
+
+    wire    [TOP_FX3_DQ_W-1:0]  out_stream_data_piped   = uut.out_stream_data_piped;
+    wire                        out_stream_valid_piped  = uut.out_stream_valid_piped;
+    wire                        out_stream_ready_piped  = uut.out_stream_ready_piped;
+    wire                        out_stream_last_piped   = uut.out_stream_last_piped;
+    wire                        out_stream_id_piped     = uut.out_stream_id_piped;
+    wire    [3:0]               sm_curr_state           = uut.cmd_handler_inst.sm_curr_state;
+
+    wire                        lo_init_done    = uut.lo_init_done;
+    wire                        lo_done         = uut.lo_done;
+    wire                        rf1_init_done   = uut.rf1_init_done;
+    wire                        rf1_done        = uut.rf1_done;
+    wire                        rf2_init_done   = uut.rf2_init_done;
+    wire                        rf2_done        = uut.rf2_done;
+    wire    [15:0]              rf1_data        = uut.rf1_data;
+    wire                        rf1_valid       = uut.rf1_valid;
+    wire    [15:0]              rf2_data        = uut.rf2_data;
+    wire                        rf2_valid       = uut.rf2_valid;
+
+    wire    [7:0]                                   cmd_ffe1_logic_channel_o                = uut.cmd_ffe1_logic_channel_o;
+    wire    [7:0]                                   cmd_ffe1_mode_o                         = uut.cmd_ffe1_mode_o;
+    wire    [31:0]                                  cmd_ffe1_filter_band_o                  = uut.cmd_ffe1_filter_band_o;
+    wire    [31:0]                                  cmd_ffe1_meas_num_o                     = uut.cmd_ffe1_meas_num_o;
+    wire    [31:0]                                  cmd_ffe1_meas_delay_o                   = uut.cmd_ffe1_meas_delay_o;
+    wire    [31:0]                                  cmd_ffe1_meas_period_o                  = uut.cmd_ffe1_meas_period_o;
+    wire    [7:0]                                   cmd_ffe1_analog_filter_o                = uut.cmd_ffe1_analog_filter_o;
+    wire    [7:0]                                   cmd_ffe1_set_ftw_o                      = uut.cmd_ffe1_set_ftw_o;
+    wire    [31:0]                                  cmd_ffe1_demod_ftw_o                    = uut.cmd_ffe1_demod_ftw_o;
+    wire                                            cmd_ffe1_new_flag_o                     = uut.cmd_ffe1_new_flag_o;
+
+    wire    [31:0]                                  filter_meas_width_o                     = uut.filter_meas_width_o;
+    wire    [31:0]                                  filter_phase_inc_o                      = uut.filter_phase_inc_o;
+    wire    [31:0]                                  filter_norm_value_o                     = uut.filter_norm_value_o;
+    wire                                            filter_data_valid_o                     = uut.filter_data_valid_o;
+
+    wire    [TOP_DSP_CH_NUM*32-1:0]                 fp_dsp_data_i_o                         = uut.fp_dsp_data_i_o;
+    wire    [TOP_DSP_CH_NUM*32-1:0]                 fp_dsp_data_q_o                         = uut.fp_dsp_data_q_o;
+    wire    [TOP_DSP_CH_NUM-1:0]                    fp_dsp_valid_i_o                        = uut.fp_dsp_valid_i_o;
+    wire    [TOP_DSP_CH_NUM-1:0]                    fp_dsp_valid_q_o                        = uut.fp_dsp_valid_q_o;
+/*
+    wire    [15:0]                                  cmd_fff7_rf_data_o                      = uut.cmd_fff7_rf_data_o;
+    wire                                            cmd_fff7_rf_valid_o                     = uut.cmd_fff7_rf_valid_o;
+    wire                                            cmd_fff7_new_flag_o                     = uut.cmd_fff7_new_flag_o;
+
+    wire    [15:0]                                  cmd_fff8_rf_data_o                      = uut.cmd_fff8_rf_data_o;
+    wire                                            cmd_fff8_rf_valid_o                     = uut.cmd_fff8_rf_valid_o;
+    wire                                            cmd_fff8_new_flag_o                     = uut.cmd_fff8_new_flag_o;
+
+    wire    [31:0]                                  cmd_fffc_delay_code_o                   = uut.cmd_fffc_delay_code_o;
+    wire    [7:0]                                   cmd_fffc_port_o                         = uut.cmd_fffc_port_o;
+    wire    [7:0]                                   cmd_fffc_rf_load_mask_o                 = uut.cmd_fffc_rf_load_mask_o;
+    wire    [31:0]                                  cmd_fffc_port_switch_delay_o            = uut.cmd_fffc_port_switch_delay_o;
+    wire                                            cmd_fffc_new_flag_o                     = uut.cmd_fffc_new_flag_o;
+    wire                                            cmd_fffc_port_switch_flag_o             = uut.cmd_fffc_port_switch_flag_o;
+    wire    [3:0]                                   cmd_fffc_curr_port_o                    = uut.cmd_fffc_curr_port_o;
+    wire    [31:0]                                  cmd_fffc_curr_delay_o                   = uut.cmd_fffc_curr_delay_o;
+
+    wire    [15:0]                                  cmd_meas_lo_data_o                      = uut.cmd_meas_lo_data_o;
+    wire                                            cmd_meas_lo_valid_o                     = uut.cmd_meas_lo_valid_o;
+    wire    [15:0]                                  cmd_meas_rf_data_o                      = uut.cmd_meas_rf_data_o;
+    wire                                            cmd_meas_rf_valid_o                     = uut.cmd_meas_rf_valid_o;
+    wire                                            cmd_meas_new_flag_o                     = uut.cmd_meas_new_flag_o;
+
+    wire    [TOP_FX3_DQ_W-1:0]                      cmd_demuxed_meas_data                   = uut.cmd_demuxed_meas_data ;
+    wire                                            cmd_demuxed_meas_valid                  = uut.cmd_demuxed_meas_valid;
+    wire                                            cmd_demuxed_meas_last                   = uut.cmd_demuxed_meas_last ;
+
+    wire    [TOP_FX3_DQ_W-1:0]                      cmd_handler_m_data_o                    = uut.cmd_handler_m_data_o;
+    wire                                            cmd_handler_m_valid_o                   = uut.cmd_handler_m_valid_o;
+    wire                                            cmd_handler_m_ready_i                   = uut.cmd_handler_m_ready_i;
+    wire                                            cmd_handler_m_last_o                    = uut.cmd_handler_m_last_o;
+    wire    [7:0]                                   cmd_handler_m_id_o                      = uut.cmd_handler_m_id_o;
+
+    wire                                            cmd_handler_block_req_o                 = uut.cmd_handler_block_req_o;
+    wire    [2:0]                                   cmd_handler_block_mask_o                = uut.cmd_handler_block_mask_o;
+    wire                                            cmd_handler_block_ack_i                 = uut.cmd_handler_block_ack_i;
+    wire                                            cmd_handler_meas_req_o                  = uut.cmd_handler_meas_req_o;
+    wire                                            cmd_handler_meas_ack_i                  = uut.cmd_handler_meas_ack_i;
+    wire                                            cmd_handler_ans_req_o                   = uut.cmd_handler_ans_req_o;
+    wire                                            cmd_handler_ans_ack_i                   = uut.cmd_handler_ans_ack_i;
+    wire    [31:0]                                  cmd_handler_cmd_head_o                  = uut.cmd_handler_cmd_head_o;
+    wire    [15:0]                                  cmd_handler_cmd_data_o                  = uut.cmd_handler_cmd_data_o;
+
+    wire                                            cmd_handler_perm_before_meas_i          = uut.cmd_handler_perm_before_meas_i;
+    wire                                            cmd_handler_perm_after_meas_i           = uut.cmd_handler_perm_after_meas_i;
+    wire                                            cmd_handler_perm_after_sweep_i          = uut.cmd_handler_perm_after_sweep_i;
+    wire                                            cmd_handler_event_meas_req_o            = uut.cmd_handler_event_meas_req_o;
+    wire                                            cmd_handler_event_before_meas_o         = uut.cmd_handler_event_before_meas_o;
+    wire                                            cmd_handler_event_after_meas_o          = uut.cmd_handler_event_after_meas_o;
+    wire                                            cmd_handler_event_sweep_end_o           = uut.cmd_handler_event_sweep_end_o;
+*/
+
+/*
+always @(negedge fx3_pclk_o) begin
+    if (cmd_ffe1_new_flag_o) begin
+        $display("cmd_ffe1_logic_channel_o      = %h", cmd_ffe1_logic_channel_o);
+        $display("cmd_ffe1_mode_o               = %h", cmd_ffe1_mode_o);
+        $display("cmd_ffe1_filter_band_o        = %h", cmd_ffe1_filter_band_o);
+        $display("cmd_ffe1_meas_num_o           = %h", cmd_ffe1_meas_num_o);
+        $display("cmd_ffe1_meas_delay_o         = %h", cmd_ffe1_meas_delay_o);
+        $display("cmd_ffe1_meas_period_o        = %h", cmd_ffe1_meas_period_o);
+        $display("cmd_ffe1_analog_filter_o      = %h", cmd_ffe1_analog_filter_o);
+        $display("cmd_ffe1_set_ftw_o            = %h", cmd_ffe1_set_ftw_o);
+        $display("cmd_ffe1_demod_ftw_o          = %h", cmd_ffe1_demod_ftw_o);
+    end
+end
+
+always @(negedge fx3_pclk_o) begin
+    if (cmd_fffc_new_flag_o) begin
+        $display("cmd_fffc_delay_code_o         = %h", cmd_fffc_delay_code_o);
+        $display("cmd_fffc_port_o               = %h", cmd_fffc_port_o);
+        $display("cmd_fffc_rf_load_mask_o       = %h", cmd_fffc_rf_load_mask_o);
+        $display("cmd_fffc_port_switch_delay_o  = %h", cmd_fffc_port_switch_delay_o);
+        $display("cmd_fffc_port_switch_flag_o   = %h", cmd_fffc_port_switch_flag_o);
+        $display("cmd_fffc_curr_port_o          = %h", cmd_fffc_curr_port_o);
+        $display("cmd_fffc_curr_delay_o         = %h", cmd_fffc_curr_delay_o);
+    end
+end    
+
+always @(negedge fx3_pclk_o) begin
+    if (cmd_fff7_rf_valid_o) begin
+        $display("FFF7 data                     = %h", cmd_fff7_rf_data_o);
+    end
+end
+
+always @(negedge fx3_pclk_o) begin
+    if (cmd_fff8_rf_valid_o) begin
+        $display("FFF8 data                     = %h", cmd_fff8_rf_data_o);
+    end
+end
+
+always @(negedge fx3_pclk_o) begin
+    if (cmd_meas_lo_valid_o) begin
+        $display("MEAS LO DATA                  = %h", cmd_meas_lo_data_o);
+    end
+
+    if (cmd_meas_rf_valid_o) begin
+        $display("MEAS RF DATA                  = %h", cmd_meas_rf_data_o);
+    end
+
+end
+*/
+
+    integer fid0_in;
+    integer fid1_in;
+    integer len;
+    integer i;
+
+    assign  ref_clk_lmx_lock_i  = 1'b0;
+
+    task automatic read_data;
+        input   integer         fid;
+        output  reg     [15:0]  data;
+        output  integer         len;
+        begin
+            len = $fread(data, fid);
+        end
+    endtask
+
+c3420_main uut(
+    .ext_clk_24mhz_i        (test_clk_24mhz),
+
+    .adc1_ctrl_sck_o        (adc1_ctrl_sck_o),
+    .adc1_ctrl_sdata_o      (adc1_ctrl_sdata_o),
+    .adc1_ctrl_ss_o         (adc1_ctrl_ss_o),
+/*
+    .adc1_ctrl_gain_a_o     (),
+    .adc1_ctrl_gain_b_o     (),
+    .adc1_ctrl_filter_o     (),
+    .adc1_ctrl_dither_o     (),
+*/
+    .adc1_ctrl_reset_o      (adc1_ctrl_reset_o),
+
+    .adc1_fclk_i_p          (test_clk_50mhz),
+    .adc1_fclk_i_n          (~test_clk_50mhz),
+    .adc1_ch_a0_i_p         (),
+    .adc1_ch_a0_i_n         (),
+    .adc1_ch_a1_i_p         (),
+    .adc1_ch_a1_i_n         (),
+    .adc1_ch_b0_i_p         (),
+    .adc1_ch_b0_i_n         (),
+    .adc1_ch_b1_i_p         (),
+    .adc1_ch_b1_i_n         (),
+
+    .adc2_ctrl_sck_o        (adc2_ctrl_sck_o),
+    .adc2_ctrl_sdata_o      (adc2_ctrl_sdata_o),
+    .adc2_ctrl_ss_o         (adc2_ctrl_ss_o),
+/*
+    .adc2_ctrl_gain_a_o     (),
+    .adc2_ctrl_gain_b_o     (),
+    .adc2_ctrl_filter_o     (),
+    .adc2_ctrl_dither_o     (),
+*/
+    .adc2_ctrl_reset_o      (adc2_ctrl_reset_o),
+/*
+    .adc2_ch_a0_i_p         (),
+    .adc2_ch_a0_i_n         (),
+    .adc2_ch_a1_i_p         (),
+    .adc2_ch_a1_i_n         (),
+    .adc2_ch_b0_i_p         (),
+    .adc2_ch_b0_i_n         (),
+    .adc2_ch_b1_i_p         (),
+    .adc2_ch_b1_i_n         (),
+*/
+    .adc3_ctrl_sck_o        (adc3_ctrl_sck_o),
+    .adc3_ctrl_sdata_o      (adc3_ctrl_sdata_o),
+    .adc3_ctrl_ss_o         (adc3_ctrl_ss_o),
+/*
+    .adc3_ctrl_gain_a_o     (),
+    .adc3_ctrl_gain_b_o     (),
+    .adc3_ctrl_filter_o     (),
+    .adc3_ctrl_dither_o     (),
+*/
+    .adc3_ctrl_reset_o      (adc3_ctrl_reset_o),
+
+    .adc3_fclk_i_p          (test_clk_50mhz),
+    .adc3_fclk_i_n          (~test_clk_50mhz),
+
+    .adc3_ch_a0_i_p         (1'b1),
+    .adc3_ch_a0_i_n         (1'b0),
+    .adc3_ch_a1_i_p         (1'b0),
+    .adc3_ch_a1_i_n         (1'b1),
+    .adc3_ch_b0_i_p         (1'b1),
+    .adc3_ch_b0_i_n         (1'b0),
+    .adc3_ch_b1_i_p         (1'b1),
+    .adc3_ch_b1_i_n         (1'b0),
+
+    .adc4_ctrl_sck_o        (adc4_ctrl_sck_o),
+    .adc4_ctrl_sdata_o      (adc4_ctrl_sdata_o),
+    .adc4_ctrl_ss_o         (adc4_ctrl_ss_o),
+/*
+    .adc4_ctrl_gain_a_o     (),
+    .adc4_ctrl_gain_b_o     (),
+    .adc4_ctrl_filter_o     (),
+    .adc4_ctrl_dither_o     (),
+*/
+    .adc4_ctrl_reset_o      (adc4_ctrl_reset_o),
+/*
+    .adc4_fclk_i_p          (),
+    .adc4_fclk_i_n          (),
+    .adc4_ch_a0_i_p         (),
+    .adc4_ch_a0_i_n         (),
+    .adc4_ch_a1_i_p         (),
+    .adc4_ch_a1_i_n         (),
+    .adc4_ch_b0_i_p         (),
+    .adc4_ch_b0_i_n         (),
+    .adc4_ch_b1_i_p         (),
+    .adc4_ch_b1_i_n         (),
+*/
+    .pg_pulse0_o            (),
+    .pg_pulse1_o            (),
+    .pg_pulse2_o            (),
+    .pg_pulse3_o            (),
+
+    .mod_pulse0_o           (),
+    .mod_pulse1_o           (),
+
+    .ref_clk_lmx_cs_o       (ref_clk_lmx_cs_o),
+    .ref_clk_lmk_cs_o       (ref_clk_lmk_cs_o),
+    .ref_clk_sck_o          (ref_clk_sck_o),
+    .ref_clk_sdata_o        (ref_clk_sdata_o),
+    .ref_clk_lmx_lock_i     (ref_clk_lmx_lock_i),
+    .ref_clk_switch_o       (ref_clk_switch_o),
+
+    .ref_clk_i2c_scl_o      (),
+    .ref_clk_i2c_sda_io     (),
+
+    .mcb5_dram_dq           (mcb5_dram_dq),
+    .mcb5_dram_a            (mcb5_dram_a),
+    .mcb5_dram_ba           (mcb5_dram_ba),
+    .mcb5_dram_ras_n        (mcb5_dram_ras_n),
+    .mcb5_dram_cas_n        (mcb5_dram_cas_n),
+    .mcb5_dram_we_n         (mcb5_dram_we_n),
+    .mcb5_dram_odt          (mcb5_dram_odt),
+    .mcb5_dram_reset_n      (mcb5_dram_reset_n),
+    .mcb5_dram_cke          (mcb5_dram_cke),
+    .mcb5_dram_dm           (mcb5_dram_dm),
+    .mcb5_dram_udqs         (mcb5_dram_udqs),
+    .mcb5_dram_udqs_n       (mcb5_dram_udqs_n),
+    .mcb5_rzq               (mcb5_rzq),
+    .mcb5_zio               (mcb5_zio),
+    .mcb5_dram_udm          (mcb5_dram_udm),
+    .mcb5_dram_dqs          (mcb5_dram_dqs),
+    .mcb5_dram_dqs_n        (mcb5_dram_dqs_n),
+    .mcb5_dram_ck           (mcb5_dram_ck),
+    .mcb5_dram_ck_n         (mcb5_dram_ck_n),
+
+    .mcb1_dram_dq           (mcb1_dram_dq),
+    .mcb1_dram_a            (mcb1_dram_a),
+    .mcb1_dram_ba           (mcb1_dram_ba),
+    .mcb1_dram_ras_n        (mcb1_dram_ras_n),
+    .mcb1_dram_cas_n        (mcb1_dram_cas_n),
+    .mcb1_dram_we_n         (mcb1_dram_we_n),
+    .mcb1_dram_odt          (mcb1_dram_odt),
+    .mcb1_dram_reset_n      (mcb1_dram_reset_n),
+    .mcb1_dram_cke          (mcb1_dram_cke),
+    .mcb1_dram_dm           (mcb1_dram_dm),
+    .mcb1_dram_udqs         (mcb1_dram_udqs),
+    .mcb1_dram_udqs_n       (mcb1_dram_udqs_n),
+    .mcb1_rzq               (mcb1_rzq),
+    .mcb1_zio               (mcb1_zio),
+    .mcb1_dram_udm          (mcb1_dram_udm),
+    .mcb1_dram_dqs          (mcb1_dram_dqs),
+    .mcb1_dram_dqs_n        (mcb1_dram_dqs_n),
+    .mcb1_dram_ck           (mcb1_dram_ck),
+    .mcb1_dram_ck_n         (mcb1_dram_ck_n),
+
+    .fx3_pclk_o             (fx3_pclk_o),
+    .fx3_slcs_o             (fx3_slcs_o),
+    .fx3_slrd_o             (fx3_slrd_o),
+    .fx3_slwr_o             (fx3_slwr_o),
+    .fx3_sloe_o             (fx3_sloe_o),
+    .fx3_pktend_o           (fx3_pktend_o), 
+    .fx3_flaga_i            (fx3_flaga_i),
+    .fx3_flagb_i            (fx3_flagb_i),
+    .fx3_addr_o             (fx3_addr_o),
+    .fx3_dq_io              (fx3_dq_io),
+
+    .lo_sdata1_o            (lo_sdata1_o),
+    .lo_sdata2_o            (lo_sdata2_o),
+    .lo_cs_o                (lo_cs_o),
+    .lo_sck_o               (lo_sck_o),
+    .rf1_sdata1_o           (rf1_sdata1_o),
+    .rf1_sdata2_o           (rf1_sdata2_o),
+    .rf1_cs_o               (rf1_cs_o),
+    .rf1_sck_o              (rf1_sck_o),
+    .rf2_sdata1_o           (rf2_sdata1_o),
+    .rf2_sdata2_o           (rf2_sdata2_o),
+    .rf2_cs_o               (rf2_cs_o),
+    .rf2_sck_o              (rf2_sck_o)
+);
+
+fx3_slfifo_model #(
+    .DQ_W           (TOP_FX3_DQ_W),             //
+    .RD_IDO_WM      (TOP_FX3_RD_WATERMARK),     //
+    .RD_ID1_WM      (TOP_FX3_RD_WATERMARK),     //
+    .WR_ID0_WM      (TOP_FX3_WR_WATERMARK),     //
+    .WR_ID1_WM      (TOP_FX3_WR_WATERMARK),     //
+    .RD_ID0_ADDR    (TOP_FX3_RD_ID0_ADDR),      //
+    .RD_ID1_ADDR    (TOP_FX3_RD_ID1_ADDR),      //
+    .WR_ID0_ADDR    (TOP_FX3_WR_ID0_ADDR),      //
+    .WR_ID1_ADDR    (TOP_FX3_WR_ID1_ADDR),      // 
+    .CLOCK_PERIOD   (10000)                     //  10000 ps <-> 100 MHz
+) fx3_slfifo_model_inst (
+    //  FX3 ports
+    .PCLK               (fx3_pclk_o),
+    .SLCS               (fx3_slcs_o),
+    .SLRD               (fx3_slrd_o),
+    .SLOE               (fx3_sloe_o),
+    .SLWR               (fx3_slwr_o),
+    .A                  (fx3_addr_o),
+    .DQ                 (fx3_dq_io),
+    .FLAGA              (fx3_flaga_i),
+    .FLAGB              (fx3_flagb_i),
+    .PKTEND             (fx3_pktend_o),
+
+    .ram_rd0_data_i     (fx3_ram_rd0_data_i),
+    .ram_rd0_val_i      (fx3_ram_rd0_val_i),
+    .ram_rd0_rdy_o      (fx3_ram_rd0_rdy_o),
+    .ram_rd0_eop_i      (fx3_ram_rd0_eop_i),
+
+    .ram_rd1_data_i     (fx3_ram_rd1_data_i),
+    .ram_rd1_val_i      (fx3_ram_rd1_val_i),
+    .ram_rd1_rdy_o      (fx3_ram_rd1_rdy_o),
+    .ram_rd1_eop_i      (fx3_ram_rd1_eop_i),
+
+    .ram_wr0_data_o     (fx3_ram_wr0_data_o),
+    .ram_wr0_val_o      (fx3_ram_wr0_val_o),
+    .ram_wr0_rdy_i      (fx3_ram_wr0_rdy_i),
+
+    .ram_wr1_data_o     (fx3_ram_wr1_data_o),
+    .ram_wr1_val_o      (fx3_ram_wr1_val_o),
+    .ram_wr1_rdy_i      (fx3_ram_wr1_rdy_i)
+);
+
+always @(negedge fx3_pclk_o) begin
+    if (fx3_ram_wr0_val_o) begin
+        $display("FX3 ID0 WR DATA   = %h", {fx3_ram_wr0_data_o[7:0], fx3_ram_wr0_data_o[15:8]});
+    end
+
+    if (fx3_ram_wr1_val_o) begin
+        $display("FX3 ID1 WR DATA   = %h", fx3_ram_wr1_data_o);
+    end
+end
+
+    ddr3_model_c5 u_mem_c5(
+        .ck         (mcb5_dram_ck),
+        .ck_n       (mcb5_dram_ck_n),
+        .cke        (mcb5_dram_cke),
+        .cs_n       (1'b0),
+        .ras_n      (mcb5_dram_ras_n),
+        .cas_n      (mcb5_dram_cas_n),
+        .we_n       (mcb5_dram_we_n),
+        .dm_tdqs    ({mcb5_dram_udm,mcb5_dram_dm}),
+        .ba         (mcb5_dram_ba),
+        .addr       (mcb5_dram_a),
+        .dq         (mcb5_dram_dq),
+        .dqs        ({mcb5_dram_udqs,mcb5_dram_dqs}),
+        .dqs_n      ({mcb5_dram_udqs_n,mcb5_dram_dqs_n}),
+        .tdqs_n     (),
+        .odt        (mcb5_dram_odt),
+        .rst_n      (mcb5_dram_reset_n)
+        );
+
+    ddr3_model_c1 u_mem_c1(
+        .ck         (mcb1_dram_ck),
+        .ck_n       (mcb1_dram_ck_n),
+        .cke        (mcb1_dram_cke),
+        .cs_n       (1'b0),
+        .ras_n      (mcb1_dram_ras_n),
+        .cas_n      (mcb1_dram_cas_n),
+        .we_n       (mcb1_dram_we_n),
+        .dm_tdqs    ({mcb1_dram_udm,mcb1_dram_dm}),
+        .ba         (mcb1_dram_ba),
+        .addr       (mcb1_dram_a),
+        .dq         (mcb1_dram_dq),
+        .dqs        ({mcb1_dram_udqs,mcb1_dram_dqs}),
+        .dqs_n      ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
+        .tdqs_n     (),
+        .odt        (mcb1_dram_odt),
+        .rst_n      (mcb1_dram_reset_n)
+        );
+
+reg [31:0]  data_buf;
+integer     data_cnt;
+
+initial begin
+    fid0_in             = $fopen("./src/tb/in_data.bin", "rb");
+    fid1_in             = $fopen("./src/tb/in_control_data.bin", "rb");
+
+    data_cnt            = 0;
+
+    fx3_ram_rd0_data_i  = 0;
+    fx3_ram_rd0_val_i   = 0;
+    fx3_ram_rd0_eop_i   = 0;
+    fx3_ram_rd1_data_i  = 0;
+    fx3_ram_rd1_val_i   = 0;
+    fx3_ram_rd1_eop_i   = 0;
+    fx3_ram_wr0_rdy_i   = 1;
+    fx3_ram_wr1_rdy_i   = 1;
+
+    //  rd1
+
+    wait (fx3_pclk_o);
+    #(UUT_CLOCK_PERIOD*20);
+
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd1_val_i   = 1'b1;
+        read_data(fid1_in, fx3_ram_rd1_data_i, len);
+    end
+
+    repeat(CONTROL_DATA_NUM-2) begin
+        #(UUT_CLOCK_PERIOD/2);
+        wait(fx3_ram_rd1_rdy_o);
+        @(posedge fx3_pclk_o) begin
+            fx3_ram_rd1_val_i   = 1'b1;
+            read_data(fid1_in, fx3_ram_rd1_data_i, len);
+        end
+    end
+
+    #(UUT_CLOCK_PERIOD/2);
+    wait(fx3_ram_rd1_rdy_o);
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd1_val_i   = 1'b1;
+        fx3_ram_rd1_eop_i   = 1'b1;
+        read_data(fid1_in, fx3_ram_rd1_data_i, len);
+    end
+
+    #(UUT_CLOCK_PERIOD/2);
+    wait(fx3_ram_rd1_rdy_o);
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd1_val_i   = 1'b0;
+        fx3_ram_rd1_eop_i   = 1'b0;
+        fx3_ram_rd1_data_i  = 16'b0;
+    end
+
+    //  End rd1
+
+    #(UUT_CLOCK_PERIOD*20);
+
+    wait (fx3_pclk_o);
+    #(UUT_CLOCK_PERIOD*20);
+
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd0_val_i   = 1'b1;
+        read_data(fid0_in, fx3_ram_rd0_data_i, len);
+    end
+
+    repeat(BULK_DATA_NUM-2) begin
+        #(UUT_CLOCK_PERIOD/2);
+        wait(fx3_ram_rd0_rdy_o);
+        @(posedge fx3_pclk_o) begin
+            fx3_ram_rd0_val_i   = 1'b1;
+            read_data(fid0_in, fx3_ram_rd0_data_i, len);
+        end
+    end
+
+    #(UUT_CLOCK_PERIOD/2);
+    wait(fx3_ram_rd0_rdy_o);
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd0_val_i   = 1'b1;
+        fx3_ram_rd0_eop_i   = 1'b1;
+        read_data(fid0_in, fx3_ram_rd0_data_i, len);
+    end
+
+    #(UUT_CLOCK_PERIOD/2);
+    wait(fx3_ram_rd0_rdy_o);
+    @(posedge fx3_pclk_o) begin
+        fx3_ram_rd0_val_i   = 1'b0;
+        fx3_ram_rd0_eop_i   = 1'b0;
+        fx3_ram_rd0_data_i  = 16'b0;
+    end
+
+end
+
+initial begin
+    test_clk_24mhz  = 1'b0;
+    forever begin
+        #(CLOCK_PERIOD_24/2) test_clk_24mhz = ~test_clk_24mhz;
+    end
+end
+
+initial begin
+    test_clk_50mhz  = 1'b1;
+    forever begin
+        #(CLOCK_PERIOD_50/2) test_clk_50mhz = ~test_clk_50mhz;
+    end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/GainOverloadControl/GainControl.v

@@ -0,0 +1,172 @@
+`timescale 1ns / 1ps
+(* KEEP = "TRUE" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControl
+#(	
+	parameter	AdcNcoMultWidth	=	35,
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	input	GainAutoEn_i,
+	
+	input	signed	[AdcNcoMultWidth-1:0]	AdcCos_i,
+	input	signed	[AdcNcoMultWidth-1:0]	AdcSin_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	
+	output	GainNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	CntWidth		=	32;
+	localparam	Delay			=	100;
+	localparam	AverageDelay	=	MeasPeriod+Delay-1;
+	localparam	SumWidth		=	AdcNcoMultWidth+6-1;
+//================================================================================
+//  REG/WIRE
+	reg		[CntWidth-1:0]	measCnt;
+	
+	reg		signed	[SumWidth-1:0]	adcSinSum;			
+	reg		signed	[SumWidth-1:0]	adcCosSum;	
+	
+	reg		measWind;
+	wire	measEnd	=	(measCnt==AverageDelay-1)&measWind;
+	
+	reg	gainNewStateR;
+	reg		gainNewState;
+	wire	sensEn	=	((gainNewStateR& (!gainNewState))|(!gainNewStateR&gainNewState));
+	
+	reg		signed	[SumWidth-1:0]	sinShifted;
+	reg		signed	[SumWidth-1:0]	cosShifted;
+	
+	wire	signed	[ThresholdWidth-5:0]		sinShiftedCut	=	sinShifted	[(SumWidth-1)-:20];		//width is 20
+	wire	signed	[ThresholdWidth-5:0]		cosShiftedCut	=	cosShifted	[(SumWidth-1)-:20];		//width is 20
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sinSumSquared	=	(sinShiftedCut*sinShiftedCut);	// width is 40
+	wire	signed	[(ThresholdWidth*2)-9:0]	cosSumSquared	=	(cosShiftedCut*cosShiftedCut);	// width is 40
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sumSquared	=	(cosSumSquared+sinSumSquared);	//width is 40	
+	
+	wire	[(ThresholdWidth*2)-9:0]	lowThresholdCompl	=	{10'b0,GainLowThreshold_i,6'b0};
+	wire	[(ThresholdWidth*2)-9:0]	highThresholdCompl	=	{10'b0,GainHighThreshold_i,6'b0};
+	
+	wire	accWind	=	(measCnt>0	&	measCnt	<=MeasPeriod-2);
+//================================================================================
+//  ASSIGNMENTS
+	assign	GainNewState_o	=	gainNewState;
+	assign	SensEn_o		=	sensEn;
+	assign	MeasStart_o		=	GainAutoEn_i?	measEnd:StartMeas_i;
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(StartMeas_i)	begin
+				measWind	<=	1'b1;
+			end	else	if	(measEnd)	begin
+				measWind	<=	1'b0;
+			end
+		end	else	begin
+			measWind	<=	1'b0;
+		end
+	end	else	begin
+		measWind	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(measWind)	begin
+		if	(measCnt	==	MeasPeriod-2)	begin
+			sinShifted	<=	adcSinSum>>>2;
+			cosShifted	<=	adcCosSum>>>2;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measWind)	begin
+			if	(measCnt	!= AverageDelay-1)	begin
+				measCnt	<=	measCnt	+	3'd1;	
+			end
+		end	else	begin
+			measCnt	<=	3'd0;
+		end
+	end	else	begin
+		measCnt	<=	3'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!accWind)	begin
+			adcSinSum	<=	AdcSin_i;
+			adcCosSum	<=	AdcCos_i;
+		end	else	begin
+			adcSinSum	<=	adcSinSum	+	AdcSin_i;
+			adcCosSum	<=	adcCosSum	+	AdcCos_i;
+		end
+	end	else	begin
+		adcSinSum	<=	0;	
+		adcCosSum	<=	0;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin	
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(measCnt	==	MeasPeriod-1)	begin
+				if	(gainNewState)	begin
+					if	(sumSquared	>	highThresholdCompl)	begin
+						gainNewState	<=	1'b0;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end	else	begin
+					if	(sumSquared	<	lowThresholdCompl)	begin
+						gainNewState	<=	1'b1;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end
+			end
+		end	else	begin
+			gainNewState	<=	1'b0;
+		end
+	end	else	begin
+		gainNewState	<=	1'b0;
+	end
+	
+	gainNewStateR	<=	gainNewState;
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/GainOverloadControl/GainControlWrapper.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+// (* use_dsp48	=	"yes"*)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControlWrapper
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	ThresholdWidth		=	24,
+	parameter	PhIncWidth			=	32,
+	parameter	IfNcoOutWidth		=	18,
+	parameter	MeasPeriod			=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	
+	input	[IfNcoOutWidth-1:0]	NcoSin_i,
+	input	[IfNcoOutWidth-1:0]	NcoCos_i,
+	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	input	GainAutoEn_i,
+	input	GainManualState_i,
+	
+	output	AmpEnNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	MultDataWidth	=	36;
+	
+//================================================================================
+	wire	[MultDataWidth-1:0]	adcSin;
+	wire	[MultDataWidth-1:0]	adcCos;
+
+	wire	[MultDataWidth-1:0]	adcSinCut	=	adcSin	[MultDataWidth-1:0];
+	wire	[MultDataWidth-1:0]	adcCosCut	=	adcCos	[MultDataWidth-1:0];
+	wire	gainNewState;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AmpEnNewState_o	=	(GainAutoEn_i)?	gainNewState:GainManualState_i;
+//================================================================================
+//  CODING
+
+MultModule		
+#(	
+	.AdcDataWidth	(AdcDataWidth),
+	.IfNcoOutWidth	(IfNcoOutWidth)
+)	
+Adc1Mult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.AdcData_i	(AdcData_i),
+	.Sin_i		(NcoSin_i),
+	.Cos_i		(NcoCos_i),
+	.AdcSin_o	(adcSin),
+	.AdcCos_o	(adcCos)
+);
+
+
+GainControl		
+#(	
+	.AdcNcoMultWidth	(MultDataWidth),
+	.ThresholdWidth		(ThresholdWidth),
+	.AdcDataWidth		(AdcDataWidth),
+	.MeasPeriod			(MeasPeriod)
+)
+GainMaster
+(
+	.Rst_i					(Rst_i),
+	.StartMeas_i			(StartMeas_i),
+	.GainAutoEn_i			(GainAutoEn_i),
+	.Clk_i					(Clk_i),
+	.AdcCos_i				(adcSin),
+	.AdcSin_i				(adcCos),
+	.GainLowThreshold_i		(GainLowThreshold_i),
+	.GainHighThreshold_i	(GainHighThreshold_i),
+	.GainNewState_o			(gainNewState),
+	.SensEn_o				(SensEn_o),
+	.MeasStart_o			(MeasStart_o)
+); 
+endmodule

S5443_M/S5443.srcs/sources_1/new/GainOverloadControl/OverloadDetect.v

@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module OverloadDetect
+#(	
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	input	[ThresholdWidth-1:0]	OverThreshold_i,
+	output	Overload_o
+);
+
+//================================================================================
+//  LOG2 FUNCTION
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<MeasPeriod)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+//================================================================================
+//  LOCALPARAMS
+	localparam CntWidth	=	Log2(MeasPeriod);
+	localparam SumWidth	=	AdcDataWidth+CntWidth;
+//================================================================================
+//  REG/WIRE
+	reg		overloadReg;
+	reg		[CntWidth-1:0]	measCnt;		
+	
+	reg		[SumWidth-1:0]	adcSum;	
+	
+	wire	[AdcDataWidth-1:0]	absAdc	=	(AdcData_i[AdcDataWidth-1])?	(~AdcData_i + 1):AdcData_i;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Overload_o	=	overloadReg;
+//================================================================================
+//  CODING
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt	!= MeasPeriod-1)	begin
+			measCnt	<=	measCnt	+	{{{CntWidth-1{1'b0}},1'b1}};	
+		end	else	begin
+			measCnt	<=	{CntWidth{1'b0}};
+		end
+	end	else	begin
+		measCnt	<=	{CntWidth{1'b0}};
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt==MeasPeriod-1)	begin
+			adcSum	<=	absAdc;	
+		end	else	begin
+			adcSum	<=	adcSum	+	absAdc;
+		end
+	end	else	begin
+		adcSum	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(measCnt	==	MeasPeriod-1)	begin
+		if	((adcSum>>CntWidth)	>	OverThreshold_i)	begin
+			overloadReg	<=	1'b1;
+		end	else	begin
+			overloadReg	<=	1'b0;
+		end
+	end
+end
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/AdcCalibration.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//18.01.2022	AdcData_I is 1.0.13 now changing to 1.2.17 for further calculation. The integer part added to avoid the overflow of the corrected data.
+//////////////////////////////////////////////////////////////////////////////////
+
+module AdcCalibration 
+#(	
+	parameter	AccNum			=	128,
+	parameter	AdcDataWidth	=	14
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		CalModeEn_i,
+	input		[AdcDataWidth-1:0]	AdcData_i,
+	
+	output		CalDone_o,
+	output		[AdcDataWidth-1:0]	CalibratedAdcData_o
+);
+
+//================================================================================
+//  Func
+//================================================================================
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+		end
+	endfunction
+	
+	localparam ShiftValue	= Log2(AccNum);
+	localparam AccWidth		= AdcDataWidth+ShiftValue;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg signed	[AccWidth:0]	adcAcc;
+	reg signed	[AdcDataWidth-1:0]	calValue;
+	reg signed	[AdcDataWidth-1:0]	calValueR;
+	reg [ShiftValue-1:0]	accCnt;
+	reg calDone;
+	
+	wire	[AccWidth:0]	adcDataCompl	=	{{ShiftValue+1{AdcData_i[AdcDataWidth-1]}},AdcData_i};
+	
+	wire	signed	[AdcDataWidth-1:0]	calibratedData	=	AdcData_i-calValue;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	CalDone_o	=	calDone;
+	assign	CalibratedAdcData_o	=	calibratedData;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				accCnt	<=	accCnt+1;
+			end	else	begin
+				accCnt	<=	0;
+			end
+		end	else	begin
+			accCnt	<=	0;
+		end
+	end	else	begin
+		accCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(accCnt	==	AccNum-1)	begin
+			calDone	<=	1'b1;
+		end	else	begin
+			calDone	<=	1'b0;
+		end
+	end	else	begin
+		calDone	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				adcAcc	<=	adcAcc+adcDataCompl;
+			end	else	begin
+				adcAcc	<=	adcDataCompl;
+			end
+		end	else	begin
+			adcAcc	<=	adcDataCompl;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(calDone)	begin
+			calValue	<=	adcAcc>>ShiftValue;
+		end	
+	end	else	begin
+		calValue	<=	14'h0;
+	end
+end
+
+endmodule
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/AdcDataGating.v

@@ -0,0 +1,112 @@
+module AdcDataGating
+#(	
+	parameter	AdcDataWidth	=	14
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+	input	GatingPulse_i,
+	
+	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,
+	input	[AdcDataWidth-1:0]	Adc1ChR1Data_i,
+	input	[AdcDataWidth-1:0]	Adc2ChR2Data_i,
+	input	[AdcDataWidth-1:0]	Adc2ChT2Data_i,
+	
+	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
+	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
+);
+
+//================================================================================
+//  CODING
+//================================================================================
+	wire	[AdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	Adc1ChT1Data_i:{AdcDataWidth{1'b0}};
+	wire	[AdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	Adc1ChR1Data_i:{AdcDataWidth{1'b0}};
+	wire	[AdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	Adc2ChR2Data_i:{AdcDataWidth{1'b0}};
+	wire	[AdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	Adc2ChT2Data_i:{AdcDataWidth{1'b0}};
+	
+	reg		[AdcDataWidth-1:0]	dataDelPipeT1	[18:0];
+	reg		[AdcDataWidth-1:0]	dataDelPipeR1	[18:0];
+	reg		[AdcDataWidth-1:0]	dataDelPipeR2	[18:0];
+	reg		[AdcDataWidth-1:0]	dataDelPipeT2	[18:0];
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Adc1ChT1Data_o	=	dataDelPipeT1[18];
+	assign	Adc1ChR1Data_o	=	dataDelPipeR1[18];
+	assign	Adc2ChR2Data_o	=	dataDelPipeR2[18];
+	assign	Adc2ChT2Data_o	=	dataDelPipeT2[18];
+
+//================================================================================
+//  CODING
+//================================================================================
+integer	m;
+
+always	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		dataDelPipeT1[0]  <= adc1ChT1DataGated;
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeT1	[m]<=dataDelPipeT1[m-1];
+		end
+	end	else	begin
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeT1	[m]<=0;
+		end
+	end
+end
+
+always	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		dataDelPipeR1[0]  <= adc1ChR1DataGated;
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeR1	[m]<=dataDelPipeR1[m-1];
+		end
+	end	else	begin
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeR1	[m]<=0;
+		end
+	end
+end
+
+always	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		dataDelPipeR2[0]  <= adc2ChR2DataGated;
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeR2	[m]<=dataDelPipeR2[m-1];
+		end
+	end	else	begin
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeR2	[m]<=0;
+		end
+	end
+end
+
+always	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		dataDelPipeT2[0]  <= adc2ChT2DataGated;
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeT2	[m]<=dataDelPipeT2[m-1];
+		end
+	end	else	begin
+		for(m=1; m<19; m=m+1) begin
+			dataDelPipeT2	[m]<=0;
+		end	
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/ComplPrng.v

@@ -0,0 +1,93 @@
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: NPK TAIR
+// Engineer: Mikhail Zaytsev
+// 
+// Create Date: 21.02.2023
+// Design Name: 
+// Module Name: ComplPrng
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: Pseudorandom number generator (PRNG) based on 
+//				Linear Feedback Shift Register (LFSR). Taus88
+//
+// Dependencies: None
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module ComplPrng
+#(
+	parameter DataPrngWidth = 4,
+	parameter InDataWidth = 14,
+	parameter OutDataWidth = 20
+)
+(
+	input [InDataWidth-1:0] Data_i,
+	input Clk_i,
+	input Rst_i,
+
+	output signed	[OutDataWidth-1:0] DataAndPrng_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [31:0] s1;
+reg [31:0] s2;
+reg [31:0] s3;
+reg signed	[31:0] dataPrng;
+
+wire	signed	[OutDataWidth-1:0]	adcDataExtended;
+
+wire	signed	[DataPrngWidth-1:0]	dataPrngCut;
+// wire	signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+reg		signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+
+reg	signed	[OutDataWidth-1:0]	dataAndPrngReg;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+// assign	adcDataExtended		=	{Data_i[InDataWidth-1], Data_i[InDataWidth-1], Data_i, 4'b0};
+assign	dataPrngCut			=	dataPrng[31-:DataPrngWidth];
+// assign	dataPrngCutExtended	=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+// assign	DataAndPrng_o		=	adcDataExtended+dataPrngCutExtended;
+assign	DataAndPrng_o		=	dataAndPrngReg;
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		s1 <= 32'd12345;
+		s2 <= 32'd12345;
+		s3 <= 32'd12345;
+	end else begin
+		s1 <= (((s1 & 32'd4294967294) << 12) ^ (((s1 << 13) ^ s1) >> 19));
+		s2 <= (((s2 & 32'd4294967288) << 4) ^ (((s2 << 2) ^ s2) >> 25));
+		s3 <= (((s3 & 32'd4294967280) << 17) ^ (((s3 << 3) ^ s3) >> 11));
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrng <= 32'b0;
+	end else begin
+		dataPrng <= s1 ^ s2 ^ s3;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrngCutExtended	<=	0;
+	end else begin
+		dataPrngCutExtended	<=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataAndPrngReg	<=	0;
+	end else begin
+		dataAndPrngReg	<=	Data_i+dataPrngCutExtended;
+	end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/CordicNco.v

@@ -0,0 +1,246 @@
+/*
+    NCO module.
+    The module implements CORDIC algorithm
+*/
+
+module CordicNco 
+#(	parameter                   ODatWidth	= 18,
+	parameter                   PhIncWidth	= 32,
+	parameter                   IterNum		= 10,
+	parameter                   EnSinN		= 0,
+	parameter                   WinTypeW	= 0
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	[PhIncWidth-1:0]	PhaseInc_i,
+	input	[WinTypeW-1:0]	WinType_i,
+	input	WindVal_i,
+	output	[ODatWidth-1:0]	Wind_o,
+	output	[ODatWidth-1:0]	Sin_o,
+	output	[ODatWidth-1:0]	Cos_o,
+    output	reg	Val_o
+);
+
+//================================================================================
+//  FUNCTIONS
+//================================================================================
+    function integer log2;
+        input integer value;
+        begin
+            log2 = 0;
+            while (value > 1) begin
+                value   = value >> 1;
+                log2    = log2 + 1;
+            end
+        end
+    endfunction
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+	localparam  [PhIncWidth-1:0]	angle270	= 3<<(PhIncWidth-2);
+	localparam  [PhIncWidth-1:0]	angle180	= 1<<(PhIncWidth-1);
+	localparam  [PhIncWidth-1:0]	angle90		= 1<<(PhIncWidth-2);
+	
+	localparam [17:0] initValue = 18'd78498;
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+	
+    wire	[PhIncWidth-1:0]	precompAngle[ODatWidth-1:0];   
+    wire	[ODatWidth-1:0]		xPipe[IterNum:0];
+    wire	[ODatWidth-1:0]		yPipe[IterNum:0];
+    wire	[IterNum:0]			valPipe;
+    reg		[PhIncWidth-1:0]	phaseDiffPipe[IterNum-1:0];
+    reg		[2:0]				scwSignPipe[IterNum-1:0];
+
+    reg		[PhIncWidth-1:0]	phaseAcc;
+    reg     [PhIncWidth-1:0]	currPhase;
+    reg		[2:0]				scwSignPrev;
+    reg		[2:0]				scwSign;
+    reg		[2:0]				valSr;
+
+	reg		[ODatWidth-1:0]		sin_o;
+	reg		[ODatWidth-1:0]		cos_o;
+	reg		[ODatWidth-1:0]		wind_o;
+    genvar	g;
+    integer	i;
+	
+	reg		valR;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign	xPipe[0]	=	(Val_i)	?	initValue:xPipe[0];
+    assign	yPipe[0]	=	(Val_i)	?	initValue:yPipe[0];
+    assign	valPipe[0]	=	valSr[2];
+	assign	Wind_o		=	(WindVal_i&&WinType_i==0)	?	wind_o:14'b0;
+
+	assign precompAngle[0] = 32'd536870912;
+	assign precompAngle[1] = 32'd316933406;
+	assign precompAngle[2] = 32'd167458907;
+	assign precompAngle[3] = 32'd85004756;
+	assign precompAngle[4] = 32'd42667331;
+	assign precompAngle[5] = 32'd21354465;
+	assign precompAngle[6] = 32'd10679838;
+	assign precompAngle[7] = 32'd5340245;
+	assign precompAngle[8] = 32'd2670163;
+	assign precompAngle[9] = 32'd1335087;
+	assign precompAngle[10] = 32'd667544;
+	assign precompAngle[11] = 32'd333772;
+	assign precompAngle[12] = 32'd166886;
+	assign precompAngle[13] = 32'd83443;
+	assign precompAngle[14] = 32'd41722;
+	assign precompAngle[15] = 32'd20861;
+	assign precompAngle[16] = 32'd10430;
+	assign precompAngle[17] = 32'd5215;
+	//assign precompAngle[18] = 32'd2608;
+
+	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;
+	assign	Cos_o	=	WindVal_i	?	cos_o	:	14'h0;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valR	<=	1'b0;
+    end else begin
+		valR	<=	Val_i;
+	end
+end
+
+//  Phase handle logic
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        phaseAcc   <= {PhIncWidth{1'b0}};
+    end else if (Val_i) begin
+        phaseAcc   <= phaseAcc + PhaseInc_i;
+    end	else	begin
+		phaseAcc   <= {PhIncWidth{1'b0}};
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        currPhase   <= {PhIncWidth{1'b0}};
+        scwSign         <= 3'b0;
+    end else begin
+        if (phaseAcc > angle270) begin
+            currPhase   <= {PhIncWidth{1'b0}} - phaseAcc;
+            scwSign         <= 3'b010;
+        end else if (phaseAcc > angle180) begin
+            currPhase   <= phaseAcc - angle180;
+            scwSign         <= 3'b011;
+        end else if (phaseAcc > angle90) begin
+            currPhase   <= angle180 - phaseAcc;
+            scwSign         <= 3'b001;
+        end else begin
+            currPhase   <= phaseAcc;
+            scwSign         <= 3'b000;
+        end
+    end
+end
+
+//--------------------------------------------------------------------------------
+//  CORDIC pipe
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valSr <= 3'b0;
+    end else if	(Val_i)	begin
+        valSr <= {valSr[1:0], Val_i};
+    end	else	begin
+		valSr <= 3'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    phaseDiffPipe[0]  <= currPhase - precompAngle[0];
+    scwSignPipe[0]     <= scwSign;
+    for(i=1; i<IterNum; i=i+1) begin
+        scwSignPipe[i] <= scwSignPipe[i-1];
+        if (phaseDiffPipe[i-1][PhIncWidth-1]) begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] + precompAngle[i];
+        end else begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] - precompAngle[i];
+        end
+    end
+end
+
+generate
+    for (g = 0; g < IterNum; g = g + 1) begin : cordic_pipe
+        cordic_rotation #(
+            .ODatWidth	(ODatWidth),
+            .Shift      (g+1)
+        ) cordic_rotation_inst (
+            .Clk_i      (Clk_i),
+            .Rst_i      (Rst_i),
+			.X_i        (xPipe[g]),
+			.Y_i        (yPipe[g]),
+			.Val_i      (valPipe[g]),
+			.Sign_i     (phaseDiffPipe[g][PhIncWidth-1]),
+			.X_o        (xPipe[g+1]),
+			.Y_o        (yPipe[g+1]),
+			.Val_o      (valPipe[g+1])
+		);
+    end
+endgenerate
+
+//--------------------------------------------------------------------------------
+//  Output logic
+
+generate 
+    if (EnSinN) begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+                if (scwSignPrev[1]) begin
+                    sin_o   <=  yPipe[IterNum];
+                end else begin
+                    sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+                end
+            end
+        end
+    end else begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[1]) begin
+					sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					sin_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+		always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                wind_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[2]) begin
+					wind_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					wind_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+    end
+endgenerate
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        cos_o		<= {ODatWidth{1'b0}};
+        scwSignPrev	<= 3'b0;
+        Val_o		<= 1'b0;
+    end else begin
+        if (scwSignPrev[0]) begin
+            cos_o	<= ~xPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+        end else begin
+            cos_o	<= xPipe[IterNum];
+        end
+		scwSignPrev	<= scwSignPipe[IterNum-1];
+		Val_o		<= valPipe[0];
+    end	
+end
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/CordicRotation.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:32:49 05/13/2020 
+// Design Name: 
+// Module Name:    cordic_rotation 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module cordic_rotation 
+#(	parameter   ODatWidth	= 16,
+	parameter   Shift		= 1)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	signed  [ODatWidth-1:0]	X_i,
+	input	signed  [ODatWidth-1:0]	Y_i,
+	input	Val_i,
+	input	Sign_i,
+	output	reg	signed	[ODatWidth-1:0]	X_o,
+	output	reg	signed	[ODatWidth-1:0]	Y_o,
+	output	reg	Val_o
+);
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+    wire    [ODatWidth-1:0]    shiftedInX;
+    wire    [ODatWidth-1:0]    shiftedInY;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign  shiftedInX    =   X_i >>> Shift;
+    assign  shiftedInY    =   Y_i >>> Shift;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        Val_o	<= 1'b0;
+    end else if	(Val_i)	begin
+        Val_o	<= Val_i;
+    end	else	begin
+		Val_o	<=	1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        X_o   <= {ODatWidth{1'b0}};
+        Y_o   <= {ODatWidth{1'b0}};
+    end else if (Val_i) begin
+        if (Sign_i) begin
+            X_o   <= X_i + shiftedInY;
+            Y_o   <= Y_i - shiftedInX; 
+        end else begin
+            X_o   <= X_i - shiftedInY;
+            Y_o   <= Y_i + shiftedInX;
+        end
+    end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/DspPipeline.v

@@ -0,0 +1,285 @@
+
+(* keep_hierarchy = "yes" *)	
+module DspPipeline 
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	AccWidth			=	48,
+	parameter	WindWidth			=	14,
+	parameter	AdcCorrData			=	20,
+	parameter	NcoWidth			=	14,
+	parameter	ResultWidth			=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	IntermediateWidth	=	14,
+	parameter	FracWidth			=	51
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	StartFpConv_i,
+	
+	input	[WindCorrCoefWidth-1:0]	FilterCorrCoef_i,
+	input	[AdcCorrData-1:0]	AdcData_i,
+	input	[WindWidth-1:0]		Wind_i,
+	input	[NcoWidth-1:0]		NcoSin_i,
+	input	[NcoWidth-1:0]		NcoCos_i,
+	input	[WindNormCoefWidth-1:0]	NormCoef_i,
+	
+	output	[ResultWidth-1:0]	CorrResultIm_o,
+	output	[ResultWidth-1:0]	CorrResultRe_o,
+    output	CorrResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	NormResultWidth	=	AccWidth+WindNormCoefWidth;
+	localparam	AdcWindWidth	=	37;
+//================================================================================
+//  REG/WIRE 
+	wire	[AdcWindWidth-1:0]	adcWindResult;
+	wire	adcWindResultVal;
+	
+	wire	[54:0]	adcWindSinResult;
+	wire	adcWindSinResultVal;
+	wire	[54:0]	adcWindCosResult;
+	wire	adcWindCosResultVal;
+	
+	wire	[AccWidth-1:0]	AccResultI;
+	wire	[AccWidth-1:0]	AccResultQ;
+	
+	wire	[ResultWidth-1:0]	NormResultI;
+	wire	NormResultIVal;
+	wire	[ResultWidth-1:0]	NormResultQ;
+	wire	NormResultQVal;
+	
+	wire	[ResultWidth-1:0]	iFp32Result;
+	wire	iFp32ResultVal;
+	wire	[ResultWidth-1:0]	qFp32Result;
+	wire	qFp32ResultVal;
+	
+	wire	CorrResultReVal;
+	wire	CorrResultImVal;
+	
+	reg		valReg;
+	reg		valRegReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	CorrResultVal_o	=	CorrResultReVal&CorrResultImVal;
+	
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			valReg		<=	Val_i;
+			valRegReg	<=	valReg;
+		end	else	begin
+			valReg		<=	0;
+			valRegReg	<=	0;	
+		end
+	end
+	
+//===============================Adc*Wind=========================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcCorrData),
+	.FactorBWidth	(WindWidth),
+	.OutputWidth	(AdcWindWidth)
+)
+AdcWindMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(valRegReg),
+	.FactorA_i	(AdcData_i),
+	.FactorB_i	(Wind_i),
+	.Result_o	(adcWindResult),
+	.ResultVal_o(adcWindResultVal)
+);
+//===============================AdcWind*NcoSinCos================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoSinMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoSin_i),	
+	.Result_o	(adcWindSinResult),
+	.ResultVal_o(adcWindSinResultVal)
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoCosMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoCos_i),
+	.Result_o	(adcWindCosResult),
+	.ResultVal_o(adcWindCosResultVal)
+);
+
+//===============================SumAcc===========================================
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccQ
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+    .Val_i		(adcWindSinResultVal),
+	
+	.Data_i		(adcWindSinResult[53:0]),
+	.Result_o	(AccResultQ)
+);
+
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccI
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+    .Val_i		(adcWindCosResultVal),
+	
+	.Data_i		(adcWindCosResult[53:0]),
+	.Result_o	(AccResultI)
+);
+
+//===============================InToFpConv=======================================
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+QToFp32
+(	
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.InData_i		(AccResultQ),
+	.InDataVal_i	(StartFpConv_i),
+	.OutData_o		(qFp32Result),
+	.OutDataVal_o	(qFp32ResultVal)
+);
+
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+IToFp32
+(	
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.InData_i		(AccResultI),
+	.InDataVal_i	(StartFpConv_i),
+	.OutData_o		(iFp32Result),
+	.OutDataVal_o	(iFp32ResultVal)
+);
+
+//===============================Result*NormCoeff=================================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultQNorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(qFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(qFp32ResultVal),
+	.Result_o		(NormResultQ),
+	.ResultValid_o	(NormResultQVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultINorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(iFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(iFp32ResultVal),
+	.Result_o		(NormResultI),
+	.ResultValid_o	(NormResultIVal)
+);
+
+//===============================NormResult*CorrCoeff========================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultReCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultQ),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultQVal),
+	.Result_o		(CorrResultRe_o),
+	.ResultValid_o	(CorrResultReVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultImCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultI),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultIVal),
+	.Result_o		(CorrResultIm_o),
+	.ResultValid_o	(CorrResultImVal)
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -0,0 +1,396 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    18:00:25 07/10/2019 
+// Design Name: 
+// Module Name:    internal_dsp 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module InternalDsp	
+#(	
+	parameter	AdcDataWidth		=	14,	
+	parameter	WindWidth			=	18,
+	parameter	WindNcoPhIncWidth	=	32,
+	parameter	NcoWidth			=	18,
+	parameter	ChNum				=	4,
+	parameter	ResultWidth			=	32,
+	parameter	WinTypeWidth		=	3,
+	parameter	BandCmdWidth		=	8,
+	parameter	WindPNumWidth		=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	CmdDataRegWith		=	24,
+	parameter	IntermediateWidth	=	18,
+	parameter	CorrAdcDataWidth	=	20,
+	parameter	AccWidth			=	80
+)
+(
+	input	wire	Clk_i,
+	input	wire	WindCalcClk_i,
+	input	wire	Rst_i,
+	input	wire	NcoRst_i,
+	output	wire	OscWind_o,
+	
+	input	wire	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	//A
+	input	wire	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	//R1
+	input	wire	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	//R2
+	input	wire	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	//B	
+	
+	input	wire	GatingPulse_i,
+	
+	input	wire	StartMeas_i,
+	input	wire	StartMeasDsp_i,
+	input	wire	OscDataRdFlag_i,
+	
+	input	wire	[32-1:0]	MeasNum_i,
+	
+	input	wire	[CmdDataRegWith-1:0]	MeasCtrl_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefL_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefH_i,
+	
+	output	wire	EndMeas_o,
+	
+	input	wire	CalModeEn_i,
+	output	wire	CalModeDone_o,
+
+	input	wire	[CmdDataRegWith-1:0]	IfFtwL_i,
+	input	wire	[CmdDataRegWith-1:0]	IfFtwH_i,
+	
+	output	wire	[ResultWidth-1:0]	Adc1ImT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ImR1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReR1Data_o,
+	//adc2                 
+	output	wire	[ResultWidth-1:0]	Adc2ImR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ImT2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReT2Data_o,
+	
+	output	wire	[NcoWidth-1:0]	NcoSin_o,
+	output	wire	[NcoWidth-1:0]	NcoCos_o,
+	
+	output	wire	MeasDataRdy_o,
+	output	wire	MeasWind_o,
+	output	wire	MeasEnd_o
+);
+
+//================================================================================
+//  REG/WIRE
+	wire	[WindNormCoefWidth-1:0]	windNormCoef;
+	wire	[WindPNumWidth-1:0]		windPointsNum;
+	wire	[WindNcoPhIncWidth-1:0]	windPhInc;
+	wire	[WindNcoPhIncWidth-1:0]	winPhIncStart;
+	
+	wire	[WindWidth-1:0]	wind;			
+
+	wire	[NcoWidth-1:0]	ncoCos;
+	wire	[NcoWidth-1:0]	ncoSin;
+	
+	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	// wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
+	wire	[ChNum-1:0]	calDone;
+	
+	genvar g;
+	
+	wire	[ResultWidth-1:0]	resultImBus		[ChNum-1:0];
+	wire	[ResultWidth-1:0]	resultReBus		[ChNum-1:0];
+	wire	[ChNum-1:0]	resultValBus;
+	
+	wire	measWind;
+	wire	measWindDelayed;
+	wire	stopMeas;
+	wire	[1:0]	tukeyCtrl;
+	
+	reg		[CmdDataRegWith-1:0]	measCtrlReg;
+	reg		[32-1:0]	windPointsNumReg;
+	reg		[32-1:0]	measNumReg;
+	reg		[WindCorrCoefWidth-1:0]	filterCorrCoeffReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwLReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwHReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefLReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefHReg;
+	
+	wire	[31:0]	windArg;
+	
+	// wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	
+	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	
+	wire	[WindNcoPhIncWidth-1:0]	ncoPhInc = {ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg};
+//================================================================================
+//  ASSIGNMENTS
+	
+	// assign	adcDataBus	[ChNum-1]	=	Adc2ChT2Data_i;
+	// assign	adcDataBus	[ChNum-2]	=	Adc2ChR2Data_i;
+	// assign	adcDataBus	[ChNum-3]	=	Adc1ChR1Data_i;
+	// assign	adcDataBus	[ChNum-4]	=	Adc1ChT1Data_i;
+
+	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	
+	
+	assign	gatedAdcDataBus	[ChNum-1]	=	adc2ChT2DataGated;
+	assign	gatedAdcDataBus	[ChNum-2]	=	adc2ChR2DataGated;
+	assign	gatedAdcDataBus	[ChNum-3]	=	adc1ChR1DataGated;
+	assign	gatedAdcDataBus	[ChNum-4]	=	adc1ChT1DataGated;
+	
+	assign	Adc1ImT1Data_o	=	resultImBus	[ChNum-4];
+	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
+	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
+	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
+	//adc2                 
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	
+	
+	assign	MeasDataRdy_o	=	&resultValBus;
+	assign	EndMeas_o		=	stopMeas;
+	
+	assign	NcoCos_o	=	ncoCos;
+	assign	NcoSin_o	=	ncoSin;
+	assign	MeasWind_o	=	measWind;
+	
+	assign	CalModeDone_o	=	&calDone;
+//================================================================================
+//  INSTANTIATIONS
+
+//----------------------------------------------
+//Module generates event signals for measurement
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!StartMeas_i)	begin
+			measCtrlReg			<=	MeasCtrl_i;
+			ifFtwLReg			<=	IfFtwL_i;
+			ifFtwHReg			<=	IfFtwH_i;
+			filterCorrCoefLReg	<=	FilterCorrCoefL_i;
+			filterCorrCoefHReg	<=	FilterCorrCoefH_i;
+			measNumReg			<=	MeasNum_i;
+			windPointsNumReg	<=	windPointsNum;
+		end 
+	end	else	begin
+		measCtrlReg			<=	0;
+		ifFtwLReg			<=	0;
+		ifFtwHReg			<=	0;
+		filterCorrCoefLReg	<=	0;
+		filterCorrCoefHReg	<=	0;
+		measNumReg			<=	0;
+		windPointsNumReg	<=	0;
+	end 
+end
+
+// PseudoRandomGenerator	RandomGenInst
+// (
+	// .Rst_i	(Rst_i),
+	// .Clk_i	(Clk_i),
+	// .Data_o	()
+// );
+
+MeasCtrlModule	
+#(	
+	.WindPNumWidth	(WindPNumWidth)
+)
+MeasCtrlModule	
+(
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.OscWind_o			(OscWind_o),
+	.FilterCmd_i		(measCtrlReg[15-:8]),
+	
+	.MeasNum_i			(measNumReg),
+	.StartMeas_i		(StartMeas_i),
+	.StartMeasDsp_i		(StartMeasDsp_i),
+	.Mode_i				(measCtrlReg[0]),
+	.OscDataRdFlag_i	(OscDataRdFlag_i),
+	
+	.WindPointsNum_i	(windPointsNumReg),
+	
+	.WindPhInc_i		(windPhInc),
+	.WindPhIncStart_i	(winPhIncStart),
+	.WindArg_o			(windArg),
+	
+	.StartFpConv_o		(StartFpConv),
+	.MeasWind_o			(measWind),
+	.MeasWindDel_o		(measWindDelayed),
+	.StopMeas_o			(stopMeas),
+	.MeasEnd_o			(MeasEnd_o),
+	.WinCtrl_o			(winCtrl),
+	.TukeyCtrl_o		(tukeyCtrl)
+);	
+
+//----------------------------------------------
+//Module selects settings for current window
+WinParameters 
+#(	
+	.WindPhIncWidth		(WindNcoPhIncWidth),
+	.WindNormCoefWidth	(WindNormCoefWidth),
+	.WindPNumWidth		(WindPNumWidth),
+	.BandCmdWidth		(BandCmdWidth)
+)
+WinParameters
+(	
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.FilterCmd_i	(measCtrlReg[15-:8]),
+	.WinPhInc_o		(windPhInc),
+	.WinPhIncStart_o(winPhIncStart),
+	.WinNormCoef_o	(windNormCoef),
+	.WinPointsNum_o	(windPointsNum)
+);
+
+//----------------------------------------------
+//Module generates win samples
+Win_calc	WinCalcInst
+(
+	.clk_i			(Clk_i),
+	.wind_clk		(WindCalcClk_i),
+	.filterCmd_i	(measCtrlReg[15-:8]),
+	.reset_i		(Rst_i),
+	.WinCtrl_i		(winCtrl),
+	.TukeyCtrl_i	(tukeyCtrl),
+	.MeasWind_i		(measWind),
+	.win_value_i	(windArg),
+	.win_type_i		(measCtrlReg[2:0]),
+	.win_o			(wind),
+	.sinWin_o		(sinwind)
+);
+
+
+//----------------------------------------------
+//Module generates Sin and Cos for measurement
+
+CordicNco		
+#(	
+	.ODatWidth	(NcoWidth),
+	.PhIncWidth	(WindNcoPhIncWidth),
+	.IterNum	(15),
+	.EnSinN		(1)
+)
+ncoInst
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i|NcoRst_i),
+	.Val_i		(1'b1),
+	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin),
+	.Cos_o		(ncoCos),
+	.Val_o		()
+);
+
+//------------------------------------------------
+//Generating needed amount of calculating channels
+generate
+	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
+	
+		AdcCalibration 
+		#(	
+			// .AccNum			(32),
+			.AccNum			(2097152),
+			.AdcDataWidth	(CorrAdcDataWidth)
+		)
+		AdcCalibrationInst
+		(	
+			.Clk_i					(Clk_i),
+			.Rst_i					(Rst_i),
+			.CalModeEn_i			(CalModeEn_i),
+			// .AdcData_i				(adcDataBusExt[g]),
+			.AdcData_i				(adcDataBus[g]),
+			
+			.CalDone_o				(calDone[g]),
+			.CalibratedAdcData_o	(calAdcData[g])
+		);
+
+		ComplPrng
+		#(
+			.DataPrngWidth	(8),
+			.InDataWidth 	(CorrAdcDataWidth),
+			.OutDataWidth	(CorrAdcDataWidth)
+		)
+		ComplPrngAdderInst
+		(
+			.Data_i	(calAdcData[g]),
+			.Clk_i	(Clk_i),
+			.Rst_i	(Rst_i),
+
+			.DataAndPrng_o	(adcDataBusExt[g])
+		);
+		
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspPipelineInst
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.StartFpConv_i		(StartFpConv),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			.Wind_i				(wind),
+			.NcoSin_i			(ncoCos),
+			.NcoCos_i			(ncoSin),	
+			.NormCoef_i			(windNormCoef),
+
+			.CorrResultIm_o		(resultImBus[g]),
+			.CorrResultRe_o		(resultReBus[g]),
+			.CorrResultVal_o	(resultValBus[g])
+		);
+	end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/MeasCtrlModule.v

@@ -0,0 +1,333 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:22:41 09/18/2019 
+// Design Name: 
+// Module Name:    MeasCtrlModule 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module MeasCtrlModule
+#(	
+	parameter	WindPNumWidth	=	48,
+	localparam	TukeyWinAlpha	=	4
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+	output	OscWind_o,
+	
+	input	StartMeas_i,
+	input	StartMeasDsp_i,
+	input	[7:0]	FilterCmd_i,
+	input	Mode_i,
+	input	OscDataRdFlag_i,
+	
+	input	[32-1:0]	MeasNum_i,
+
+	input	[WindPNumWidth-1:0]	WindPointsNum_i,
+	
+	input	[32-1:0]	WindPhInc_i,
+	input	[32-1:0]	WindPhIncStart_i,
+	output	[32-1:0]	WindArg_o,
+	
+	output	StartFpConv_o,
+	output	MeasWind_o,
+	output	MeasWindDel_o,
+	output	StopMeas_o,
+	output	MeasEnd_o,
+	output	WinCtrl_o,
+	output	[1:0]	TukeyCtrl_o
+);
+
+
+//================================================================================
+//  REG/WIRE
+	reg	startFpConv;
+
+	reg	[1:0]	startFpConvPipe	[3:0];
+	integer i;
+
+	reg		measWind;
+	reg		measWindR;
+	
+	reg		startMeasReg;										
+	reg		startMeasDspReg;										
+	wire	startMeasCmd	=	(StartMeas_i		&	!startMeasReg);	//esli prihodit bol'she chem 1 sigtal zapuska na 1 izmerenie, to ostal'nie ignoriruutsya
+	wire	stopMeasCmd		=	(!StartMeasDsp_i	&	startMeasDspReg);
+	wire	startMeasDspPos	=	(StartMeasDsp_i		&	!startMeasDspReg);
+	
+	reg		[31:0]	measCnt;
+	
+	reg		[WindPNumWidth-1:0]	pNumCnt;
+
+	reg		measWindEnd;
+	reg		pMeasEnd;
+	wire	pNumCntRes		=	!measWind;
+	wire	measCntRes		=	pMeasEnd|!StartMeasDsp_i;
+	
+	wire	stopCalc		=	(stopMeasCmd|measWindEnd);
+
+	reg		[32-1:0]	windArg;
+	
+	wire	oscMode	=	(Mode_i	==	1'b1);
+	
+	reg		oscWind;
+	
+	wire	[31:0]	tukeyCosPNum = WindPointsNum_i/TukeyWinAlpha;
+	
+	wire	[31:0]	tukeyCosPNumDiv2			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValues			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValuesDiv2		=	tukeyFirstCosValues/2;
+	wire	[31:0]	tukeySecondCosValuesDiv2	=	(WindPointsNum_i-tukeyFirstCosValuesDiv2);
+	wire	[31:0]	tukeySecondCosValues		=	(WindPointsNum_i-tukeyCosPNum/2);
+
+	reg		[1:0]	tukeyCtrl;
+	reg		[1:0]	tukeyCtrlR;
+	reg		[1:0]	tukeyCtrlRR;
+
+	
+	wire	incPhase	=	(pNumCnt	<=	tukeyFirstCosValues);
+	wire	decrPhase	=	(pNumCnt	>=	tukeySecondCosValues-1	&	pNumCnt	<=	WindPointsNum_i-1);
+	
+	wire	wideFilterFlag	=	(FilterCmd_i>=8'h54	&	FilterCmd_i!=8'h70);
+
+//================================================================================
+//  ASSIGNMENTS
+	assign	StartFpConv_o		=	startFpConvPipe	[2];
+	assign	MeasWind_o			=	measWind;
+	assign	MeasWindDel_o		=	measWindR;
+	assign	StopMeas_o			=	pMeasEnd;
+	assign	MeasEnd_o			=	stopMeasCmd;
+	assign	WindArg_o			=	windArg;
+	assign	OscWind_o			=	oscWind;
+	assign	TukeyCtrl_o			=	tukeyCtrl;
+	assign	WinCtrl_o			=	(pNumCnt<=tukeyFirstCosValuesDiv2+1|pNumCnt>tukeySecondCosValuesDiv2);
+//================================================================================
+//  CODING
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(measWind)	begin
+				if	(pNumCnt	!=	0)	begin
+					if	(pNumCnt	<=	tukeyFirstCosValues-1	|	pNumCnt	>	tukeySecondCosValues)	begin
+						tukeyCtrl	=	2'd2;
+					end	else	begin
+						tukeyCtrl	=	2'd1;
+					end
+				end	else	begin
+					tukeyCtrl	=	2'd0;
+				end
+			end	else	begin
+				tukeyCtrl	=	2'd0;
+			end
+		end	else	begin
+			tukeyCtrl	=	2'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measWindR	<=	measWind;
+		end	else	begin
+			measWindR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			tukeyCtrlR	<=	tukeyCtrl;
+			tukeyCtrlRR	<=	tukeyCtrlR;
+		end	else	begin
+			tukeyCtrlR	<=	1'b0;
+			tukeyCtrlRR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(measWindR)	begin
+				if	(pNumCnt	==	WindPointsNum_i-1)	begin
+					measWindEnd	<=	1'b1;
+				end	else	begin
+					measWindEnd	<=	1'b0;
+				end
+			end	else	begin
+				measWindEnd	<=	1'b0;
+			end
+		end	else	begin
+			measWindEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!oscMode)	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(measWindEnd)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end	else	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(OscDataRdFlag_i)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end
+		end	else	begin
+			pMeasEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(wideFilterFlag)	begin
+				if	(measWind)	begin
+					windArg	<=	windArg+WindPhInc_i;
+				end	else	begin
+					windArg	<=	WindPhInc_i>>1;
+				end
+			end	else	begin
+				if	(measWind)	begin
+					if	(incPhase)	begin
+						windArg	<=	windArg+WindPhInc_i;
+					end	
+					if	(decrPhase)	begin
+						windArg	<=	windArg-WindPhInc_i;
+					end
+				end	else	begin
+					windArg	<=	WindPhIncStart_i;
+				end
+			end
+		end	else	begin
+			windArg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!measCntRes)	begin
+				if	(!oscMode)	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(measWindEnd)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end	else	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(OscDataRdFlag_i)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end
+			end	else	begin
+				measCnt	<=	0;
+			end
+		end	else	begin
+			measCnt	<=	0;
+		end	
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscMode)	begin
+				if	(startMeasDspPos)	begin
+					oscWind	<=	1'b1;
+				end	
+				if	(pMeasEnd)	begin
+					oscWind	<=	1'b0;
+				end
+			end	else	begin
+				oscWind	<=	1'b0;
+			end
+		end	else	begin
+			oscWind	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i) begin
+		if	(!Rst_i)	begin
+			if	(measWindEnd)	begin
+				startFpConv	<=	1'b1;
+			end	else	begin
+				startFpConv	<=	1'b0;
+			end
+		end	else	begin
+			startFpConv	<=	1'b0;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		startFpConvPipe[0]  <= startFpConv;
+		for(i=1; i<4; i=i+1) begin
+			startFpConvPipe	[i]<=startFpConvPipe[i-1];
+		end
+	end
+	
+	always 	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(pNumCntRes)	begin
+				pNumCnt	<=	{WindPNumWidth{1'b0}};
+			end	else	begin
+				pNumCnt	<=	pNumCnt	+	{{WindPNumWidth-1{1'b0}},1'b1};
+			end
+		end	else	begin
+			pNumCnt	<=	{WindPNumWidth{1'b0}};
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasReg	<=	StartMeas_i;
+		end	else	begin
+			startMeasReg	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasDspReg	<=	StartMeasDsp_i;
+		end	else	begin
+			startMeasDspReg	<=	1'b0;
+		end
+	end
+	
+	always	@(*)	begin	
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(!measWind)	begin
+					if	(startMeasCmd)	begin
+						measWind	=	1'b1;
+					end	
+				end	else	if	(stopCalc)	begin	
+					measWind	=	1'b0;
+				end
+			end	else	begin
+				measWind	=	1'b0;
+			end
+		end	else	begin
+			measWind	<=	1'b0;
+		end
+	end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/NcoRstGen.v

@@ -0,0 +1,115 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module NcoRstGen	
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	[31:0]	NcoPhInc_i,
+	input	StartMeasEvent_i,
+	
+	output	NcoRst_o,
+	output	StartMeasEvent_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[15:0]	startMeasEventReg;
+	reg	[31:0]	ncoPhIncReg;
+	reg	[31:0]	ncoPhIncRegR;
+	
+	wire	ncoPhIncUpdateFlag	=	(ncoPhIncRegR!=ncoPhIncReg);
+	wire	delFlag	=	(startMeasEventReg[15]);
+	
+	reg	[1:0]	currState;
+	
+	reg	rst;
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	parameter	[1:0]	IDLE	=	2'd0;
+	parameter	[1:0]	RST		=	2'd1;
+	parameter	[1:0]	DEL		=	2'd2;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	assign	NcoRst_o	=	rst;
+	assign	StartMeasEvent_o	=	(currState	==	IDLE)?	StartMeasEvent_i:startMeasEventReg[15];
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			ncoPhIncReg		<=	NcoPhInc_i;
+			ncoPhIncRegR	<=	ncoPhIncReg;
+		end	else	begin
+			ncoPhIncReg		<=	0;
+			ncoPhIncRegR	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasEventReg	<=	{startMeasEventReg[15:0],StartMeasEvent_i};
+		end	else	begin
+			startMeasEventReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			case(currState)
+			IDLE	:	begin
+							if (ncoPhIncUpdateFlag)	begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end	else begin
+								currState	<= IDLE;
+								rst	<=	1'b0;
+							end
+						end
+						
+			RST		:	begin
+							if	(rst	&	StartMeasEvent_i)	begin
+								currState	<= DEL;
+								rst	<=	1'b0;
+							end	else begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end
+						end
+		
+			DEL		:	begin
+							if	(delFlag)	begin
+								currState  <= IDLE;
+								rst	<=	1'b0;
+							end	else begin
+								currState  <= DEL;
+								rst	<=	1'b0;
+							end
+						end
+			endcase
+		end	else	begin
+			currState	<=	2'd0;
+		end
+	end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Tb/InternalDspTb.v

@@ -0,0 +1,151 @@
+`timescale 1ns / 1ps
+module InternalDspTb;
+
+	parameter	AdcDataWidth	=	14;
+	parameter	ChNum			=	4;
+	parameter	ResultWidth		=	32;
+	parameter	CmdDataRegWith	=	24;
+	
+	reg	rst;
+	reg	clk_50;
+
+	reg	[31:0]	tb_cnt;
+	
+	reg	StartCalcCmdReg	;
+								
+	wire	[AdcDataWidth-1:0]	adcData;				
+	wire	measDataRdy;			
+
+	reg	startMeas;
+	reg	[CmdDataRegWith-1:0]	measCtrl;
+	reg	calModeEn;
+	reg	[8-1:0]	ifFtw0;
+	reg	[CmdDataRegWith-1:0]	ifFtw1;
+//==========================================================================================
+//clocks gen
+	always	#10 clk_50	=	~clk_50;
+//==========================================================================================
+	initial begin
+		clk_50	=	1'b1;
+		rst		=	1'b1;
+	#10;
+		rst		=	1'b0;
+	end		
+
+	always	@(posedge	clk_50)	begin
+		if	(!rst)		begin
+			tb_cnt	<=	tb_cnt+1;
+		end	else	begin
+			tb_cnt	<=	0;
+		end
+	end
+
+	always	@(posedge	clk_50)	begin
+		if	(tb_cnt	== 10)	begin
+			measCtrl	<=	{8'h0,8'h55,8'b0};
+			calModeEn	<=	1'b0;
+			ifFtw0		<=	8'h89;
+			ifFtw1		<=	24'h256041;
+		end
+	end
+	
+	always	@(posedge	clk_50)	begin
+		if	(rst)	begin
+			startMeas	<=	1'b0;
+		end	else	begin
+			if	(tb_cnt	== 20)	begin
+				startMeas	<=	1'b1;
+			end	else	if	(measDataRdy)	begin
+				startMeas	<=	1'b0;
+			end
+		end
+	end
+	
+CordicNco		
+#(	.ODatWidth	(14),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(clk_50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(32'h25604189),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(adcData),
+	.Cos_o				(),
+	.Val_o				()
+);
+
+InternalDsp	
+#(	
+	.AdcDataWidth		(AdcDataWidth),
+	.ChNum				(ChNum),
+	.ResultWidth		(ResultWidth),
+	.CmdDataRegWith		(CmdDataRegWith)
+)
+InternalDsp
+(
+	.Clk_i				(clk_50),
+	.Rst_i				(rst),
+	
+	.adc1ChAData_i		(adcData),	//A
+	.adc1ChR1Data_i		(adcData),	//R1
+	.adc2ChR2Data_i		(adcData),	//R2
+	.adc2ChBData_i		(adcData),	//B
+	
+	.StartMeas_i		(startMeas),	
+	
+	.MeasCtrl_i			(measCtrl),
+	
+	.CalModeEn_i		(calModeEn),
+
+	.IfFtw_i			({ifFtw1,ifFtw0}),
+	
+	.Adc1ImAData_o		(),
+	.Adc1ReAData_o		(),
+	.Adc1ImR1Data_o		(),
+	.Adc1ReR1Data_o		(),
+	
+	.Adc2ImR2Data_o		(),
+	.Adc2ReR2Data_o		(),
+	.Adc2ImBData_o		(),
+	.Adc2ReBData_o		(),
+	
+	.MeasDataRdy_o		(measDataRdy)
+); 
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/WinParameters.v

@@ -0,0 +1,315 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module WinParameters 
+#(	
+	parameter	WindPhIncWidth		=	48,
+	parameter	WindNormCoefWidth	=	14,
+	parameter	WindPNumWidth		=	32,
+	parameter	BandCmdWidth		=	16
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		[BandCmdWidth-1:0]		FilterCmd_i,
+	output		[WindPhIncWidth-1:0]	WinPhInc_o,
+	output		[WindPhIncWidth-1:0]	WinPhIncStart_o,
+	output		[WindNormCoefWidth-1:0]	WinNormCoef_o,
+	output		[WindPNumWidth-1:0]		WinPointsNum_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg [WindPhIncWidth-1:0]	windPhInc;
+	reg	[WindNormCoefWidth-1:0]	winNormCoef;
+	reg	[WindPNumWidth-1:0]		winPointsNum;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	WinPhInc_o 		=	windPhInc;
+	assign	WinPhIncStart_o =	32'h80000000;
+	assign	WinNormCoef_o	=	winNormCoef;
+	assign	WinPointsNum_o	=	winPointsNum;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@	(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case (FilterCmd_i)			
+			8'h0 : begin	//	1	Hz
+						windPhInc		<=	32'h2a8;
+						winNormCoef		<=	32'h3342b45d;
+						winPointsNum	<=	32'h30291a0;
+					end
+			8'h1 : begin//	1.5	Hz
+						windPhInc		<=	32'h3fc;
+						winNormCoef		<=	32'h3391cf5e;
+						winPointsNum	<=	32'h201b66a;
+					end
+			8'h2 : begin//	2	Hz
+						windPhInc		<=	32'h550;
+						winNormCoef		<=	32'h33c269d2;
+						winPointsNum	<=	32'h18148d0;
+					 end
+			8'h3 : begin//	3	Hz
+						windPhInc		<=	32'h7f9;
+						winNormCoef		<=	32'h3411ccc1;
+						winPointsNum	<=	32'h100db35;
+					end
+			8'h4 : begin//	5	Hz
+						windPhInc		<=	32'hd49;
+						winNormCoef		<=	32'h347301aa;
+						winPointsNum	<=	32'h9a1d20;
+					end
+			8'h5 : begin//	7	Hz
+						windPhInc		<=	32'h129a;
+						winNormCoef		<=	32'h34aa19fd;
+						winPointsNum	<=	32'h6e14cd;
+					end
+			8'h10 : begin//	10	Hz
+						windPhInc		<=	32'h1a93;
+						winNormCoef		<=	32'h34f3005d;
+						winPointsNum	<=	32'h4d0e90;
+					end
+			8'h11 : begin//	15	Hz
+						windPhInc		<=	32'h27dd;
+						winNormCoef		<=	32'h35363ff7;
+						winPointsNum	<=	32'h335f0a;
+					end
+			8'h12 : begin//	20	Hz
+						windPhInc		<=	32'h3527;
+						winNormCoef		<=	32'h3572ffba;
+						winPointsNum	<=	32'h268748;
+					end
+			8'h13 : begin//	30	Hz
+						windPhInc		<=	32'h4fbb;
+						winNormCoef		<=	32'h35b63fa7;
+						winPointsNum	<=	32'h19af85;
+					end
+			8'h14 : begin//	50	Hz
+						windPhInc		<=	32'h84e3;
+						winNormCoef		<=	32'h3617df9c;
+						winPointsNum	<=	32'hf6950;
+					end
+			8'h15 : begin//	70	Hz
+						windPhInc		<=	32'hba0b;
+						winNormCoef		<=	32'h36549f77;
+						winPointsNum	<=	32'hb0214;
+					end
+			8'h20 : begin//	100	Hz
+						windPhInc		<=	32'h109c7;
+						winNormCoef		<=	32'h3697df93;
+						winPointsNum	<=	32'h7b4a8;
+					end
+			8'h21 : begin//	150	Hz
+						windPhInc		<=	32'h18eab;
+						winNormCoef		<=	32'h36e3cf84;
+						winPointsNum	<=	32'h5231a;
+					end
+			8'h22 : begin//	200	Hz
+						windPhInc		<=	32'h21390;
+						winNormCoef		<=	32'h3717df94;
+						winPointsNum	<=	32'h3da54;
+					end
+			8'h23 : begin//	300	Hz 
+						windPhInc		<=	32'h31d5b;
+						winNormCoef		<=	32'h3763cf83;
+						winPointsNum	<=	32'h2918d;
+					end
+			8'h24 : begin//	500	Hz
+						windPhInc		<=	32'h530e3;
+						winNormCoef		<=	32'h37bdd7e8;
+						winPointsNum	<=	32'h18a88;
+					end
+			8'h25 : begin//	700	Hz
+						windPhInc		<=	32'h7449e;
+						winNormCoef		<=	32'h3804e417;
+						winPointsNum	<=	32'h119ce;
+					end
+			8'h30 : begin//	1	kHz
+						windPhInc		<=	32'ha61fc;
+						winNormCoef		<=	32'h383dd7e8;
+						winPointsNum	<=	32'hc544;
+					end
+			8'h31 : begin//	1.5	kHz
+						windPhInc		<=	32'hf92fb;
+						winNormCoef		<=	32'h388e6329;
+						winPointsNum	<=	32'h8382;
+					end
+			8'h32 : begin//	2	kHz
+						windPhInc		<=	32'h14c3f9;
+						winNormCoef		<=	32'h38bdd900;
+						winPointsNum	<=	32'h62a2;
+					end
+			8'h33 : begin//	3	kHz
+						windPhInc		<=	32'h1f25f6;
+						winNormCoef		<=	32'h390e6466;
+						winPointsNum	<=	32'h41c1;
+					end
+			8'h34 : begin//	5	kHz
+						windPhInc		<=	32'h33ee26;
+						winNormCoef		<=	32'h396d509f;
+						winPointsNum	<=	32'h2774;
+					end
+			8'h35 : begin//	7	kHz
+						windPhInc		<=	32'h48bca9;
+						winNormCoef		<=	32'h39a61fcc;
+						winPointsNum	<=	32'h1c2e;
+					end
+			8'h40 : begin//	10	kHz
+						windPhInc		<=	32'h67dc4c;
+						winNormCoef		<=	32'h39ed577f;
+						winPointsNum	<=	32'h13ba;
+					end
+			8'h41 : begin//	15	kHz
+						windPhInc		<=	32'h9c09c0;
+						winNormCoef		<=	32'h3a3206c8;
+						winPointsNum	<=	32'hd26;
+					end
+			8'h42 : begin//	20	kHz
+						windPhInc 		<=	32'hd00d00;
+						winNormCoef		<=	32'h3a6d577f;
+						winPointsNum	<=	32'h9dd;
+					end
+			8'h43 : begin//	30	kHz
+						windPhInc		<=	32'h1381381;
+						winNormCoef		<=	32'h3ab1e1ce;
+						winPointsNum	<=	32'h693;
+					end
+			8'h44 : begin//	50	kHz
+						windPhInc		<=	32'h2082082;
+						winNormCoef		<=	32'h3b1444c4;
+						winPointsNum	<=	32'h3f2;
+					end
+			8'h45 : begin//	70	KHz
+						windPhInc		<=	32'h2d82d82;
+						winNormCoef		<=	32'h3b4fb73a;
+						winPointsNum	<=	32'h2d1;
+					end
+			8'h50 : begin//	100	KHz
+						windPhInc		<=	32'h4104104;
+						winNormCoef		<=	32'h3b944cd1;
+						winPointsNum	<=	32'h1f9;
+					end
+			8'h51 : begin//	150	KHz
+						windPhInc 		<=	32'h6186186;
+						winNormCoef		<=	32'h3bdeed44;
+						winPointsNum	<=	32'h150;
+					end
+			8'h52 : begin//	200	KHz
+						windPhInc		<=	32'h8421084;
+						winNormCoef		<=	32'h3c1442d8;
+						winPointsNum	<=	32'hfc;
+					end
+			8'h53 : begin//	300	KHz
+						windPhInc 		<=	32'hc30c30c;
+						winNormCoef		<=	32'h3c5ed0fd;
+						winPointsNum	<=	32'ha8;
+					end
+			8'h54 : begin//	500	KHz
+						windPhInc 		<=	32'h1c71c71;
+						winNormCoef		<=	32'h3ce38e38;
+						winPointsNum	<=	32'h90;
+					end
+			8'h55 : begin//	700	KHz
+						windPhInc		<=	32'h2828282;
+						winNormCoef		<=	32'h3d20a0a0;
+						winPointsNum	<=	32'h66;
+					end
+			8'h60 : begin//	1	MHz
+						windPhInc 		<=	32'h38e38e3;
+						winNormCoef		<=	32'h3d638e39;
+						winPointsNum	<=	32'h48;
+					end
+			8'h61 : begin//	1.5	MHz
+						windPhInc 		<=	32'h5555555;
+						winNormCoef		<=	32'h3daaaaab;
+						winPointsNum	<=	32'h30;
+					end
+			8'h62 : begin//	2	MHz
+						windPhInc 		<=	32'h71c71c7;
+						winNormCoef		<=	32'h3de38e39;
+						winPointsNum	<=	32'h24;
+					end	
+			8'h63 : begin
+						windPhInc 		<=	32'h0;
+						winNormCoef		<=	32'h3e124925;
+						winPointsNum	<=	32'he;
+					end	
+			// 8'h64 : begin//	5	MHz
+						// windPhInc 		<=	32'h12492492;
+						// winNormCoef		<=	32'h3e924925;
+						// winPointsNum	<=	32'he;
+					// end	
+			// 8'h64 : begin//	2,46	MHz
+						// windPhInc 		<=	32'h9d89d89;
+						// winNormCoef		<=	32'h3df76c57;
+						// winPointsNum	<=	32'h1a;
+					// end	
+			// 8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						// windPhInc 		<=	32'h1FFFFFFF;
+						// winNormCoef		<=	32'h6D13892;
+						// winPointsNum	<=	32'h10000;
+					// end	
+			// 8'h71 : begin
+						// 7.5MHZ
+						// windPhInc 		<=	32'h1c71c71c;
+						// winNormCoef		<=	32'h3ee38e39;
+						// winPointsNum	<=	32'h9;
+					// end	
+			// 8'h72 : begin
+						// 10MHZ
+						// windPhInc 		<=	32'h24924924;
+						// winNormCoef		<=	32'h3f124925;
+						// winPointsNum	<=	32'h7;
+					// end	
+			8'h64 : begin
+						windPhInc 		<=	32'h0;
+						winNormCoef		<=	32'h3e800000;
+						winPointsNum	<=	32'h8;
+					end	
+			8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						windPhInc 		<=	32'h1FFFFFFF;
+						winNormCoef		<=	32'h6D13892;
+						winPointsNum	<=	32'h10000;
+					end	
+			8'h71 : begin							
+						windPhInc 		<=	32'h0;
+						winNormCoef		<=	32'h3eaaaaab;
+						winPointsNum	<=	32'h6;
+					end	
+			8'h72 : begin	
+						windPhInc 		<=	32'h0;
+						winNormCoef		<=	32'h3f000000;
+						winPointsNum	<=	32'h4;
+					end
+					
+			default: begin	
+						windPhInc 		<=	32'h15555555;
+						winNormCoef		<=	32'h3e86cfea;
+						winPointsNum	<=	32'hc;
+					 end					 
+		endcase
+	end	
+end
+endmodule
+

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -0,0 +1,402 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Win_calc	(
+	input			clk_i,
+	input			wind_clk,
+	input	[7:0]	filterCmd_i,
+	input			reset_i,
+	input			WinCtrl_i,
+	input			MeasWind_i,
+	input	[1:0]	TukeyCtrl_i,
+	input	[31:0]	win_value_i,
+	input	[2:0]	win_type_i,	
+	output	signed [17:0]	win_o,
+	output	reg	signed [17:0]	sinWin_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	reg			[2:0]	calc_cycle;
+	reg	signed	[17:0]	a1;		
+	reg signed	[17:0]	b; 	
+	reg signed	[17:0]	c1;
+	reg signed	[17:0]	c2;	
+	wire 		[47:0]	p2;
+	wire 		[47:0]	p1;	
+	
+	reg			signed	[17:0]	sinWind;
+	reg			signed	[17:0]	tukeyWind;	
+		
+	reg	[1:0]	tukeyCtrlR;
+	reg	[1:0]	tukeyCtrlRR;
+	
+	reg	[35:0]	sinWindPow2;
+	
+	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
+	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
+	
+	wire	[17:0]	bSin	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	wire	[17:0]	bTukey	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	
+	wire	[17:0]	bCurr	=	sinFilterFlag	?	bSin:bTukey;
+	
+	wire	signed	[17:0]	constOne	=	18'b011111111111111111;
+	
+	reg		signed	[18:0]	tukeyCorr;
+	
+	reg		[17:0]	tukeyWindOut;
+	
+	wire	signed [17:0]	windMux1;
+	wire	signed [17:0]	windMux2;
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	localparam	signed	A3_1	=	18'h15584;
+// ????????? ??? ?????????? SIN
+	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
+	localparam signed	[17:0]	A2	=	18'h002C0;			// b
+	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
+	localparam signed	[17:0]	A4	=	18'h0126C;			// d
+	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
+	
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+
+	// assign	win_o	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
+	
+	assign	win_o		=	windMux2;
+	
+	assign	windMux1	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
+	assign	windMux2	=	(rectFilterFlag)?	18'h1ffff:windMux1;
+
+// ================================================================================
+//  CODING
+//================================================================================	
+
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		tukeyCtrlR	<=	TukeyCtrl_i;
+		tukeyCtrlRR	<=	tukeyCtrlR;
+	end	else	begin
+		tukeyCtrlR	<=	0;
+		tukeyCtrlRR	<=	0;
+	end
+end
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		tukeyCorr	<=	(tukeyWind+constOne);
+		sinWindPow2	<=	sinWind**2;
+	end	else	begin
+		tukeyCorr	<=	18'h0;
+		sinWindPow2	<=	18'h0;
+	end
+end
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		case(tukeyCtrlRR)
+			2'h0:		begin
+							tukeyWindOut	=	0;
+						end
+			2'h1:		begin
+							tukeyWindOut	=	18'h1ffff;
+						end
+			2'h2:		begin
+							tukeyWindOut	=	tukeyCorr[18-:18];
+						end
+			default:	begin
+							tukeyWindOut	=	0;
+						end
+		endcase
+	end	else	begin
+		tukeyWindOut	=	18'h0;
+	end
+end
+
+always	@(posedge	wind_clk)	begin
+	if	(!reset_i)	begin
+			case	(calc_cycle)
+				3'd0: 	
+						begin
+							a1	<=	A5;
+							c1	<=	A4;
+							c2	<=	A3;
+							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+							b	<=	bCurr;
+						end
+						
+				3'd1:	
+						begin
+							a1	<=	p2[34:17];
+							c1	<=	A2;
+							c2	<=	A1;
+						end
+				3'd2:	
+						begin
+							a1	<=	p2[34:17];
+							c1	<=	b;
+						end
+			endcase
+	end	else	begin
+		a1	<=	18'b0;
+		c1	<=	18'b0;
+		c2	<=	18'b0;
+		b	<=	18'b0;
+	end
+end
+		
+always	@(posedge	wind_clk)	begin
+	if	(!reset_i)	begin
+		if	(!win_type_i)	begin 
+			if (calc_cycle	==	3'd0) begin
+				if	(p1[47:34]	==	0)	begin
+					sinWind	<=	p1[34-:18];//1.0.17	
+				end	else	begin
+					sinWind	<=	18'h1FFFF;
+				end
+				
+			end 
+		end	else	begin
+			sinWind		<=	18'h0;
+		end
+	end	else	begin
+		sinWind		<=	18'h0;
+	end
+end
+
+always	@(posedge	wind_clk)	begin
+	if	(!reset_i)	begin
+		if	(!win_type_i)	begin 
+			if (calc_cycle	==	3'd0) begin
+				if	(!WinCtrl_i)	begin
+					tukeyWind	<=	p1[34-:18];
+				end	else	begin
+					tukeyWind	<=	0-p1[34-:18];
+				end
+			end 
+		end	else	begin
+			tukeyWind	<=	18'h0;
+		end
+	end	else	begin
+		tukeyWind	<=	18'h0;
+	end
+end
+
+//??????? "????? ??????? ????????". ????????  [(b*A5+A4) = p1 ? ????????????? ?????? (b*p1+A3)=p2] == 1 ????.
+
+always	@(posedge	wind_clk)	begin
+	if	(!reset_i)	begin
+			if	(calc_cycle	!=	3'd2)	begin
+				calc_cycle	<=	calc_cycle	+	3'd1;
+			end	else	begin
+				calc_cycle	<=	3'd0;
+			end
+	end	else	begin
+		calc_cycle	<=	3'd0;
+	end
+end
+
+DSP48E1 #(
+      // Feature Control Attributes: Data Path Selection
+      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
+      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
+      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
+      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
+      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
+      // Pattern Detector Attributes: Pattern Detection Configuration
+      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
+      .MASK(48'h3fffffffffff),          // 48-bit mask value for pattern detect (1=ignore)
+      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
+      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
+      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
+      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
+      // Register Control Attributes: Pipeline Register Configuration
+      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
+      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
+      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
+      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
+      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
+      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
+      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
+      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
+      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
+      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
+      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
+      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
+      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
+      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+   )
+DSP48E1_1inst (
+      // Cascade: 30-bit (each) output: Cascade Ports
+      .ACOUT(),                   // 30-bit output: A port cascade output
+      .BCOUT(),                   // 18-bit output: B port cascade output
+      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
+      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
+      .PCOUT(),                   // 48-bit output: Cascade output
+      // Control: 1-bit (each) output: Control Inputs/Status Bits
+      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
+      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
+      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
+      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
+      // Data: 4-bit (each) output: Data Ports
+      .CARRYOUT(),             // 4-bit output: Carry output
+      .P(p1),                           // 48-bit output: Primary data output
+      // Cascade: 30-bit (each) input: Cascade Ports
+      .ACIN(),                     // 30-bit input: A cascade data input
+      .BCIN(),                     // 18-bit input: B cascade input
+      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
+      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
+      .PCIN(48'b0),                     // 48-bit input: P cascade input
+      // Control: 4-bit (each) input: Control Inputs/Status Bits
+      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
+      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
+      .CLK(1'b0),                       // 1-bit input: Clock input
+      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
+      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
+      // Data: 30-bit (each) input: Data Ports
+      .A({{12{a1[17]}},a1}),                           // 30-bit input: A data input
+      .B(b),                           // 18-bit input: B data input
+      .C({ {13{c1[17]}}, c1[17:0],17'b0 }),                           // 48-bit input: C data input
+      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
+      .D(25'b0),                           // 25-bit input: D data input
+      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
+      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
+      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
+      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
+      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
+      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
+      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
+      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
+      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
+      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
+      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
+      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
+      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
+      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
+      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
+      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
+      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
+      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
+      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+);
+   
+DSP48E1 #(
+      // Feature Control Attributes: Data Path Selection
+      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
+      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
+      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
+      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
+      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
+      // Pattern Detector Attributes: Pattern Detection Configuration
+      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
+      .MASK(48'h1),          // 48-bit mask value for pattern detect (1=ignore)
+      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
+      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
+      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
+      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
+      // Register Control Attributes: Pipeline Register Configuration
+      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
+      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
+      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
+      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
+      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
+      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
+      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
+      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
+      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
+      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
+      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
+      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
+      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
+      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+   )
+DSP48E1_2inst (
+      // Cascade: 30-bit (each) output: Cascade Ports
+      .ACOUT(),                   // 30-bit output: A port cascade output
+      .BCOUT(),                   // 18-bit output: B port cascade output
+      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
+      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
+      .PCOUT(),                   // 48-bit output: Cascade output
+      // Control: 1-bit (each) output: Control Inputs/Status Bits
+      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
+      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
+      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
+      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
+      // Data: 4-bit (each) output: Data Ports
+      .CARRYOUT(),             // 4-bit output: Carry output
+      .P(p2),                           // 48-bit output: Primary data output
+      // Cascade: 30-bit (each) input: Cascade Ports
+      .ACIN(),                     // 30-bit input: A cascade data input
+      .BCIN(),                     // 18-bit input: B cascade input
+      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
+      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
+      .PCIN(48'b0),                     // 48-bit input: P cascade input
+      // Control: 4-bit (each) input: Control Inputs/Status Bits
+      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
+      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
+      .CLK(1'b0),                       // 1-bit input: Clock input
+      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
+      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
+      // Data: 30-bit (each) input: Data Ports
+      .A({{12{p1[47]}},p1[34:17]}),                           // 30-bit input: A data input
+      .B(b),                           // 18-bit input: B data input
+      .C({ {13{c2[17]}}, c2[17:0],17'b0 }),                           // 48-bit input: C data input
+      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
+      .D(25'b0),                           // 25-bit input: D data input
+      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
+      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
+      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
+      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
+      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
+      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
+      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
+      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
+      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
+      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
+      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
+      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
+      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
+      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
+      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
+      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
+      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
+      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
+      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+);
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc_tb.v

@@ -0,0 +1,111 @@
+module WinCalcTb();
+
+reg	Clk_i;
+reg	WindClk;
+reg	Rst_i;
+reg	[31:0]	WinValue_i;
+reg	WinType_i;
+reg	CalcWind_i;
+reg	Val;
+
+always	#10 Clk_i	=	~Clk_i;
+always	#2.5	WindClk	=	~WindClk;	
+
+parameter	WV	=	32;
+
+initial	begin
+	Rst_i	=	1;
+	Clk_i	=	1;
+	WindClk	=	1;
+	WinValue_i	=	0;
+	WinType_i	=	0;
+	CalcWind_i	=	0;
+	#200
+	Rst_i	=	0;
+end
+
+
+// localparam	[31:0]	win_start_value	=	32'h02AAAAAB;
+// localparam	[31:0]	win_step_value	=	32'h05555555;
+
+localparam	[31:0]	win_start_value	=	32'h0;
+localparam	[31:0]	win_step_value	=	32'h4325c53;
+localparam	[31:0]	winPointsNum	=	32'h3D;
+
+reg	[31:0]	pointsCnt;
+reg	[31:0]	tb_cnt;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalcWind_i)	begin
+			if	(pointsCnt	!=	winPointsNum-1)	begin
+				pointsCnt	<=	pointsCnt+1;
+			end	else	begin
+				pointsCnt	<=	0;
+			end
+		end	else	begin
+			pointsCnt	<=	0;
+		end
+	end	else	begin
+		pointsCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(tb_cnt	==	50)	begin
+			CalcWind_i	<=	1;
+		end	else	if	(pointsCnt	==	winPointsNum-1)	begin
+			CalcWind_i	<=	0;
+		end
+	end
+end
+
+reg		[WV-1:0]	windArg;				
+// reg		[WV-1:0]	win_value_reg;				
+// wire	[WV-1:0]	win_value;					
+// wire	[WV	 :0]	win_next_value;				
+
+// assign	win_next_value			=	win_value_reg	+	win_step_value;
+// assign	win_value				=	(CalcWind_i)	?	win_next_value	:	win_start_value;
+	
+ // always	@(posedge	Clk_i)	begin
+	// if	(!Rst_i)	begin
+		// win_value_reg	<=	win_value;
+	// end	else	begin
+		// win_value_reg	<=	48'b0;
+	// end
+// end
+
+	
+ always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalcWind_i)	begin
+			windArg	<=	windArg+win_step_value;
+		end	else	begin
+			windArg	<=	win_start_value;
+		end
+	end	else	begin
+		windArg	<=	0;
+	end
+end
+	
+Win_calc	WinCalcInst
+(
+	.clk_i			(Clk_i),
+	.wind_clk		(WindClk),
+	.reset_i		(Rst_i),
+	.win_value_i	(windArg),
+	.win_type_i		(WinType_i),		
+	.calc_wind_i	(CalcWind_i),
+	.win_o			()
+);
+endmodule

S5443_M/S5443.srcs/sources_1/new/Math/FpCustomMultiplier.v

@@ -0,0 +1,116 @@
+module FpCustomMultiplier # (
+	parameter	ManWidth	=	16,
+	parameter	ExpWidth	=	6
+)
+(Rst_i,Clk_i,A_i,B_i,Nd_i,Result_o,ResultValid_o);	
+
+	localparam	InOutWidth	=	1+ExpWidth+ManWidth;
+	
+	input	Rst_i;
+	input	Clk_i;
+	
+	input	[InOutWidth-1:0]	A_i;
+	input	[InOutWidth-1:0]	B_i;
+	input	Nd_i;
+	output	[InOutWidth-1:0]	Result_o;
+	output	ResultValid_o;
+	
+	localparam	ExtManWidth			=	2+ManWidth;
+	localparam	MultResultWidth		=	(ExtManWidth*2)-2;
+	localparam	ExpConst			=	(2**(ExpWidth-1))-1;
+	
+	reg	expA_or;
+	reg	expB_or;
+	
+	reg	signed	[ExtManWidth-1:0]	manAReg;
+	reg	signed	[ExtManWidth-1:0]	manBReg;
+	
+	reg	[ExpWidth-1:0]	expAReg;
+	reg	[ExpWidth-1:0]	expBReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expA_or	<=	|A_i[InOutWidth-2 -:ExpWidth];	//looking for zero exponents for mult operation
+		expB_or	<=	|B_i[InOutWidth-2 -:ExpWidth];
+		
+		manAReg	<=	{2'b01,A_i[ManWidth-1 -:ManWidth]};	//add 0-sign and implied 1 to mantissa.
+		manBReg	<=	{2'b01,B_i[ManWidth-1 -:ManWidth]};
+		
+		expAReg	<=	A_i[InOutWidth-2 -:ExpWidth];	//exp highlight
+		expBReg	<=	B_i[InOutWidth-2 -:ExpWidth];
+	end
+	
+	reg	[ExpWidth:0]	expAddProd;
+	reg	expZero;
+	reg	signed	[MultResultWidth-1:0]	manMultProd;
+	
+	always	@(posedge	Clk_i)	begin
+		manMultProd	<=	manAReg*manBReg;	//man(C)=man(A)*man(B)
+		
+		expAddProd	<=	expAReg+expBReg-ExpConst;	//exp(C)=exp(A)+exp(B)-ExpConst. ExpConst = 2^ExpWidth-1;
+		
+		expZero	<=	~(expA_or&expB_or);	//setting exp(C) = 0 when either A or B is zero or denormalized.
+	end
+	
+	reg	[ExpWidth-1:0]	expCReg;
+	reg	expResultNegative;
+	reg	[ManWidth-1:0]	manCReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expResultNegative	<=	expAddProd[ExpWidth]; //if exponents are too small then their result will be negative
+		
+		if	(Rst_i)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	begin
+			expCReg	<=	expAddProd[ExpWidth-1:0]+manMultProd[MultResultWidth-1];
+		end
+		
+		if	(Rst_i)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(!manMultProd[MultResultWidth-1])	begin	//normalize man(C) in accordance to MSB value
+			manCReg	<=	manMultProd[MultResultWidth-3 -:ManWidth];	
+		end	else	begin
+			manCReg	<=	manMultProd[MultResultWidth-2 -:ManWidth];
+		end
+	end
+		
+	reg	[4:0]	signCShReg;
+	always	@(posedge	Clk_i)	begin
+		signCShReg	<=	{signCShReg[3:0], A_i[InOutWidth-1] ^ B_i[InOutWidth-1]};
+	end
+	
+	reg	[5:0]	resValidShReg;
+	always	@(posedge	Clk_i)	begin
+		resValidShReg	<=	{resValidShReg[4:0],	Nd_i};
+	end
+	
+	assign Result_o = {signCShReg[2], expCReg,manCReg};
+	assign ResultValid_o = resValidShReg[2];
+	
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/Math/MultModule.v

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MultModule	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	IfNcoOutWidth	=	18,
+	parameter	MultDataWidth	=	36
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	signed	[AdcDataWidth-1:0]	AdcData_i,
+	input	signed	[IfNcoOutWidth-1:0]	Sin_i,
+	input	signed	[IfNcoOutWidth-1:0]	Cos_i,
+	output	signed	[MultDataWidth-1:0]	AdcSin_o,
+	output	signed	[MultDataWidth-1:0]	AdcCos_o
+);
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//  REG/WIRE
+	wire	signed	[IfNcoOutWidth-1:0]	adcDataCompl	=	{AdcData_i,4'b0};
+	
+	reg	[MultDataWidth-1:0]	AdcSinReg;
+	reg	[MultDataWidth-1:0]	AdcCosReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AdcSin_o	=	AdcSinReg;
+	assign	AdcCos_o	=	AdcCosReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			AdcSinReg	<=	adcDataCompl*Sin_i;
+			AdcCosReg	<=	adcDataCompl*Cos_i;
+		end	else	begin
+			AdcSinReg	<=	{MultDataWidth{1'b0}};
+			AdcCosReg	<=	{MultDataWidth{1'b0}};
+		end
+	end
+	
+endmodule

S5443_M/S5443.srcs/sources_1/new/Math/Mult_calc.v

@@ -0,0 +1,107 @@
+`timescale 1ns / 1ps
+	
+module Mult_calc	(
+	input			clk_i, 
+	input			reset_i,
+	input			[13:0]	adc_i,	
+	input	[17:0]	sin_i, 
+	input	[17:0]	cos_i,
+	input			[17:0]	win_i,
+	input			sum_en_i,	
+	output	[39:0]	sum_re_o,
+	output	[39:0]	sum_im_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	wire	[47:0]	sum_cos;
+	wire	[47:0]	sum_sin;		
+	wire 			ovfl_sum_cos;	// Check For Overflow
+	wire 			ovfl_sum_sin;
+	reg[9:0] 		null_corr	= 10'b0;	// Êîððåêòèðîâêà íóëÿ
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	
+	assign ovfl_sum_cos	= (sum_cos[41]^sum_cos[42])|(sum_cos[42]^sum_cos[43]);	// Check For Overflow
+	assign ovfl_sum_sin	= (sum_sin[41]^sum_sin[42])|(sum_sin[42]^sum_sin[43]);	// Check For Overflow
+
+	
+	assign sum_re_o 	= (ovfl_sum_cos) ? { sum_cos[41],{39{~sum_cos[41]}}} : {sum_cos[40:1]};
+	assign sum_im_o 	= (ovfl_sum_sin) ? { sum_sin[41],{39{~sum_sin[41]}}} : {sum_sin[40:1]};	
+	//works for now 
+	//======================================
+	wire [35:0]	adc_wind;
+//================================================================================
+//  CODING
+//================================================================================		
+	
+//Null correction * Window	
+Dsp48Mult	NullCorrWind
+(
+  .CLK	(clk_i),
+  .A	({{8{null_corr[9]}},null_corr[9:0]}),
+  .B	(win_i),
+  .C	(40'd0),
+  .D	({adc_i[13:0],4'b0}),
+  .P	(adc_wind)
+);
+
+	DSP48A1 #(
+       .A0REG(0),              // First stage A input pipeline register (0/1)
+       .A1REG(0),              // Second stage A input pipeline register (0/1)
+       .B0REG(0),              // First stage B input pipeline register (0/1)
+       .B1REG(0),              // Second stage B input pipeline register (0/1)
+       .CARRYINREG(0),         // CARRYIN input pipeline register (0/1)
+       .CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5" 
+       .CARRYOUTREG(0),        // CARRYOUT output pipeline register (0/1)
+       .CREG(1),               // C input pipeline register (0/1)
+       .DREG(0),               // D pre-adder input pipeline register (0/1)
+       .MREG(0),               // M pipeline register (0/1)
+       .OPMODEREG(1),          // Enable=1/disable=0 OPMODE input pipeline registers
+       .PREG(1),               // P output pipeline register (0/1)
+       .RSTTYPE("SYNC")        // Specify reset type, "SYNC" or "ASYNC" 
+    )
+    DSP48A1_wind_cos (
+	//  Cascade Ports: No Cascade
+		.BCOUT(),   	   	   // 18-bit output: B port cascade output
+		.PCOUT(), 	   	      // 48-bit output: P cascade output
+	//   Data Ports: 1-bit (each) output: Data input and output ports
+		.CARRYOUT(),			// 1-bit output: carry output                               
+		.CARRYOUTF(),  			// 1-bit output: fabric carry output
+		.M(), 			        // 36-bit output: fabric multiplier data output
+		.P(sum_cos),      		// 48-bit output: data output
+	//  Cascade Ports: 48-bit (each) input: No Cascade
+		.PCIN(48'b0),           // 48-bit input: P cascade input
+	// Control Input Ports: 1-bit (each) input: Clocking and operation mode
+		.CLK(clk_i),           
+		.OPMODE({4'b0000,sum_en_i,3'b001}),// 8-bit input: operation mode input
+		 // .OPMODE({4'b0000,sum_en_i,sum_en_i,2'b01}),// 8-bit input: operation mode input
+	// Data Ports: 18-bit (each) input: Data input and output ports
+		.A(adc_wind[34:17]),    // 18-bit input: A data input
+		.B(cos_i), 				// 18-bit input: B data input
+		.C(sum_cos),			// 48-bit input: C data input
+		.CARRYIN(1'b0),			// 1-bit input: carry input signal
+		.D(18'b0),				// 18-bit input: B pre-adder data input
+	//  Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports
+		.CEA(1'b1),				// 1-bit input: clock enable input for A registers
+		.CEB(1'b1),				// 1-bit input: clock enable input for B registers
+		.CEC(1'b1),    			// 1-bit input: clock enable input for C registers
+		.CECARRYIN(1'b1),   	// 1-bit input: clock enable input for CARRYIN registers
+		.CED(1'b1),             // 1-bit input: clock enable input for D registers
+		.CEM(1'b1),             // 1-bit input: clock enable input for multiplier registers
+		.CEOPMODE(1'b1),		// 1-bit input: clock enable input for OPMODE registers
+		.CEP(1'b1),    			// 1-bit input: clock enable input for P registers
+		.RSTA(1'b0),            // 1-bit input: reset input for A pipeline registers
+		.RSTB(1'b0),            // 1-bit input: reset input for B pipeline registers
+		.RSTC(1'b0),            // 1-bit input: reset input for C pipeline registers
+		.RSTCARRYIN(1'b0), 		// 1-bit input: reset input for CARRYIN pipeline registers
+		.RSTD(1'b0),            // 1-bit input: reset input for D pipeline registers
+		.RSTM(1'b0),            // 1-bit input: reset input for M pipeline registers
+		.RSTOPMODE(1'b0),		// 1-bit input: reset input for OPMODE pipeline registers
+		.RSTP(1'b0)   	        // 1-bit input: reset input for P pipeline registers
+    );
+	
+endmodule

S5443_M/S5443.srcs/sources_1/new/Math/MyIntToFp.v

@@ -0,0 +1,147 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:14:34 01/28/2021 
+// Design Name: 
+// Module Name:    FpConvTop 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MyIntToFp	
+#(	
+	parameter	InWidth		=	32,
+	parameter	ExpWidth	=	8,
+	parameter	ManWidth	=	23,
+	parameter	FracWidth	=	17
+)
+(Clk_i,Rst_i,InData_i,InDataVal_i,OutData_o,OutDataVal_o);
+
+	input	Clk_i;
+	input	Rst_i;
+	input	[InWidth-1:0]	InData_i;
+	input	InDataVal_i;
+	
+	localparam	OutWidth	=	1+ExpWidth+ManWidth;	//sign+ExpWidth+ManWidth
+	localparam	ExpConst	=	(2**(ExpWidth-1))-1;
+	
+	output	reg	[OutWidth-1:0]	OutData_o;
+	output	reg	OutDataVal_o;
+	
+//================================================================================
+//  Func
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<InWidth)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+	
+	localparam Stages = Log2(InWidth);
+	
+//================================================================================
+//  Coding
+	reg		[InWidth-1:0]	inDataR;
+	reg		signR;
+	reg		outValR;
+	wire	[OutWidth-1:0]	fpOut;
+	wire	[Stages-1:0]	distance;
+	genvar  i;
+	wire	[ExpWidth-1:0]	fpExp;
+	
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		inDataR	<=	{InWidth{1'b0}};
+		signR	<=	1'b0;
+		outValR	<=	1'b0;
+	end	else	begin
+		if	(InData_i	[InWidth-1])	begin
+			inDataR	<=	~InData_i+1'b1;
+		end	else	begin
+			inDataR	<=	InData_i;
+		end
+		signR	<=	InData_i[InWidth-1];
+		outValR	<=	InDataVal_i;
+	end
+end
+
+wire	[(Stages+1)*InWidth-1:0]	dataArray;
+
+assign  dataArray [InWidth-1:0] = inDataR;			
+	
+generate	
+	for (i=0; i<Stages; i=i+1)	begin: searchMSB
+		wire [InWidth-1:0] dataIn;	
+        wire [InWidth-1:0] shiftedDataOut;
+        wire [InWidth-1:0] dataOut;
+		
+        assign  dataIn = dataArray[(i+1)*InWidth-1:i*InWidth];
+
+        wire    shiftDesired = ~|(dataIn[InWidth-1:InWidth-(1 << (Stages-1-i))]);
+        assign  distance[(Stages-1-i)] = shiftDesired;		
+        assign  shiftedDataOut = dataIn << (1 << (Stages-1-i));	
+        assign  dataOut = shiftDesired ? shiftedDataOut : dataIn;	
+        assign  dataArray[(i+2)*InWidth-1:(i+1)*InWidth] = dataOut;	
+	end
+endgenerate
+
+wire	[InWidth-1:0]	scaledData	=	dataArray[(Stages+1)*InWidth-1:Stages*InWidth];
+wire	[ManWidth-1:0]	mantisa		=	scaledData[InWidth-2 -:ManWidth];
+
+assign	fpExp		=	(ExpConst+(InWidth-1-FracWidth))-distance;
+assign	fpOut		=	&distance ? {signR, 31'h0}:	{signR, fpExp,	mantisa};
+
+always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+	if	(Rst_i)	begin
+		OutData_o		<=	{OutWidth{1'b0}};
+		OutDataVal_o	<=	1'b0;
+	end	else	begin
+		if	(outValR)	begin
+			OutData_o	<=	fpOut;
+		end
+		OutDataVal_o	<=	outValR;
+	end
+end
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/Math/SimpleMult.v

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    SimpleMult 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	SimpleMult	
+#(	
+	parameter	FactorAWidth	=	14,
+	parameter	FactorBWidth	=	14,
+	parameter	OutputWidth		=	18
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	Val_i,
+	input	signed	[FactorAWidth-1:0]	FactorA_i,
+	input	signed	[FactorBWidth-1:0]	FactorB_i,
+	
+	
+	output	signed	[OutputWidth-1:0]	Result_o,
+	output	ResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	ResultWidth	=	FactorAWidth+FactorBWidth;
+//================================================================================
+//  REG/WIRE
+	reg	[ResultWidth-1:0]	resultReg;
+	reg	resultValReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	(ResultWidth==OutputWidth)?	resultReg:resultReg[ResultWidth-2-:OutputWidth];
+	assign	ResultVal_o	=	resultValReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(Val_i)	begin
+				resultReg		<=	FactorA_i*FactorB_i;
+				resultValReg	<=	Val_i;
+			end	else	begin
+				resultReg		<=	{ResultWidth{1'b0}};
+				resultValReg	<=	1'b0;
+			end
+		end	else	begin
+			resultReg		<=	{ResultWidth{1'b0}};
+			resultValReg	<=	1'b0;
+		end
+	end
+endmodule

S5443_M/S5443.srcs/sources_1/new/Math/SumAcc.v

@@ -0,0 +1,39 @@
+module SumAcc 
+#(	
+	parameter	IDataWidth	=	14,
+	parameter	ODataWidth	=	48
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+	input	[IDataWidth-1:0]	Data_i,
+	
+	output	[ODataWidth-1:0]	Result_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg		[ODataWidth-1:0]	dataAcc;
+	reg		resultVal;
+	wire	[ODataWidth-1:0]	extData	=	{{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i};	//sign extension
+	
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	dataAcc;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			dataAcc		<=	{ODataWidth{1'b0}};
+		end	else	if	(Val_i)	begin
+			dataAcc		<=	dataAcc+extData;
+		end	else	begin
+			dataAcc		<=	0;
+		end
+	end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/Math/resultViewer.v

@@ -0,0 +1,53 @@
+module resultViewer
+#(
+	parameter	ExpWidth	=	8,
+	parameter	ManWidth	=	23,
+	parameter	InWidth		=	32
+)
+(
+	input Clk_i,
+	input [InWidth-1:0] Data_i,
+	input DataNd_i
+);
+	
+	localparam	ExpConst		=	(2**(ExpWidth-1))-1;
+	
+	function real Fp32ToRealFunc;
+		input [InWidth-1:0] Data;
+		reg sign;
+		reg [ExpWidth-1:0] exp;
+		reg [ManWidth-1:0] frac;
+		real realFrac;
+		real realDiv;
+		real realExp;
+		reg	[63:0]	Test64bitReg;
+	begin
+		sign = Data[InWidth-1];
+		exp = Data[InWidth-2 -:ExpWidth];
+		frac = Data[ManWidth-1:0];
+		Test64bitReg	=	2**(exp - ExpConst);
+		realFrac = frac;
+		realDiv = 2**ManWidth;
+		
+		if (exp > ExpConst)
+			realExp = 2**(exp - ExpConst);
+		else if (exp < ExpConst)
+			realExp = 1.0 / (2.0**(ExpConst-exp));
+		else 
+			realExp = 1.0;
+
+		if ((exp == 0) && (frac == 0))
+			Fp32ToRealFunc = 0;
+		else
+			Fp32ToRealFunc = ((-1)**sign) * (1.0 + (realFrac / realDiv)) * Test64bitReg;
+	end
+	endfunction
+
+	real dataReal;
+	always @ (posedge Clk_i)
+		if (DataNd_i) begin
+			dataReal = Fp32ToRealFunc(Data_i);
+			// $display("%e\n", dataReal);
+		end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/FftDataFormer.v

@@ -0,0 +1,137 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+module FftDataFormer
+#(	
+	parameter	AdcDataWidth		=	16,	
+	parameter	ExtAdcDataWidth		=	AdcDataWidth+2,	
+	parameter	ChNum				=	1,
+	parameter	OutDataWidth		=	256,
+	parameter	DataValCycles		=	OutDataWidth/(AdcDataWidth*2)
+)	
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	OscWind_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	[AdcDataWidth*2-1:0]	AdcData_i,
+	input	AdcDataVal_i,
+
+	
+	output	[OutDataWidth-1:0]	OscDataBus_o,
+	output	OscDataBusVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	reg	[OutDataWidth-1:0]	oscDataBusReg;
+	reg	[OutDataWidth-1:0]	oscDataBusRegReg;
+	
+	reg	oscDataBusValReg;
+	reg	oscDataBusValRegReg;
+	
+	reg	[DataValCycles-1:0]	cycleCnt;
+	
+	reg	[31:0]	wrDataCnt;
+	wire	wrDone	=	OscWind_i?	(wrDataCnt	==	MeasNum_i):1'b0;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+	assign	OscDataBus_o	=	oscDataBusRegReg;
+	assign	OscDataBusVal_o	=	oscDataBusValRegReg;
+	
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(!wrDone)	begin
+					oscDataBusValRegReg	<=	oscDataBusValReg;
+				end	else	begin
+					oscDataBusValRegReg	<=	0;
+				end
+			end	else	begin
+				oscDataBusValRegReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusValRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscDataBusValReg)	begin
+				// oscDataBusRegReg	<=	oscDataBusReg;
+				oscDataBusRegReg	<=	{oscDataBusReg[127:0], oscDataBusReg[OutDataWidth-1:128]};
+			end	
+		end	else	begin
+			oscDataBusRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					if	(cycleCnt	!=	DataValCycles-1)	begin
+						cycleCnt	<=	cycleCnt+4'd1;
+					end	else	begin
+						cycleCnt	<=	4'd0;
+					end
+				end	
+			end	else	begin
+				cycleCnt	<=	0;
+			end
+		end	else	begin
+			cycleCnt	<=	4'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(oscDataBusValRegReg)	begin
+					if	(wrDataCnt	!=	MeasNum_i)	begin
+						wrDataCnt	<=	wrDataCnt+1;
+					end
+				end
+			end	else	begin
+				wrDataCnt	<=	0;
+			end
+		end	else	begin
+			wrDataCnt	<=	0;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					oscDataBusReg	<=	{oscDataBusReg[OutDataWidth-AdcDataWidth-1:0],AdcData_i};	//first points
+				end
+			end	else	begin
+				oscDataBusReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(cycleCnt	==	DataValCycles-1	&	AdcDataVal_i)	begin
+				oscDataBusValReg	<=	1'b1;
+			end	else	begin
+				oscDataBusValReg	<=	1'b0;
+			end
+		end	else	begin
+			oscDataBusValReg	<=	1'b0;
+		end
+	end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+	
+module FifoController	
+(
+	input	Clk_i, 
+	input	ClkPpiOut_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	input	MeasDataVal_i,
+	input	FullFlag_i,
+	input	EmptyFlag_i,
+	
+	output	MeasDataVal_o,
+	
+	output	reg	WrEn_o,
+	output	RdEn_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	rdEn;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
+	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
+//================================================================================
+//  CODING
+//================================================================================		
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(MeasDataVal_i)	begin
+			if	(!FullFlag_i)	begin
+				WrEn_o	<=	1'b1;
+			end	else	begin
+				WrEn_o	<=	1'b0;
+			end
+		end	else	begin
+			WrEn_o	<=	1'b0;
+		end
+	end	else	begin
+		WrEn_o	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!PpiBusy_i)	begin
+			if	(!EmptyFlag_i)	begin
+				rdEn	<=	1'b1;
+			end	else	begin
+				rdEn	<=	1'b0;
+			end
+		end	else	begin
+			rdEn	<=	1'b0;
+		end
+	end	else	begin
+		rdEn	<=	1'b0;
+	end
+end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+	
+module MeasDataFifoWrapper	
+#(	
+	parameter	DataWidth	=	32,
+	parameter	ChNum		=	4
+)
+(
+	input	Clk_i, 
+	input	ClkPpiOut_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	
+	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	input	MeasDataVal_i,
+	
+	output	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_o,
+	output	MeasDataVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	wire	fullFlag;
+	wire	emptyFlag;
+	wire	wrEn;
+	wire	rdEn;
+	wire	fifoRst;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	MeasDataVal_o	=	rdEn;	
+//================================================================================
+//  CODING
+//================================================================================		
+
+	
+MeasDataFifo	MeasDataFifoInst
+(
+	.clk	(Clk_i),
+	// .srst	(fifoRst),
+	// .srst	(Rst_i|fifoRst),
+	.srst	(Rst_i),
+	.din	(MeasDataBus_i),
+	.wr_en	(wrEn),
+	.rd_en	(rdEn),
+	.dout	(MeasDataBus_o),
+	.full	(fullFlag),
+	.empty	(emptyFlag)
+);
+
+  
+FifoController	FifoControllerInst
+(
+	.Clk_i			(Clk_i), 
+	.Rst_i			(Rst_i),	
+	.PpiBusy_i		(PpiBusy_i),	
+	.MeasDataVal_i	(MeasDataVal_i),
+	.FullFlag_i		(fullFlag),
+	.EmptyFlag_i	(emptyFlag),
+	
+	.MeasDataVal_o	(),
+	.WrEn_o			(wrEn),
+	.RdEn_o			(rdEn)
+);
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/OscDataFormer.v

@@ -0,0 +1,132 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+module OscDataFormer
+#(	
+	parameter	AdcDataWidth		=	14,	
+	parameter	ExtAdcDataWidth		=	AdcDataWidth+2,	
+	parameter	ChNum				=	1,
+	parameter	DataValCycles		=	16,
+	parameter	OutDataWidth		=	(16*ChNum)*DataValCycles
+)	
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	OscWind_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	[AdcDataWidth-1:0]	AdcData_i,	
+	
+	output	[OutDataWidth-1:0]	OscDataBus_o,
+	output	OscDataBusVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	wire	signed	[15:0]	adcDataExt	=	{{2{AdcData_i[AdcDataWidth-1]}},AdcData_i};
+	
+	reg	[OutDataWidth-1:0]	oscDataBusReg;
+	reg	[OutDataWidth-1:0]	oscDataBusRegReg;
+	
+	reg	oscDataBusValReg;
+	reg	oscDataBusValRegReg;
+	
+	reg	[DataValCycles-1:0]	cycleCnt;
+	
+	reg	[31:0]	wrDataCnt;
+	wire	wrDone	=	OscWind_i?	(wrDataCnt	==	MeasNum_i):1'b0;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	OscDataBus_o	=	oscDataBusRegReg;
+	assign	OscDataBusVal_o	=	oscDataBusValRegReg;
+	
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(!wrDone)	begin
+					oscDataBusValRegReg	<=	oscDataBusValReg;
+				end	else	begin
+					oscDataBusValRegReg	<=	0;
+				end
+			end	else	begin
+				oscDataBusValRegReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusValRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscDataBusValReg)	begin
+				oscDataBusRegReg	<=	{oscDataBusReg[127:0], oscDataBusReg[OutDataWidth-1:128]};
+				// oscDataBusRegReg	<=	{16'h7,16'h6,16'h5,16'h4,16'h3,16'h2,16'h1,16'h0,16'hF,16'hE,16'hD,16'hC,16'hB,16'hA,16'h9,16'h8};
+			end	
+		end	else	begin
+			oscDataBusRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(cycleCnt	!=	DataValCycles-1)	begin
+					cycleCnt	<=	cycleCnt+4'd1;
+				end	else	begin
+					cycleCnt	<=	4'd0;
+				end
+			end	else	begin
+				cycleCnt	<=	0;
+			end
+		end	else	begin
+			cycleCnt	<=	4'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(oscDataBusValRegReg)	begin
+					if	(wrDataCnt	!=	MeasNum_i)	begin
+						wrDataCnt	<=	wrDataCnt+1;
+					end
+				end
+			end	else	begin
+				wrDataCnt	<=	0;
+			end
+		end	else	begin
+			wrDataCnt	<=	0;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				oscDataBusReg	<=	{adcDataExt,oscDataBusReg[OutDataWidth-1:AdcDataWidth+2]};	//first points
+			end	else	begin
+				oscDataBusReg		<=	0;
+			end
+		end	else	begin
+			oscDataBusReg		<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(cycleCnt	==	DataValCycles-1)	begin
+				oscDataBusValReg	<=	1'b1;
+			end	else	begin
+				oscDataBusValReg	<=	1'b0;
+			end
+		end	else	begin
+			oscDataBusValReg	<=	1'b0;
+		end
+	end
+	
+endmodule

S5443_M/S5443.srcs/sources_1/new/P2P5meas.txt

@@ -0,0 +1,643 @@
+// `timescale 1ns / 1ns
+module S5443TopPMTb;
+	
+	//=================================================================================================================================================================================================================
+	//COMMANDS	FOR REG_MAP
+	parameter	[31:0]	MeasCmd 			= {8'h11,8'h0,8'h72,8'h0};
+	parameter	[31:0]	IfFtwH 				= {8'h15,16'h0,8'h23};
+	parameter	[31:0]	IfFtwL 				= {8'h16,24'h51eb85};
+	
+	
+	
+	
+	
+	parameter	[31:0]	PulseMeasCtrlCmd 		=	{8'h1b,12'h0,4'h0,8'h1};	
+	parameter	[31:0]	PG12ModeRegCmd			=	{8'h0b,8'h0,8'h1,8'h1};	
+	parameter	[31:0]	PG34GModeRegCmd			=	{8'h0c,8'h0,8'h1,8'h1};
+	parameter	[31:0]	GGPnumRegCmd			=	{8'h0d,24'h1};
+	//PG1 Cmd
+	parameter	[31:0]	PG1P1DelayRegCmd		=	{8'h28,24'd10};
+	parameter	[31:0]	PG1P2DelayRegCmd		=	{8'h29,24'd50};
+	parameter	[31:0]	PG1P3DelayRegCmd		=	{8'h2a,24'd90};
+	parameter	[31:0]	PG1P123DelayRegCmd		=	{8'h2b,24'd0};
+	parameter	[31:0]	PG1P1WidthRegCmd		=	{8'h2c,24'd30};
+	parameter	[31:0]	PG1P2WidthRegCmd		=	{8'h2d,24'd30};
+	parameter	[31:0]	PG1P3WidthRegCmd		=	{8'h2e,24'd30};
+	parameter	[31:0]	PG1P123WidthRegCmd		=	{8'h2f,24'd0};
+
+	//SSG Cmd
+	parameter	[31:0]	SSGP1DelayRegCmd		=	{8'h4e,24'd20};
+	parameter	[31:0]	SSGP2DelayRegCmd		=	{8'h4f,24'd35};
+	parameter	[31:0]	SSGP12DelNumRegCmd		=	{8'h50,24'd0};
+	parameter	[31:0]	SSGPNumRegCmd			=	{8'h51,24'd1};
+	
+	parameter	[31:0]	RefSeqPerRegCmd			=	{8'h52,24'd59};
+	parameter	[31:0]	MeasNumRegCmd			=	{8'h53,24'd5};
+	parameter	[31:0]	RefSeqPerMNumRegCmd		=	{8'h54,24'd0};
+	
+	
+	
+	
+	
+	//PG1-4 Cmd
+	parameter	[31:0]	PG1PNumRegCmd			=	{8'h48,24'd1};
+	parameter	[31:0]	PG2PNumRegCmd			=	{8'h49,24'd1};
+	parameter	[31:0]	PG3PNumRegCmd			=	{8'h4a,24'd1};
+	parameter	[31:0]	PG4PNumRegCmd			=	{8'h4b,24'd1};
+	parameter	[31:0]	PG12PNumRegCmd			=	{8'h4c,24'd0};
+	parameter	[31:0]	PG34GPNumRegCmd			=	{8'h4d,24'd0};
+
+	//Gating Gen Cmd
+	parameter	[31:0]	GGP1DelayRegCmd			=	{8'h1c,24'd6};
+	parameter	[31:0]	GGP2DelayRegCmd			=	{8'h1d,24'd16};
+	parameter	[31:0]	GGP3DelayRegCmd			=	{8'h1e,24'd31};
+	parameter	[31:0]	GGP123DelayRegCmd		=	{8'h1f,24'd0};
+	parameter	[31:0]	GGP1WidthRegCmd			=	{8'h20,24'd45};
+	parameter	[31:0]	GGP2WidthRegCmd			=	{8'h21,24'd5};
+	parameter	[31:0]	GGP3WidthRegCmd			=	{8'h22,24'd6};
+	parameter	[31:0]	GGP123WidthRegCmd		=	{8'h23,24'd0};
+	
+
+	
+	parameter	[31:0]	FilterCorrCmdH 		= {8'h17,24'hD70A3D};
+	parameter	[31:0]	FilterCorrCmdL 		= {8'h18,24'hD70A3D};
+	
+		
+	//PG2 Cmd
+	parameter	[31:0]	PG2P1DelayRegCmd		=	{8'h30,24'd5};
+	parameter	[31:0]	PG2P2DelayRegCmd		=	{8'h31,24'd15};
+	parameter	[31:0]	PG2P3DelayRegCmd		=	{8'h32,24'd30};
+	parameter	[31:0]	PG2P123DelayRegCmd		=	{8'h33,24'd0};
+	parameter	[31:0]	PG2P1WidthRegCmd		=	{8'h34,24'd5};
+	parameter	[31:0]	PG2P2WidthRegCmd		=	{8'h35,24'd6};
+	parameter	[31:0]	PG2P3WidthRegCmd		=	{8'h36,24'd7};
+	parameter	[31:0]	PG2P123WidthRegCmd		=	{8'h37,24'd0};
+	
+	//PG3 Cmd
+	parameter	[31:0]	PG3P1DelayRegCmd		=	{8'h38,24'd5};
+	parameter	[31:0]	PG3P2DelayRegCmd		=	{8'h39,24'd15};
+	parameter	[31:0]	PG3P3DelayRegCmd		=	{8'h3a,24'd30};
+	parameter	[31:0]	PG3P123DelayRegCmd		=	{8'h3b,24'd0};
+	parameter	[31:0]	PG3P1WidthRegCmd		=	{8'h3c,24'd5};
+	parameter	[31:0]	PG3P2WidthRegCmd		=	{8'h3d,24'd6};
+	parameter	[31:0]	PG3P3WidthRegCmd		=	{8'h3e,24'd7};
+	parameter	[31:0]	PG3P123WidthRegCmd		=	{8'h3f,24'd0};
+	
+	//PG4 Cmd
+	parameter	[31:0]	PG4P1DelayRegCmd		=	{8'h40,24'd5};
+	parameter	[31:0]	PG4P2DelayRegCmd		=	{8'h41,24'd15};
+	parameter	[31:0]	PG4P3DelayRegCmd		=	{8'h42,24'd30};
+	parameter	[31:0]	PG4P123DelayRegCmd		=	{8'h43,24'd0};
+	parameter	[31:0]	PG4P1WidthRegCmd		=	{8'h44,24'd5};
+	parameter	[31:0]	PG4P2WidthRegCmd		=	{8'h45,24'd6};
+	parameter	[31:0]	PG4P3WidthRegCmd		=	{8'h46,24'd7};
+	parameter	[31:0]	PG4P123WidthRegCmd		=	{8'h47,24'd0};
+	
+	//=================================================================================================================================================================================================================
+	
+	reg		Clk41;
+	reg		Clk82;
+	reg		Clk50;
+	reg		Clk70;
+	reg		Dclk175;
+	reg		Clk350;
+	reg		Clk125;
+	
+	reg	[31:0]	tb_cnt=4'd0;
+	reg	rst;
+	reg	mosi_i	=	1'b0;
+	reg	Miso_i	=	1'b0;
+	reg	ss_i;
+	reg	clk_i	=	1'b0;
+	
+	
+	reg	[31:0]	DspSpiData;
+	reg		startCalcCmdReg;
+	wire	startCalcCmdRegO;
+						
+	wire	[13:0]	cos_value;	
+	wire	[17:0]	sin_value;				
+
+	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
+	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
+	
+	// wire	ExtTrigger0		=	(tb_cnt	<=	150)?	ExtDspTrigPos0:ExtDspTrigNeg0;
+	wire	ExtTrigger0		=	ExtDspTrigNeg0;
+	
+	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
+	wire	endMeas;
+	reg	[31:0]	cmdCnt;
+	
+	reg	trig0;
+	reg	trig1;
+	
+	wire	trig0R;
+    wire	trig1R;
+	
+	assign	trig0R	=	trig0;
+    assign	trig1R	=	trig1;
+	
+//==========================================================================================
+//clocks gen
+	always	#10 Clk50	=	~Clk50;
+	always	#8 Clk125	=	~Clk125;
+	always	#14.285714285714 Clk70	=	~Clk70;
+	always	#10 clk_i	=	~clk_i;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+	
+	reg	Dclk175Reg;
+	wire	sck_i;	
+//==========================================================================================
+initial begin
+	Clk50	=	1'b1;
+	Clk70	=	1'b1;
+	Clk125	=	1'b1;
+	rst		=	1'b1;
+	Clk41	=	1'b0;
+	startCalcCmdReg	=	1'b0;
+	trig0	=	1'b0;
+	trig1	=	1'b0;
+#100;
+	rst		=	1'b0;
+#400;
+	Clk41	=	1'b0;
+end		
+	
+reg	endMeasReg;
+always	@(posedge	Clk41)	begin
+	endMeasReg	<=	endMeas;
+end
+
+wire	endMeasNeg	=	!endMeas&endMeasReg;
+
+always	@(posedge	Clk70)	begin
+	if	(tb_cnt	==	3000)	begin
+		startCalcCmdReg	<=	1'b1;
+	end	else	if	(endMeas)	begin
+		startCalcCmdReg	<=	1'b0;
+	end	
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+reg	startMeasSync;
+always	@(posedge	Clk41)	begin
+	startMeasSync	<=	startCalcCmdRegO;
+end
+
+wire	Adc1DataDa0P;
+wire	Adc1DataDa1P;
+
+wire	[31:0]	test	=	32'h2351eb85;
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test>>1),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sin_value),
+	.Cos_o				(cos_value),
+	.Val_o				()
+);
+
+wire	[13:0]	TPSK1		=	14'h1;
+wire	[13:0]	TPSKN1		=	14'b11111111111111;
+wire	[13:0]	I			=	(tb_cnt	>=	300	&&	tb_cnt	<=	500)?	TPSK1:TPSKN1;
+wire	[13:0]	Q			=	(tb_cnt	>=	200	&&	tb_cnt	<=	500)?	TPSKN1:TPSK1;
+
+//----------------------------------------------
+// Module generates wind for measurement
+wire	[17:0]	wind;
+wire	[13:0]	adcWind;
+CordicNco		
+#(	
+	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0),
+	.WinTypeW	(3)
+)
+winGenInst
+(
+	.Clk_i		(Clk50),
+	.Rst_i		(1'b0),
+	.Val_i		(1'b1),
+	.PhaseInc_i	(32'h45>>1),
+	.WinType_i	(0),
+	.WindVal_i	(1'b1),
+	.Wind_o		(wind),
+	.Sin_o		(),
+	.Cos_o		(),
+	.Val_o		()
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(18),
+	.FactorBWidth	(18),
+	.OutputWidth	(14)
+)
+AdcWindMult	
+(
+	.Rst_i		(1'b0),
+	.Clk_i		(Clk50),
+	.Val_i		(1'b1),
+	.FactorA_i	(sin_value),
+	.FactorB_i	(wind),
+	.Result_o	(adcWind),
+	.ResultVal_o()
+);
+
+
+S5443Top uut (
+	.Clk_i				(Clk50),
+	.Led_o				(),
+//------------------------------------------	
+    .Adc1FclkP_i		(Clk70),		
+    .Adc1FclkN_i		(~Clk70),		
+		
+    .Adc1DataDa0P_i		(Adc1DataDa0P),
+	.Adc1DataDa0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDa1P_i		(Adc1DataDa1P),
+    .Adc1DataDa1N_i		(~Adc1DataDa1P),
+    	
+	.Adc1DataDb0P_i		(Adc1DataDa0P),
+    .Adc1DataDb0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDb1P_i		(Adc1DataDa1P),
+    .Adc1DataDb1N_i		(~Adc1DataDa1P),
+//------------------------------------------	
+    .Adc2FclkP_i		(Clk70),		
+    .Adc2FclkN_i		(~Clk70),		
+			
+    .Adc2DataDa0P_i		(1'b1),
+    .Adc2DataDa0N_i		(1'b0),		
+    .Adc2DataDa1P_i		(1'b1),
+    .Adc2DataDa1N_i		(1'b0),
+  
+	.Adc2DataDb0P_i		(1'b1),
+    .Adc2DataDb0N_i		(1'b0),		
+    .Adc2DataDb1P_i		(1'b1),
+    .Adc2DataDb1N_i		(1'b0),
+//------------------------------------------
+	.AdcInitMosi_o		(),
+	.AdcInitClk_o		(),			
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	.AdcInitRst_o		(),
+//------------------------------------------	
+	
+	.Mosi_i				(mosi_i),
+	.Sck_i				(~sck_i),
+	.Ss_i				(ss_i),
+		
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeas_i		(startCalcCmdReg),
+	.StartMeas_o		(),
+	.EndMeas_o			(endMeas),
+	.TimersClk_o		(),
+	
+	.Trig0_io			(trig0R),		//Trigger0 from/to external device
+	.Trig0Dir_o			(),		//Trigger0 direction 
+	
+	.Trig1_io			(trig1R),		//Trigger0 from/to external device	
+	.Trig1Dir_o			(),				//Trigger0 direction 
+	
+	.TrigFromDsp_i		(),				//Trig from DSP
+	.TrigToDsp_o		(),				//Trig To DSP
+	
+	.OverloadS_i		(1'b0),
+	.Overload_o			(),
+	
+	//mod out line
+	
+	.Mod_o				(),	
+	
+	//gain lines
+	.SensEnS_i			(1'b0),
+	.AmpEn_o			(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i			(adcWind)
+);
+
+parameter	IDLE	=	2'h0;
+parameter	CMD		=	2'h1;
+parameter	TX		=	2'h2;
+parameter	PAUSE	=	2'h3;
+
+reg	[1:0]	txCurrState;
+reg	[1:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+wire	txStop	=	cmdCnt	>=	62;
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmd;
+		end	else	if	(cmdCnt	==	1)	begin
+			DspSpiData		<=	IfFtwH;
+		end	else	if	(cmdCnt	==	2)	begin
+			DspSpiData		<=	IfFtwL;
+		end	else	if	(cmdCnt	==	3)	begin
+			DspSpiData		<=	RefSeqPerMNumRegCmd;
+		end else	if	(cmdCnt	==	4)	begin
+			DspSpiData		<=	PG12ModeRegCmd;
+		end	else	if	(cmdCnt	==	5)	begin
+			DspSpiData		<=	PG34GModeRegCmd;
+		end	else	if	(cmdCnt	==	6)	begin
+			DspSpiData		<=	GGPnumRegCmd;	
+		end	else	if	(cmdCnt	==	7)	begin
+			DspSpiData		<=	PG1P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	8)	begin
+			DspSpiData		<=	PG1P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	9)	begin
+			DspSpiData		<=	PG1P3DelayRegCmd;
+		end	else	if	(cmdCnt	==	10)	begin
+			DspSpiData		<=	PG1P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	11)	begin
+			DspSpiData		<=	PG1P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	12)	begin
+			DspSpiData		<=	PG1P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	13)	begin
+			DspSpiData		<=	PG1P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	14)	begin
+			DspSpiData		<=	PG1P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	15)	begin
+			DspSpiData		<=	PG2P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	16)	begin
+			DspSpiData		<=	PG2P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	17)	begin
+			DspSpiData		<=	PG2P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	18)	begin
+			DspSpiData		<=	PG2P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	19)	begin
+			DspSpiData		<=	PG2P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	20)	begin
+			DspSpiData		<=	PG2P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	21)	begin
+			DspSpiData		<=	PG2P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	22)	begin
+			DspSpiData		<=	PG2P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	23)	begin
+			DspSpiData		<=	PG3P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	24)	begin
+			DspSpiData		<=	PG3P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	25)	begin
+			DspSpiData		<=	PG3P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	26)	begin
+			DspSpiData		<=	PG3P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	27)	begin
+			DspSpiData		<=	PG3P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	28)	begin
+			DspSpiData		<=	PG3P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	29)	begin
+			DspSpiData		<=	PG3P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	30)	begin
+			DspSpiData		<=	PG3P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	31)	begin
+			DspSpiData		<=	PG4P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	32)	begin
+			DspSpiData		<=	PG4P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	33)	begin
+			DspSpiData		<=	PG4P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	34)	begin
+			DspSpiData		<=	PG4P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	35)	begin
+			DspSpiData		<=	PG4P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	36)	begin
+			DspSpiData		<=	PG4P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	37)	begin
+			DspSpiData		<=	PG4P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	38)	begin
+			DspSpiData		<=	PG4P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	39)	begin
+			DspSpiData		<=	PG1PNumRegCmd;
+		end	else	if	(cmdCnt	==	40)	begin
+			DspSpiData		<=	PG2PNumRegCmd;
+		end	else	if	(cmdCnt	==	41)	begin
+			DspSpiData		<=	PG3PNumRegCmd;
+		end	else	if	(cmdCnt	==	42)	begin
+			DspSpiData		<=	PG4PNumRegCmd;
+		end	else	if	(cmdCnt	==	43)	begin
+			DspSpiData		<=	PG12PNumRegCmd;
+		end	else	if	(cmdCnt	==	44)	begin
+			DspSpiData		<=	PG34GPNumRegCmd;
+		end	else	if	(cmdCnt	==	45)	begin
+			DspSpiData		<=	GGP1DelayRegCmd;
+		end	else	if	(cmdCnt	==	46)	begin
+			DspSpiData		<=	GGP2DelayRegCmd;
+		end	else	if	(cmdCnt	==	47)	begin
+			DspSpiData		<=	GGP3DelayRegCmd;
+		end	else	if	(cmdCnt	==	48)	begin
+			DspSpiData		<=	GGP123DelayRegCmd;
+		end	else	if	(cmdCnt	==	49)	begin
+			DspSpiData		<=	GGP1WidthRegCmd;
+		end	else	if	(cmdCnt	==	50)	begin
+			DspSpiData		<=	GGP2WidthRegCmd;
+		end	else	if	(cmdCnt	==	51)	begin
+			DspSpiData		<=	GGP3WidthRegCmd;
+		end	else	if	(cmdCnt	==	52)	begin
+			DspSpiData		<=	GGP123WidthRegCmd;
+		end	else	if	(cmdCnt	==	53)	begin
+			DspSpiData		<=	SSGP1DelayRegCmd;
+		end	else	if	(cmdCnt	==	54)	begin
+			DspSpiData		<=	SSGP2DelayRegCmd;
+		end	else	if	(cmdCnt	==	55)	begin
+			DspSpiData		<=	SSGP12DelNumRegCmd;
+		end	else	if	(cmdCnt	==	56)	begin
+			DspSpiData		<=	SSGPNumRegCmd;
+		end	else	if	(cmdCnt	==	57)	begin
+			DspSpiData		<=	RefSeqPerRegCmd;
+		end	else	if	(cmdCnt	==	58)	begin
+			DspSpiData		<=	MeasNumRegCmd;
+		end else	if	(cmdCnt	==	59)	begin
+			DspSpiData		<=	PulseMeasCtrlCmd;
+		end	else	if	(cmdCnt	==	60)	begin
+			DspSpiData		<=	FilterCorrCmdH;
+		end else	if	(cmdCnt	==	61)	begin
+			DspSpiData		<=	FilterCorrCmdL;
+		end
+	end	else	if	(txCurrState	==	TX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi_i	<=	DspSpiData[31];
+		end	else	begin
+			mosi_i	<=	1'b1;
+		end
+	end	else	begin
+		mosi_i	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		ss_i	<=	1'b0;
+	end	else	begin
+		ss_i	<=	1'b1;
+	end
+end
+
+assign	sck_i	=	Clk41;
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						txNextState = TX;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PgenDecription.txt

@@ -0,0 +1,54 @@
+Чтобы попасть в режим "Точка в импульсе" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1 импульс", значения задержки и длительности импульса.
+2. Колличество измерений установить = 1.
+3. Колличество импульсов SampleStrobeGen  установить = 1.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+
+
+Чтобы попасть в режим "Профиль импульса с конфигурируемым колличеством импульсов" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1 импульс", значения задержки и длительности импульса.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+Чтобы попасть в режим "Профиль импульса с шаблонами" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1,2 или 3 импульса", значения задержки и длительности импульсов.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+Чтобы попасть в режим "От импульса к импульсу" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "Burst", значения задержки и длительности импульса.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/ActivePortSelector.v

@@ -0,0 +1,152 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	ActivePortSelector	
+#(	
+	parameter	PortsNum	=	4
+)
+(
+	input	Rst_i,
+	
+	input	Mod_i,
+	input	[PortsNum-1:0]	Ctrl_i,
+	
+	output	reg	[PortsNum-1:0]	Ctrl_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	LutNum		=	2**PortsNum;
+	localparam	PortsNone	=	4'b0000;
+	localparam	Ports_1		=	4'b0001;
+	localparam	Ports_2		=	4'b0010;
+	localparam	Ports_21	=	4'b0011;
+	localparam	Ports_3		=	4'b0100;
+	localparam	Ports_31	=	4'b0101;
+	localparam	Ports_32	=	4'b0110;
+	localparam	Ports_321	=	4'b0111;
+	localparam	Ports_4		=	4'b1000;
+	localparam	Ports_41	=	4'b1001;
+	localparam	Ports_42	=	4'b1010;
+	localparam	Ports_421	=	4'b1011;
+	localparam	Ports_43	=	4'b1100;
+	localparam	Ports_431	=	4'b1101;
+	localparam	Ports_432	=	4'b1110;
+	localparam	Ports_4321	=	4'b1111;
+	
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire		[PortsNum-1:0]	Lut	[LutNum-1:0];
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Lut	[0]		=	~(4'b0000);
+	assign	Lut	[1]		=	~({3'b000,Mod_i});
+	assign	Lut	[2]		=	~({2'b00,Mod_i,1'b0});
+	assign	Lut	[3]		=	~({2'b00,Mod_i,Mod_i});
+	assign	Lut	[4]		=	~({1'b0,Mod_i,2'b0});
+	assign	Lut	[5]		=	~({1'b0,Mod_i,1'b0,Mod_i});
+	assign	Lut	[6]		=	~({1'b0,Mod_i,Mod_i,1'b0});
+	assign	Lut	[7]		=	~({1'b0,Mod_i,Mod_i,Mod_i});
+	assign	Lut	[8]		=	~({Mod_i,3'b000});
+	assign	Lut	[9]		=	~({Mod_i,2'b00,Mod_i});
+	assign	Lut	[10]	=	~({Mod_i,1'b0,Mod_i,1'd0});
+	assign	Lut	[11]	=	~({Mod_i,1'b0,Mod_i,Mod_i});
+	assign	Lut	[12]	=	~({Mod_i,Mod_i,2'b00});
+	assign	Lut	[13]	=	~({Mod_i,Mod_i,1'b0,Mod_i});
+	assign	Lut	[14]	=	~({Mod_i,Mod_i,Mod_i,1'b0});
+	assign	Lut	[15]	=	~({Mod_i,Mod_i,Mod_i,Mod_i});
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case	(Ctrl_i)
+			PortsNone:	begin
+							Ctrl_o	=	Lut[0];
+						end
+			Ports_1:	begin
+							Ctrl_o	=	Lut[1];
+						end	
+			Ports_2:	begin
+							Ctrl_o	=	Lut[2];
+						end
+			Ports_21:	begin
+							Ctrl_o	=	Lut[3];
+						end	
+			Ports_3:	begin
+							Ctrl_o	=	Lut[4];
+						end		
+			Ports_31:	begin
+							Ctrl_o	=	Lut[5];
+						end	
+			Ports_32:	begin
+							Ctrl_o	=	Lut[6];
+						end	
+			Ports_321:	begin
+							Ctrl_o	=	Lut[7];
+						end
+			Ports_4:	begin
+							Ctrl_o	=	Lut[8];
+						end		
+			Ports_41:	begin
+							Ctrl_o	=	Lut[9];
+						end	
+			Ports_42:	begin
+							Ctrl_o	=	Lut[10];
+						end	
+			Ports_421:	begin
+							Ctrl_o	=	Lut[11];
+						end
+			Ports_43:	begin
+							Ctrl_o	=	Lut[12];
+						end	
+			Ports_431:	begin
+							Ctrl_o	=	Lut[13];
+						end
+			Ports_432:	begin
+							Ctrl_o	=	Lut[14];
+						end
+			Ports_4321:	begin
+							Ctrl_o	=	Lut[15];
+						end
+		endcase
+	end	else	begin
+		Ctrl_o	=	4'd0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/MeasStartEventGen.v

@@ -0,0 +1,109 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//commands:
+//	ExtTrigUsage: 0 - no, 1 - yes.
+//
+//
+//
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MeasStartEventGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	MeasTrig_i,
+	input	StartMeasDsp_i,
+	
+	output	StartMeasEvent_o,
+	output	InitTrig_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+	reg		startMeasEvent;
+	reg		initTrig;
+	
+	reg		measTrigReg;
+	wire	measTrigPos;
+//================================================================================
+//  ASSIGNMENTS
+	assign	measTrigPos			=	(!measTrigReg&MeasTrig_i);
+	assign	StartMeasEvent_o	=	startMeasEvent;
+	assign	InitTrig_o			=	initTrig;
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measTrigReg	<=	MeasTrig_i;
+		end	else	begin
+			measTrigReg	=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(measTrigPos)	begin
+					startMeasEvent	=	1'b1;
+				end
+			end	else	begin
+				startMeasEvent	=	0;
+			end
+		end	else	begin
+			startMeasEvent	=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(measTrigPos)	begin
+					initTrig	=	1'b1;
+				end	else	begin
+					initTrig	=	1'b0;
+				end	
+			end	else	begin
+				initTrig	=	0;
+			end
+		end	else	begin
+			initTrig	=	0;
+		end
+	end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/ModOutMux.v

@@ -0,0 +1,88 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	ModOutMux	
+#(	
+	parameter	CmdDataRegWith	=	24,
+	parameter	PGenNum			=	4
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	[CmdDataRegWith-1:0]	PMeasCtrl_i,
+	
+	input	[PGenNum-1:0]	Pulses_i,
+	input	Trig0_i,	
+	input	Trig1_i,	
+	
+	output	Mod_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	
+	reg	modOut;
+	
+	wire	pulseMeasEn	=	PMeasCtrl_i[0];
+	wire	intExtSel	=	PMeasCtrl_i[4];
+	wire	extPortSel	=	PMeasCtrl_i[5];
+	wire	[PGenNum-1:0]	pGenSel	=	PMeasCtrl_i[11:8];
+//================================================================================
+//  ASSIGNMENTS
+	assign	Mod_o	=	modOut;
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(pulseMeasEn)	begin
+			if	(intExtSel)	begin
+				if	(extPortSel)	begin
+					modOut	<=	Trig1_i;
+				end	else	begin
+					modOut	<=	Trig0_i;
+				end
+			end	else	begin
+				modOut	<=	Pulses_i[pGenSel];
+			end
+		end	else	begin
+			modOut	<=	1'b0;
+		end
+	end	else	begin
+		modOut	<=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/Mux.v

@@ -0,0 +1,75 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	Mux	
+#(	
+	parameter	CmdRegWidth		=	24,
+	parameter	PGenNum			=	7,
+	parameter	TrigPortsNum	=	6
+)
+(
+	input	Rst_i,
+	
+	input	[CmdRegWidth-28:0]	MuxCtrl_i,
+	
+	input	DspTrigOut_i,
+	input	DspStartCmd_i,
+	input	IntTrig_i,
+	input	IntTrig2_i,
+	input	[PGenNum-1:0]		PulseBus_i,
+	input	[TrigPortsNum-1:0]	ExtPortsBus_i,
+	
+	output	MuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg		muxOut;
+	wire	[PGenNum+TrigPortsNum+5:0]	inputBus	=	{IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
+//================================================================================
+//  ASSIGNMENTS
+	assign	MuxOut_o	=	muxOut;
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		muxOut	=	inputBus[MuxCtrl_i];
+	end	else	begin
+		muxOut	=	1'b0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/MuxTb.v

@@ -0,0 +1,77 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MuxTb();	
+
+//================================================================================
+//	PARAMETERS
+
+//================================================================================
+//  REG/WIRE
+	reg		Clk50;	
+	reg		Rst;	
+
+//================================================================================
+//  ASSIGNMENTS
+
+//================================================================================
+//  CODING
+
+	always	#10 Clk50	=	~Clk50;
+
+	initial begin
+		Clk50	=	1'b1;
+		Rst		=	1'b1;
+		#50
+		Rst		=	1'b0;
+	end	
+
+
+Mux	
+#(	
+	.CmdDataRegWith	(24),
+	.PGenNum		(7),
+	.TrigPortsNum	(6),
+	.Source			("MIXED")
+)
+MuxInst
+(
+	.Rst_i			(Rst),
+
+	.MuxCtrl_i		(4),
+
+	.IntTrig_i		(1'b1),
+	.PulseBus_i		(7'd6),
+	.ExtPortsBus_i	(6'd5),
+	
+	.MuxOut_o		()
+);	
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/PGenRstGenerator.v

@@ -0,0 +1,117 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PGenRstGenerator	
+#(	
+	parameter	PgenNum	=	7
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	[PgenNum-1:0]	PGenRst_i,
+	
+	output	reg	[PgenNum-1:0]	PGenRst_o,
+	output	reg	RstDone_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	IDLE	=	2'h0;
+	localparam	RST		=	2'h1;
+	localparam	DEL		=	2'h2;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[1:0]	currState;
+	
+	reg	[PgenNum-1:0]	pGenRstReg;
+	
+	wire	orPGenRstReg	=	|pGenRstReg;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+//================================================================================
+//  CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		pGenRstReg		<=	PGenRst_i;
+	end	else	begin
+		pGenRstReg		<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(currState)
+		IDLE	:	begin
+						if (orPGenRstReg)	begin
+							currState 	<= RST;
+							PGenRst_o	<=	pGenRstReg;
+							RstDone_o	<=	1'b1;
+						end	else begin
+							currState <= IDLE;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		RST	:		begin
+						if	(RstDone_o)	begin
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+							currState 	<= DEL;
+						end	else begin
+							currState 	<= RST;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		DEL	:		begin
+						PGenRst_o	<=	0;
+						RstDone_o	<=	0;
+						currState 	<= IDLE;
+					end
+		endcase
+	end	else	begin
+		currState	<=	IDLE;
+		PGenRst_o	<=	0;
+		RstDone_o	<=	0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/PulseEventGen.v

@@ -0,0 +1,61 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MeasStartEventGen	
+#(	
+	parameter	CmdDataRegWith	=	24
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	MeasModeReg_i,
+	input	PriRegH_i,
+	input	PriRegL_i,
+	
+	output	StartPulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+	reg	startPulse;
+	
+//================================================================================
+//  ASSIGNMENTS
+	assign	StartPulse_o	=	startPulse;
+//================================================================================
+//  CODING
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

S5443_M/S5443.srcs/sources_1/new/PulseMeas/PulseGen.v

@@ -0,0 +1,314 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	wire	zeroDelay	=	(P1Del_i==0);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	<=	0;
+				currWidthValue	<=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	<=	delArray[pulseCnt];
+				currWidthValue	<=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(currState	==	IDLE)	begin
+						currDelValue	<=	delArray[0];
+						currWidthValue	<=	widthArray[0];
+					end	else	if	(currState	==	PULSE	&	pulseDone)	begin
+						currDelValue	<=	delArray[1];
+						currWidthValue	<=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	<=	0;
+		currWidthValue	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		end	else	begin
+			patternDone	=	0;
+		end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							nextState = PULSE;
+						end	else begin
+							nextState = DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							pulse	=	1'b0;
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+