Убран сброс NCO при изменении FTW.

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Thu Jul 13 15:41:50 2023
+// Date        : Tue Aug 29 17:27:14 2023
 // Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
-//               MeasDataFifo_ MeasDataFifo_stub.v
+// Command     : write_verilog -force -mode synth_stub
+//               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga324-2

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Tue Aug 29 17:27:14 2023
 -- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga324-2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -96,7 +96,7 @@ map_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/activehdl"
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/activehdl"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -98,7 +98,7 @@ copy_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/modelsim"
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/modelsim"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -105,7 +105,7 @@ copy_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/questa"
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/questa"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -96,7 +96,7 @@ map_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/riviera"
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/riviera"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
+# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
+# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci

@@ -554,10 +554,6 @@
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
             <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Dout_Reset_Value" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Safety_Circuit" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
@@ -565,9 +561,6 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Pin" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Dout_Reset" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
           </xilinx:configElementInfos>
           <xilinx:boundaryDescriptionInfo>

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_clocks.xdc

@@ -1,69 +0,0 @@
-################################################################################
-# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-################################################################################
-#------------------------------------------------------------------------------#
-#                         Native FIFO Constraints                              #
-#------------------------------------------------------------------------------#
-
-#set wr_clock          [get_clocks -of_objects [get_ports wr_clk]]
-#set rd_clock          [get_clocks -of_objects [get_ports rd_clk]]
-#set wr_clk_period     [get_property PERIOD $wr_clock]
-#set rd_clk_period     [get_property PERIOD $rd_clock]
-#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
-
-
-# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
-
-## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
-## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
-
-## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
-## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
-#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
-#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
-################################################################################

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Thu Jul 13 15:41:50 2023
+// Date        : Tue Aug 29 17:27:14 2023
 // Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
-//               MeasDataFifo_ MeasDataFifo_stub.v
+// Command     : write_verilog -force -mode synth_stub
+//               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Tue Aug 29 17:27:14 2023
 -- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/new/InternalDsp/CordicNco.v

@@ -112,9 +112,12 @@ end
 //  Phase handle logic
 always @(posedge Clk_i) begin
     if (Rst_i) begin
-        phaseAcc   <= {PhIncWidth{1'b0}};
+        // phaseAcc   <= {PhIncWidth{1'b0}};
+        // phaseAcc   <= 32'h40000000;
+        phaseAcc   <= 32'h3fffffff;
     end else if (Val_i) begin
         phaseAcc   <= phaseAcc + PhaseInc_i;
+        // phaseAcc   <= phaseAcc + 0;
     end	else	begin
 		phaseAcc   <= {PhIncWidth{1'b0}};
 	end

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -292,12 +292,13 @@ CordicNco
 	.ODatWidth	(NcoWidth),
 	.PhIncWidth	(WindNcoPhIncWidth),
 	.IterNum	(15),
-	.EnSinN		(1)
+	.EnSinN		(0)
 )
 ncoFirstTone
 (
 	.Clk_i		(Clk_i),
-	.Rst_i		(Rst_i|NcoRst_i),
+	// .Rst_i		(Rst_i|NcoRst_i),
+	.Rst_i		(Rst_i),
 	.Val_i		(1'b1),
 	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
 	// .PhaseInc_i	(32'h40000000),
@@ -315,12 +316,13 @@ CordicNco
 	.ODatWidth	(NcoWidth),
 	.PhIncWidth	(WindNcoPhIncWidth),
 	.IterNum	(15),
-	.EnSinN		(1)
+	.EnSinN		(0)
 )
 ncoSecondTone
 (
 	.Clk_i		(Clk_i),
-	.Rst_i		(Rst_i|NcoRst_i),
+	// .Rst_i		(Rst_i|NcoRst_i),
+	.Rst_i		(Rst_i),
 	.Val_i		(1'b1),
 	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
 	// .PhaseInc_i	(32'h31eb851e),