Правки проекта для повышения стабильности.

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Wed May  3 12:25:17 2023
-// Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
+// Date        : Thu Jul 13 15:41:50 2023
+// Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
+//               MeasDataFifo_ MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga324-2

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Thu Jul 13 15:41:50 2023
+-- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
+--               MeasDataFifo_ MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Wed May  3 12:25:17 2023
-// Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
+// Date        : Thu Jul 13 15:41:50 2023
+// Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
+//               MeasDataFifo_ MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Thu Jul 13 15:41:50 2023
+-- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
+--               MeasDataFifo_ MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(6),
+      	.CLKOUT2_DIVIDE		(8),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -229,33 +229,33 @@ DecimFilterWrapper	DecimFilter
 	.FilteredDataVal_o	(filteredDecimDataVal)
 );
 
-// FftDataFormer	FftDataFormerInst
-// (
-	// .Clk_i				(Clk_i), 
-	// .Rst_i				(Rst_i),	
-	// .OscWind_i			(OscWind_i),
-	// .MeasNum_i			(MeasNum_i),
-	
-	// .AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+FftDataFormer	FftDataFormerInst
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i),	
+	.OscWind_i			(OscWind_i),
+	.MeasNum_i			(MeasNum_i),
+	
+	.AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
 	// .AdcData_i			({testPatternData,testPatternData}),
-	// .AdcDataVal_i		(filteredDecimDataVal),
+	.AdcDataVal_i		(filteredDecimDataVal),
 	
-	// .OscDataBus_o		(fftDataBus),
-	// .OscDataBusVal_o	(fftDataBusVal)
-// );
+	.OscDataBus_o		(fftDataBus),
+	.OscDataBusVal_o	(fftDataBusVal)
+);
 
-// OscDataFormer	BypassDataFormer
-// (
-	// .Clk_i				(Clk_i), 
-	// .Rst_i				(Rst_i),	
-	// .OscWind_i			(OscWind_i),
-	// .MeasNum_i			(MeasNum_i),
-	
-	// .AdcData_i			(currDataChannel),	
-	
-	// .OscDataBus_o		(bypassDataBus),
-	// .OscDataBusVal_o	(bypassDataBusVal)
-// );
+OscDataFormer	BypassDataFormer
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i),	
+	.OscWind_i			(OscWind_i),
+	.MeasNum_i			(MeasNum_i),
+	
+	.AdcData_i			(currDataChannel),	
+	
+	.OscDataBus_o		(bypassDataBus),
+	.OscDataBusVal_o	(bypassDataBusVal)
+);
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
@@ -290,10 +290,10 @@ MeasDataFifoInst
 	.MeasNum_i		(MeasNum_i),	
 	.StartMeasDsp_i	(StartMeasDsp_i),	
 	.DspReadyForRx_i(DspReadyForRx_i),	
-	.MeasDataBus_i	(measDataBus),
-	// .MeasDataBus_i	(dataForFifo),
-	.MeasDataVal_i	(LpOutStart_i),	
-	// .MeasDataVal_i	(dataForFifoVal),	
+	// .MeasDataBus_i	(measDataBus),
+	.MeasDataBus_i	(dataForFifo),
+	// .MeasDataVal_i	(LpOutStart_i),	
+	.MeasDataVal_i	(dataForFifoVal),	
 	
 	.MeasDataBus_o	(measDataBusTx),
 	.MeasDataVal_o	(measDataValTx)

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -29,13 +29,14 @@ module Win_calc	(
 	input	[1:0]	TukeyCtrl_i,
 	input	[31:0]	win_value_i,
 	input	[2:0]	win_type_i,	
-	output	signed [17:0]	win_o
+	output	signed [17:0]	win_o,
+	output	reg	signed [17:0]	sinWin_o
 );
 //================================================================================
 //  REG/WIRE
 //================================================================================
 	
-	reg			[3:0]	calc_cycle;
+	reg			[2:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -52,7 +53,6 @@ module Win_calc	(
 	reg	[35:0]	sinWindPow2;
 	
 	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
-	// wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70)|filterCmd_i==8'h30;
 	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
 	
 	wire	[17:0]	bSin	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
@@ -68,6 +68,18 @@ module Win_calc	(
 	
 	wire	signed [17:0]	windMux1;
 	wire	signed [17:0]	windMux2;
+	
+	
+	wire	[18*2-1:0]	b2	=	bCurr**2;
+	wire	[18*3-1:0]	b3	=	bCurr**3;
+	wire	[18*4-1:0]	b4	=	bCurr**4;
+	wire	[18*5-1:0]	b5	=	bCurr**5;
+	
+	
+	wire	[17:0]	b2Cut	=	b2[18*2-1-:18];
+	wire	[17:0]	b3Cut	=	b3[18*3-1-:18];
+	wire	[17:0]	b4Cut	=	b4[18*4-1-:18];
+	wire	[17:0]	b5Cut	=	b5[18*5-1-:18];	
 //================================================================================
 //  PARAMETERS
 //================================================================================
@@ -136,36 +148,30 @@ always	@(*)	begin
 	end
 end
 
-always	@(negedge	wind_clk)	begin
+always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				4'd1: 	
+				3'd0: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
+							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				4'd2:	
+				3'd1:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				4'd3:	
+				3'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
-		// end	else	begin
-			// a1	<=	18'b0;
-			// c1	<=	18'b0;
-			// c2	<=	18'b0;
-			// b	<=	18'b0;
-		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -173,33 +179,6 @@ always	@(negedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
-
-// always	@(*)	begin
-	// if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
-			// case	(calc_cycle)
-				// 3'd1: 	
-						// begin
-							// a1	=	A5;
-							// c1	=	A4;
-							// c2	=	A3;
-							// b	=	bCurr;
-						// end
-			// endcase
-		// end	else	begin
-			// a1	=	18'b0;
-			// c1	=	18'b0;
-			// c2	=	18'b0;
-			// b	=	18'b0;
-		// end
-	// end	else	begin
-		// a1	=	18'b0;
-		// c1	=	18'b0;
-		// c2	=	18'b0;
-		// b	=	18'b0;
-	// end
-// end
-
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -242,17 +221,13 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		if	(MeasWind_i)	begin
-			if	(calc_cycle	!=	4'd3)	begin
-				calc_cycle	<=	calc_cycle	+	4'd1;
+			if	(calc_cycle	!=	3'd2)	begin
+				calc_cycle	<=	calc_cycle	+	3'd1;
 			end	else	begin
-				calc_cycle	<=	4'd0;
+				calc_cycle	<=	3'd0;
 			end
-		end	else	begin
-			calc_cycle	<=	4'd0;
-		end
 	end	else	begin
-		calc_cycle	<=	4'd0;
+		calc_cycle	<=	3'd0;
 	end
 end
 
@@ -284,9 +259,9 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
-FirstStage (
+DSP48E1_1inst (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -310,8 +285,8 @@ FirstStage (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      // .CLK(1'b0),                       // 1-bit input: Clock input
-      .CLK(wind_clk),                       // 1-bit input: Clock input
+      .CLK(1'b0),                       // 1-bit input: Clock input
+      // .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -332,7 +307,7 @@ FirstStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -342,8 +317,8 @@ FirstStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -376,7 +351,7 @@ DSP48E1 #(
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
       .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
-SecondStage (
+DSP48E1_2inst (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -422,8 +397,8 @@ SecondStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -432,8 +407,8 @@ SecondStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule

S5443_M/S5443.srcs/sources_1/new/S5243Top.v

@@ -165,8 +165,8 @@ module	S5243Top
 	wire	gatingPulse;
 	wire	sampleStrobe;
 	wire	[ChNum-1:0]	measStartBus;
-	// wire	measStart	=	&measStartBus;
-	reg		measStart;
+	wire	measStart;
+	// reg		measStart;
 	
 	//spi signals for adc init
 	wire	adcInitRst;
@@ -1010,60 +1010,18 @@ generate
 	end
 endgenerate
 
-always	@(*)	begin
-	if	(!initRst)	begin
-		case(gainAutoEn)
-			4'd0:	begin
-						measStart	=	&measStartBus;
-					end
-			4'd1:	begin
-						measStart	=	measStartBus[0];
-					end
-			4'd2:	begin
-						measStart	=	measStartBus[1];
-					end
-			4'd3:	begin
-						measStart	=	measStartBus[0]&measStartBus[1];
-					end
-			4'd4:	begin
-						measStart	=	&measStartBus[2];
-					end
-			4'd5:	begin
-						measStart	=	measStartBus[0]&measStartBus[2];
-					end
-			4'd6:	begin
-						measStart	=	measStartBus[1]&measStartBus[2];
-					end
-			4'd7:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[2];
-					end
-			4'd8:	begin
-						measStart	=	measStartBus[3];
-					end
-			4'd9:	begin
-						measStart	=	measStartBus[0]&measStartBus[3];
-					end
-			4'd10:	begin
-						measStart	=	measStartBus[1]&measStartBus[3];
-					end
-			4'd11:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[3];
-					end
-			4'd12:	begin
-						measStart	=	measStartBus[2]&measStartBus[3];
-					end
-			4'd13:	begin
-						measStart	=	measStartBus[0]&measStartBus[2]&measStartBus[3];
-					end
-			4'd14:	begin
-						measStart	=	measStartBus[1]&measStartBus[2]&measStartBus[3];
-					end
-			4'd15:	begin
-						measStart	=	&measStartBus;
-					end		
-		endcase
-	end
-end
+StartAfterGainSel	
+#(	
+	.ChNum	(ChNum)
+)	
+StartAfterGainSelInst
+(
+	.Rst_i			(initRst),
+	.GainCtrl_i		(gainAutoEn),
+	.MeasStart_i	(measStartBus),
+	
+	.MeasStart_o	(measStart)
+);
 //--------------------------------------------------------------------------------
 //	Trig TO/FROM DSP	
 //--------------------------------------------------------------------------------