Изменение алгоритма расчета оконной функции.

S5443_M/S5443.srcs/constrs_1/new/S5243Top.xdc

@@ -302,6 +302,9 @@ connect_debug_port u_ila_0/probe3 [get_nets [list {InternalDsp/DspChannel[0].Adc
 
 
 
+
+
+
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
 set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
@@ -313,9 +316,13 @@ set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
 set_property port_width 1 [get_debug_ports u_ila_0/clk]
 connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
 set_property port_width 18 [get_debug_ports u_ila_0/probe0]
 connect_debug_port u_ila_0/probe0 [get_nets [list {InternalDsp/wind[0]} {InternalDsp/wind[1]} {InternalDsp/wind[2]} {InternalDsp/wind[3]} {InternalDsp/wind[4]} {InternalDsp/wind[5]} {InternalDsp/wind[6]} {InternalDsp/wind[7]} {InternalDsp/wind[8]} {InternalDsp/wind[9]} {InternalDsp/wind[10]} {InternalDsp/wind[11]} {InternalDsp/wind[12]} {InternalDsp/wind[13]} {InternalDsp/wind[14]} {InternalDsp/wind[15]} {InternalDsp/wind[16]} {InternalDsp/wind[17]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list InternalDsp/MeasWind_o]]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -47,8 +47,8 @@ module	DspInterface
 	input	[CmdWidth-2:0]		PortSel_i,
 	input	[CmdWidth-1:0]		DecimFactor_i,
 	
-	input	[CmdRegWidth-1:0]	IfFtwL_i,
-	input	[CmdRegWidth-1:0]   IfFtwH_i,
+	input	[CmdRegWidth-9:0]	IfFtwL_i,
+	input	[CmdRegWidth-9:0]   IfFtwH_i,
 	
 	output	OscDataRdFlag_o,
 	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	
@@ -74,15 +74,15 @@ module	DspInterface
 	output	LpOutClk_o,
 	output	[ODataWidth-1:0]	LpOutData_o,
 	
-	input	[ResultWidth-1:0]	Adc1T1ImResult_i,
-	input	[ResultWidth-1:0]	Adc1T1ReResult_i,
-	input	[ResultWidth-1:0]	Adc1R1ImResult_i,
-	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	
+	input	[ResultWidth-1:0]	Adc1T1ImResult_i,	//T1_FIRST_IM
+	input	[ResultWidth-1:0]	Adc1T1ReResult_i,	//T1_FIRST_RE
+	input	[ResultWidth-1:0]	Adc1R1ImResult_i,	//T2_FIRST_IM
+	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	//T2_FIRST_RE
 	
-	input	[ResultWidth-1:0]	Adc2R2ImResult_i,
-	input	[ResultWidth-1:0]	Adc2R2ReResult_i,
-	input	[ResultWidth-1:0]	Adc2T2ImResult_i,
-	input	[ResultWidth-1:0]	Adc2T2ReResult_i,
+	input	[ResultWidth-1:0]	Adc2R2ImResult_i,	//T2_SECOND_IM
+	input	[ResultWidth-1:0]	Adc2R2ReResult_i,	//T2_SECOND_RE
+	input	[ResultWidth-1:0]	Adc2T2ImResult_i,	//T1_SECOND_IM
+	input	[ResultWidth-1:0]	Adc2T2ReResult_i,	//T1_SECOND_RE
 	input	[ChNum-1:0]			ServiseRegData_i,
 
 	input	LpOutStart_i
@@ -211,71 +211,71 @@ DspSlaveSpi
 	.Miso_o		(Miso_o)
 );
 
-DecimFilterWrapper	DecimFilter
-(
-	.Clk_i			(Clk_i),
-	.Rst_i			(Rst_i),
-	.OscWind_i		(OscWind_i),
-	.DecimFactor_i	(DecimFactor_i),
+// DecimFilterWrapper	DecimFilter
+// (
+	// .Clk_i			(Clk_i),
+	// .Rst_i			(Rst_i),
+	// .OscWind_i		(OscWind_i),
+	// .DecimFactor_i	(DecimFactor_i),
 	
-	.IfFtwL_i		(IfFtwL_i),
-	.IfFtwH_i		(IfFtwH_i),
+	// .IfFtwL_i		(IfFtwL_i),
+	// .IfFtwH_i		(IfFtwH_i),
 	
-	.AdcData_i		(currDataChannel),
+	// .AdcData_i		(currDataChannel),
 	// .TestData_o		(testData),
 	
-	.FilteredAdcDataI_o	(filteredDecimDataI),
-	.FilteredAdcDataQ_o	(filteredDecimDataQ),
-	.FilteredDataVal_o	(filteredDecimDataVal)
-);
+	// .FilteredAdcDataI_o	(filteredDecimDataI),
+	// .FilteredAdcDataQ_o	(filteredDecimDataQ),
+	// .FilteredDataVal_o	(filteredDecimDataVal)
+// );
 
-FftDataFormer	FftDataFormerInst
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+// FftDataFormer	FftDataFormerInst
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
 	// .AdcData_i			({testPatternData,testPatternData}),
-	.AdcDataVal_i		(filteredDecimDataVal),
+	// .AdcDataVal_i		(filteredDecimDataVal),
 	
-	.OscDataBus_o		(fftDataBus),
-	.OscDataBusVal_o	(fftDataBusVal)
-);
+	// .OscDataBus_o		(fftDataBus),
+	// .OscDataBusVal_o	(fftDataBusVal)
+// );
 
-OscDataFormer	BypassDataFormer
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			(currDataChannel),	
-	
-	.OscDataBus_o		(bypassDataBus),
-	.OscDataBusVal_o	(bypassDataBusVal)
-);
+// OscDataFormer	BypassDataFormer
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			(currDataChannel),	
+	
+	// .OscDataBus_o		(bypassDataBus),
+	// .OscDataBusVal_o	(bypassDataBusVal)
+// );
 
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(Mode_i)	begin
-			if	(DecimFactor_i	==	0)	begin
-				dataForFifo		<=	bypassDataBus;
-				dataForFifoVal	<=	bypassDataBusVal;
-			end	else	begin
-				dataForFifo		<=	fftDataBus;
-				dataForFifoVal	<=	fftDataBusVal;
-			end
-		end	else	begin
-			dataForFifo		<=	measDataBus;
-			dataForFifoVal	<=	LpOutStart_i;
-		end
-	end	else	begin
-		dataForFifo		<=	0;
-		dataForFifoVal	<=	0;
-	end
-end
+// always	@(posedge	Clk_i)	begin
+	// if	(!Rst_i)	begin
+		// if	(Mode_i)	begin
+			// if	(DecimFactor_i	==	0)	begin
+				// dataForFifo		<=	bypassDataBus;
+				// dataForFifoVal	<=	bypassDataBusVal;
+			// end	else	begin
+				// dataForFifo		<=	fftDataBus;
+				// dataForFifoVal	<=	fftDataBusVal;
+			// end
+		// end	else	begin
+			// dataForFifo		<=	measDataBus;
+			// dataForFifoVal	<=	LpOutStart_i;
+		// end
+	// end	else	begin
+		// dataForFifo		<=	0;
+		// dataForFifoVal	<=	0;
+	// end
+// end
 
 MeasDataFifoWrapper		
 #(	
@@ -290,10 +290,10 @@ MeasDataFifoInst
 	.MeasNum_i		(MeasNum_i),	
 	.StartMeasDsp_i	(StartMeasDsp_i),	
 	.DspReadyForRx_i(DspReadyForRx_i),	
-	// .MeasDataBus_i	(measDataBus),
-	.MeasDataBus_i	(dataForFifo),
-	// .MeasDataVal_i	(LpOutStart_i),	
-	.MeasDataVal_i	(dataForFifoVal),	
+	.MeasDataBus_i	(measDataBus),
+	// .MeasDataBus_i	(dataForFifo),
+	.MeasDataVal_i	(LpOutStart_i),	
+	// .MeasDataVal_i	(dataForFifoVal),	
 	
 	.MeasDataBus_o	(measDataBusTx),
 	.MeasDataVal_o	(measDataValTx)

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -32,18 +32,29 @@ module Win_calc	(
 	output	signed [17:0]	win_o,
 	output	reg	signed [17:0]	sinWin_o
 );
+
 //================================================================================
-//  REG/WIRE
+//  PARAMETERS
 //================================================================================
+	localparam	signed	A3_1	=	18'h15584;
+// ????????? ??? ?????????? SIN
+	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
+	localparam signed	[17:0]	A2	=	18'h002C0;			// b
+	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
+	localparam signed	[17:0]	A4	=	18'h0126C;			// d
+	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
 	
-	reg			[2:0]	calc_cycle;
-	reg	signed	[17:0]	a1;		
-	reg signed	[17:0]	b; 	
-	reg signed	[17:0]	c1;
-	reg signed	[17:0]	c2;	
-	wire 		[47:0]	p2;
-	wire 		[47:0]	p1;	
+	localparam	CalcWidth			=	10;
+	localparam	CalcWidthR			=	18;
+	localparam	b2Width				=	CalcWidth*2;
+	localparam	b3Width				=	CalcWidth*3;
+	localparam	b4Width				=	CalcWidth*4;
+	localparam	b5Width				=	CalcWidth*5;
 	
+	localparam [31:0]	testArg	=	32'h12492492;
+//================================================================================
+//  REG/WIRE
+//================================================================================
 	reg			signed	[17:0]	sinWind;
 	reg			signed	[17:0]	tukeyWind;	
 		
@@ -55,10 +66,9 @@ module Win_calc	(
 	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
 	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
 	
-	wire	[17:0]	bSin	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
-	wire	[17:0]	bTukey	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	wire	[CalcWidth-1:0]	bCurr	=	win_value_i[31]	?	10'h3FF	-	win_value_i[31-:CalcWidth]	:	win_value_i	[31-:CalcWidth];
 	
-	wire	[17:0]	bCurr	=	sinFilterFlag	?	bSin:bTukey;
+	wire	[CalcWidthR-1:0]	bNew	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 	
 	wire	signed	[17:0]	constOne	=	18'b011111111111111111;
 	
@@ -69,43 +79,61 @@ module Win_calc	(
 	wire	signed [17:0]	windMux1;
 	wire	signed [17:0]	windMux2;
 	
-	
-	wire	[18*2-1:0]	b2	=	bCurr**2;
-	wire	[18*3-1:0]	b3	=	bCurr**3;
-	wire	[18*4-1:0]	b4	=	bCurr**4;
-	wire	[18*5-1:0]	b5	=	bCurr**5;
-	
-	
-	wire	[17:0]	b2Cut	=	b2[18*2-1-:18];
-	wire	[17:0]	b3Cut	=	b3[18*3-1-:18];
-	wire	[17:0]	b4Cut	=	b4[18*4-1-:18];
-	wire	[17:0]	b5Cut	=	b5[18*5-1-:18];	
-//================================================================================
-//  PARAMETERS
-//================================================================================
-	localparam	signed	A3_1	=	18'h15584;
-// ????????? ??? ?????????? SIN
-	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
-	localparam signed	[17:0]	A2	=	18'h002C0;			// b
-	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
-	localparam signed	[17:0]	A4	=	18'h0126C;			// d
-	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
+	wire	signed	[b2Width-1:0]	b2	=	bCurr**2;
+	wire	signed	[b3Width-1:0]	b3	=	bCurr**3;
+	wire	signed	[b4Width-1:0]	b4	=	bCurr**4;
+	wire	signed	[b5Width-1:0]	b5	=	bCurr**5;
+	
+	wire	signed	[CalcWidthR-1:0]	b2Cut	=	b2[b2Width-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b3Cut	=	b3[b3Width-3-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b4Cut	=	b4[b4Width-4-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b5Cut	=	b5[b5Width-5-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR*2-1:0]	a1b;
+	reg		signed	[CalcWidthR*2-1:0]	a2b2;
+	reg		signed	[CalcWidthR*2-1:0]	a3b3;
+	reg		signed	[CalcWidthR*2-1:0]	a4b4;
+	reg		signed	[CalcWidthR*2-1:0]	a5b5;
+	
+	wire	signed	[CalcWidthR-1:0]	a1bCut	=	a1b	[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a2b2Cut	=	a2b2[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a3b3Cut	=	a3b3[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a4b4Cut	=	a4b4[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a5b5Cut	=	a5b5[CalcWidthR*2-2-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR-1:0]	bPrevSh;
+		
+	wire	signed	[CalcWidthR-1:0]	approxSin	=	a5b5Cut+a4b4Cut+a3b3Cut+a2b2Cut+a1bCut+bPrevSh;	
 	
 //================================================================================
 //  ASSIGNMENTS
 // ================================================================================	
-
-	// assign	win_o	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
-	
-	assign	win_o		=	windMux2;
 	
 	assign	windMux1	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
 	assign	windMux2	=	(rectFilterFlag)?	18'h1ffff:windMux1;
 
+	assign	win_o		=	windMux2;
 // ================================================================================
 //  CODING
 //================================================================================	
 
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		a5b5	<=	A5*b5Cut;
+		a4b4	<=	A4*b4Cut;
+		a3b3	<=	A3*b3Cut;
+		a2b2	<=	A2*b2Cut;
+		a1b		<=	A1*bNew;
+		bPrevSh	<=	bNew;
+	end	else	begin
+		a5b5	<=	0;
+		a4b4	<=	0;
+		a3b3	<=	0;
+		a2b2	<=	0;
+		a1b		<=	0;
+		bPrevSh	<=	0;
+	end
+end
 
 always	@(posedge	clk_i)	begin
 	if	(!reset_i)	begin
@@ -117,19 +145,19 @@ always	@(posedge	clk_i)	begin
 	end
 end
 
-always	@(posedge	clk_i)	begin
+always	@(*)	begin
 	if	(!reset_i)	begin
-		tukeyCorr	<=	(tukeyWind+constOne);
-		sinWindPow2	<=	sinWind**2;
+		tukeyCorr	=	(tukeyWind+constOne);
+		sinWindPow2	=	approxSin**2;
 	end	else	begin
-		tukeyCorr	<=	18'h0;
-		sinWindPow2	<=	18'h0;
+		tukeyCorr	=	18'h0;
+		sinWindPow2	=	18'h0;
 	end
 end
 
 always	@(*)	begin
 	if	(!reset_i)	begin
-		case(tukeyCtrlRR)
+		case(tukeyCtrlR)
 			2'h0:		begin
 							tukeyWindOut	=	0;
 						end
@@ -148,267 +176,20 @@ always	@(*)	begin
 	end
 end
 
-always	@(posedge	wind_clk)	begin
-	if	(!reset_i)	begin
-			case	(calc_cycle)
-				3'd0: 	
-						begin
-							a1	<=	A5;
-							c1	<=	A4;
-							c2	<=	A3;
-							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
-							b	<=	bCurr;
-						end
-						
-				3'd1:	
-						begin
-							a1	<=	p2[34:17];
-							c1	<=	A2;
-							c2	<=	A1;
-						end
-				3'd2:	
-						begin
-							a1	<=	p2[34:17];
-							c1	<=	b;
-						end
-			endcase
-	end	else	begin
-		a1	<=	18'b0;
-		c1	<=	18'b0;
-		c2	<=	18'b0;
-		b	<=	18'b0;
-	end
-end
-		
-always	@(posedge	wind_clk)	begin
-	if	(!reset_i)	begin
-		if	(!win_type_i)	begin 
-			if (calc_cycle	==	3'd0) begin
-				if	(p1[47:34]	==	0)	begin
-					sinWind	<=	p1[34-:18];//1.0.17	
-				end	else	begin
-					sinWind	<=	18'h1FFFF;
-				end
-				
-			end 
-		end	else	begin
-			sinWind		<=	18'h0;
-		end
-	end	else	begin
-		sinWind		<=	18'h0;
-	end
-end
 
-always	@(posedge	wind_clk)	begin
+always	@(*)	begin
 	if	(!reset_i)	begin
 		if	(!win_type_i)	begin 
-			if (calc_cycle	==	3'd0) begin
-				if	(!WinCtrl_i)	begin
-					tukeyWind	<=	p1[34-:18];
-				end	else	begin
-					tukeyWind	<=	0-p1[34-:18];
-				end
-			end 
-		end	else	begin
-			tukeyWind	<=	18'h0;
-		end
-	end	else	begin
-		tukeyWind	<=	18'h0;
-	end
-end
-
-//??????? "????? ??????? ????????". ????????  [(b*A5+A4) = p1 ? ????????????? ?????? (b*p1+A3)=p2] == 1 ????.
-
-always	@(posedge	wind_clk)	begin
-	if	(!reset_i)	begin
-			if	(calc_cycle	!=	3'd2)	begin
-				calc_cycle	<=	calc_cycle	+	3'd1;
+			if	(!WinCtrl_i)	begin
+				tukeyWind	=	approxSin;
 			end	else	begin
-				calc_cycle	<=	3'd0;
+				tukeyWind	=	0-approxSin;
 			end
+		end	else	begin
+			tukeyWind	=	18'h0;
+		end
 	end	else	begin
-		calc_cycle	<=	3'd0;
+		tukeyWind	=	18'h0;
 	end
 end
-
-DSP48E1 #(
-      // Feature Control Attributes: Data Path Selection
-      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
-      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
-      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
-      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
-      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
-      // Pattern Detector Attributes: Pattern Detection Configuration
-      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
-      .MASK(48'h3fffffffffff),          // 48-bit mask value for pattern detect (1=ignore)
-      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
-      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
-      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
-      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
-      // Register Control Attributes: Pipeline Register Configuration
-      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
-      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
-      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
-      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
-      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
-      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
-      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
-      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
-      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
-      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
-      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
-      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
-      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
-   )
-DSP48E1_1inst (
-      // Cascade: 30-bit (each) output: Cascade Ports
-      .ACOUT(),                   // 30-bit output: A port cascade output
-      .BCOUT(),                   // 18-bit output: B port cascade output
-      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
-      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
-      .PCOUT(),                   // 48-bit output: Cascade output
-      // Control: 1-bit (each) output: Control Inputs/Status Bits
-      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
-      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
-      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
-      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
-      // Data: 4-bit (each) output: Data Ports
-      .CARRYOUT(),             // 4-bit output: Carry output
-      .P(p1),                           // 48-bit output: Primary data output
-      // Cascade: 30-bit (each) input: Cascade Ports
-      .ACIN(),                     // 30-bit input: A cascade data input
-      .BCIN(),                     // 18-bit input: B cascade input
-      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
-      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
-      .PCIN(48'b0),                     // 48-bit input: P cascade input
-      // Control: 4-bit (each) input: Control Inputs/Status Bits
-      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
-      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
-      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
-      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
-      // Data: 30-bit (each) input: Data Ports
-      .A({{12{a1[17]}},a1}),                           // 30-bit input: A data input
-      .B(b),                           // 18-bit input: B data input
-      .C({ {13{c1[17]}}, c1[17:0],17'b0 }),                           // 48-bit input: C data input
-      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
-      .D(25'b0),                           // 25-bit input: D data input
-      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
-      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
-      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
-      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
-      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
-      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
-      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
-      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
-      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
-      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
-      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
-      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
-      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
-      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
-      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
-      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
-      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
-      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
-      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
-      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
-);
-   
-DSP48E1 #(
-      // Feature Control Attributes: Data Path Selection
-      .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
-      .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
-      .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
-      .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
-      .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
-      // Pattern Detector Attributes: Pattern Detection Configuration
-      .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" 
-      .MASK(48'h1),          // 48-bit mask value for pattern detect (1=ignore)
-      .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
-      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
-      .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
-      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
-      // Register Control Attributes: Pipeline Register Configuration
-      .ACASCREG(0),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
-      .ADREG(0),                        // Number of pipeline stages for pre-adder (0 or 1)
-      .ALUMODEREG(0),                   // Number of pipeline stages for ALUMODE (0 or 1)
-      .AREG(0),                         // Number of pipeline stages for A (0, 1 or 2)
-      .BCASCREG(0),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
-      .BREG(0),                         // Number of pipeline stages for B (0, 1 or 2)
-      .CARRYINREG(0),                   // Number of pipeline stages for CARRYIN (0 or 1)
-      .CARRYINSELREG(0),                // Number of pipeline stages for CARRYINSEL (0 or 1)
-      .CREG(0),                         // Number of pipeline stages for C (0 or 1)
-      .DREG(0),                         // Number of pipeline stages for D (0 or 1)
-      .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
-      .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
-      .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
-   )
-DSP48E1_2inst (
-      // Cascade: 30-bit (each) output: Cascade Ports
-      .ACOUT(),                   // 30-bit output: A port cascade output
-      .BCOUT(),                   // 18-bit output: B port cascade output
-      .CARRYCASCOUT(),     // 1-bit output: Cascade carry output
-      .MULTSIGNOUT(),       // 1-bit output: Multiplier sign cascade output
-      .PCOUT(),                   // 48-bit output: Cascade output
-      // Control: 1-bit (each) output: Control Inputs/Status Bits
-      .OVERFLOW(),             // 1-bit output: Overflow in add/acc output
-      .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
-      .PATTERNDETECT(),   // 1-bit output: Pattern detect output
-      .UNDERFLOW(),           // 1-bit output: Underflow in add/acc output
-      // Data: 4-bit (each) output: Data Ports
-      .CARRYOUT(),             // 4-bit output: Carry output
-      .P(p2),                           // 48-bit output: Primary data output
-      // Cascade: 30-bit (each) input: Cascade Ports
-      .ACIN(),                     // 30-bit input: A cascade data input
-      .BCIN(),                     // 18-bit input: B cascade input
-      .CARRYCASCIN(),       // 1-bit input: Cascade carry input
-      .MULTSIGNIN(),         // 1-bit input: Multiplier sign input
-      .PCIN(48'b0),                     // 48-bit input: P cascade input
-      // Control: 4-bit (each) input: Control Inputs/Status Bits
-      .ALUMODE(4'b0000),               // 4-bit input: ALU control input
-      .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
-      .INMODE(5'b00000),                 // 5-bit input: INMODE control input
-      .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
-      // Data: 30-bit (each) input: Data Ports
-      .A({{12{p1[47]}},p1[34:17]}),                           // 30-bit input: A data input
-      .B(b),                           // 18-bit input: B data input
-      .C({ {13{c2[17]}}, c2[17:0],17'b0 }),                           // 48-bit input: C data input
-      .CARRYIN(1'b0),               // 1-bit input: Carry input signal
-      .D(25'b0),                           // 25-bit input: D data input
-      // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
-      .CEA1(1'b1),                     // 1-bit input: Clock enable input for 1st stage AREG
-      .CEA2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage AREG
-      .CEAD(1'b1),                     // 1-bit input: Clock enable input for ADREG
-      .CEALUMODE(1'b1),           // 1-bit input: Clock enable input for ALUMODE
-      .CEB1(1'b1),                     // 1-bit input: Clock enable input for 1st stage BREG
-      .CEB2(1'b1),                     // 1-bit input: Clock enable input for 2nd stage BREG
-      .CEC(1'b1),                       // 1-bit input: Clock enable input for CREG
-      .CECARRYIN(1'b1),           // 1-bit input: Clock enable input for CARRYINREG
-      .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
-      .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
-      .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
-      .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
-      .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
-      .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
-      .RSTB(1'b0),                     // 1-bit input: Reset input for BREG
-      .RSTC(1'b0),                     // 1-bit input: Reset input for CREG
-      .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
-      .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
-      .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
-);
-
 endmodule

S5443_M/S5443.srcs/sources_1/new/S5243Top.v

@@ -29,7 +29,7 @@
 //  xc7s25-2csga225
 // new feature added
 
-module	S5243Top
+module	S5443Top
 #(	
 	parameter	LpDataWidth			=	16,
 	parameter	CtrlWidth			=	4,
@@ -165,6 +165,7 @@ module	S5243Top
 	wire	gatingPulse;
 	wire	sampleStrobe;
 	wire	[ChNum-1:0]	measStartBus;
+	// wire	measStart	=	&measStartBus;
 	wire	measStart;
 	// reg		measStart;