Актуализирован проект для FPGA_S.

S5443_S/S5443.srcs/sources_1/new/InternalDsp/ComplPrng.v

@@ -46,7 +46,7 @@ reg	signed	[OutDataWidth-1:0]	dataAndPrngReg;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-assign	adcDataExtended		=	{Data_i[InDataWidth-1], Data_i[InDataWidth-1], Data_i, 4'b0};
+// assign	adcDataExtended		=	{Data_i[InDataWidth-1], Data_i[InDataWidth-1], Data_i, 4'b0};
 assign	dataPrngCut			=	dataPrng[31-:DataPrngWidth];
 // assign	dataPrngCutExtended	=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
 // assign	DataAndPrng_o		=	adcDataExtended+dataPrngCutExtended;
@@ -86,7 +86,7 @@ always @(posedge Clk_i) begin
 	if (Rst_i) begin
 		dataAndPrngReg	<=	0;
 	end else begin
-		dataAndPrngReg	<=	adcDataExtended+dataPrngCutExtended;
+		dataAndPrngReg	<=	Data_i+dataPrngCutExtended;
 	end
 end
 

S5443_S/S5443.srcs/sources_1/new/InternalDsp/DspPipeline.v

@@ -46,9 +46,7 @@ module DspPipeline
 	wire	adcWindCosResultVal;
 	
 	wire	[AccWidth-1:0]	AccResultI;
-	wire	AccResultIVal;
 	wire	[AccWidth-1:0]	AccResultQ;
-	wire	AccResultQVal;
 	
 	wire	[ResultWidth-1:0]	NormResultI;
 	wire	NormResultIVal;
@@ -147,8 +145,7 @@ SummAccQ
     .Val_i		(adcWindSinResultVal),
 	
 	.Data_i		(adcWindSinResult[53:0]),
-	.Result_o	(AccResultQ),
-	.ResultVal_o(AccResultQVal)
+	.Result_o	(AccResultQ)
 );
 
 SumAcc
@@ -163,8 +160,7 @@ SummAccI
     .Val_i		(adcWindCosResultVal),
 	
 	.Data_i		(adcWindCosResult[53:0]),
-	.Result_o	(AccResultI),
-	.ResultVal_o(AccResultIVal)
+	.Result_o	(AccResultI)
 );
 
 //===============================InToFpConv=======================================

S5443_S/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -99,8 +99,8 @@ module InternalDsp
 	wire	[NcoWidth-1:0]	ncoCos;
 	wire	[NcoWidth-1:0]	ncoSin;
 	
-	// wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
-	wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	// wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
@@ -128,24 +128,29 @@ module InternalDsp
 	
 	wire	[31:0]	windArg;
 	
-	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-4]:{CorrAdcDataWidth{1'b0}};
-	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-3]:{CorrAdcDataWidth{1'b0}};
-	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-2]:{CorrAdcDataWidth{1'b0}};
-	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	// wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	// wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	
+	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
 	
 	wire	[WindNcoPhIncWidth-1:0]	ncoPhInc = {ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg};
 //================================================================================
 //  ASSIGNMENTS
 	
-	assign	adcDataBus	[ChNum-1]	=	Adc2ChT2Data_i;
-	assign	adcDataBus	[ChNum-2]	=	Adc2ChR2Data_i;
-	assign	adcDataBus	[ChNum-3]	=	Adc1ChR1Data_i;
-	assign	adcDataBus	[ChNum-4]	=	Adc1ChT1Data_i;
+	// assign	adcDataBus	[ChNum-1]	=	Adc2ChT2Data_i;
+	// assign	adcDataBus	[ChNum-2]	=	Adc2ChR2Data_i;
+	// assign	adcDataBus	[ChNum-3]	=	Adc1ChR1Data_i;
+	// assign	adcDataBus	[ChNum-4]	=	Adc1ChT1Data_i;
 
-	// assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
 	
 	
 	assign	gatedAdcDataBus	[ChNum-1]	=	adc2ChT2DataGated;
@@ -306,21 +311,6 @@ ncoInst
 generate
 	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
 	
-		ComplPrng
-		#(
-			.DataPrngWidth	(6),
-			.InDataWidth 	(AdcDataWidth),
-			.OutDataWidth	(CorrAdcDataWidth)
-		)
-		ComplPrngAdderInst
-		(
-			.Data_i	(adcDataBus[g]),
-			.Clk_i	(Clk_i),
-			.Rst_i	(Rst_i),
-
-			.DataAndPrng_o	(adcDataBusExt[g])
-		);
-
 		AdcCalibration 
 		#(	
 			// .AccNum			(32),
@@ -332,13 +322,28 @@ generate
 			.Clk_i					(Clk_i),
 			.Rst_i					(Rst_i),
 			.CalModeEn_i			(CalModeEn_i),
-			.AdcData_i				(adcDataBusExt[g]),
-			// .AdcData_i				(adcDataBus[g]),
+			// .AdcData_i				(adcDataBusExt[g]),
+			.AdcData_i				(adcDataBus[g]),
 			
 			.CalDone_o				(calDone[g]),
 			.CalibratedAdcData_o	(calAdcData[g])
 		);
 
+		ComplPrng
+		#(
+			.DataPrngWidth	(8),
+			.InDataWidth 	(CorrAdcDataWidth),
+			.OutDataWidth	(CorrAdcDataWidth)
+		)
+		ComplPrngAdderInst
+		(
+			.Data_i	(calAdcData[g]),
+			.Clk_i	(Clk_i),
+			.Rst_i	(Rst_i),
+
+			.DataAndPrng_o	(adcDataBusExt[g])
+		);
+		
 		DspPipeline	
 		#(	
 			.AdcDataWidth		(AdcDataWidth),

S5443_S/S5443.srcs/sources_1/new/Math/MyIntToFp.v

@@ -115,7 +115,11 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 		OutDataVal_o	<=	1'b0;
 	end	else	begin
 		if	(outValR)	begin
-			OutData_o	<=	fpOut;
+			if	(fpOut!=0)	begin
+				OutData_o	<=	fpOut;
+			end	else	begin
+				OutData_o	<=	32'h3a83126f;
+			end
 		end
 		OutDataVal_o	<=	outValR;
 	end

S5443_S/S5443.srcs/sources_1/new/S5443Top.v

@@ -1177,7 +1177,7 @@ SampleStrobeMux
 
 	.DspTrigOut_i	(1'b0),
 	.DspStartCmd_i	(1'b0),
-	.IntTrig_i		(1'b0),
+	.IntTrig_i		(intTrig1),
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(),