Расчет оконной функции ведется на частоте 200MHz, с добавлением регистра между стадиями расчета, для улучшения таймингов.

S5443_M/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DIVIDE		(6),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -35,7 +35,7 @@ module Win_calc	(
 //  REG/WIRE
 //================================================================================
 	
-	reg			[2:0]	calc_cycle;
+	reg			[3:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -136,30 +136,36 @@ always	@(*)	begin
 	end
 end
 
-always	@(posedge	wind_clk)	begin
+always	@(negedge	wind_clk)	begin
 	if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				3'd0: 	
+				4'd1: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
-							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				3'd1:	
+				4'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				3'd2:	
+				4'd3:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
+		// end	else	begin
+			// a1	<=	18'b0;
+			// c1	<=	18'b0;
+			// c2	<=	18'b0;
+			// b	<=	18'b0;
+		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -167,6 +173,33 @@ always	@(posedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
+
+// always	@(*)	begin
+	// if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
+			// case	(calc_cycle)
+				// 3'd1: 	
+						// begin
+							// a1	=	A5;
+							// c1	=	A4;
+							// c2	=	A3;
+							// b	=	bCurr;
+						// end
+			// endcase
+		// end	else	begin
+			// a1	=	18'b0;
+			// c1	=	18'b0;
+			// c2	=	18'b0;
+			// b	=	18'b0;
+		// end
+	// end	else	begin
+		// a1	=	18'b0;
+		// c1	=	18'b0;
+		// c2	=	18'b0;
+		// b	=	18'b0;
+	// end
+// end
+
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -209,13 +242,17 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-			if	(calc_cycle	!=	3'd2)	begin
-				calc_cycle	<=	calc_cycle	+	3'd1;
+		if	(MeasWind_i)	begin
+			if	(calc_cycle	!=	4'd3)	begin
+				calc_cycle	<=	calc_cycle	+	4'd1;
 			end	else	begin
-				calc_cycle	<=	3'd0;
+				calc_cycle	<=	4'd0;
 			end
+		end	else	begin
+			calc_cycle	<=	4'd0;
+		end
 	end	else	begin
-		calc_cycle	<=	3'd0;
+		calc_cycle	<=	4'd0;
 	end
 end
 
@@ -247,7 +284,7 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
    )
 FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
@@ -273,8 +310,8 @@ FirstStage (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      // .CLK(1'b0),                       // 1-bit input: Clock input
+      .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -295,7 +332,7 @@ FirstStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -305,8 +342,8 @@ FirstStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -385,8 +422,8 @@ SecondStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -395,8 +432,8 @@ SecondStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule

S5443_M/S5443.srcs/sources_1/new/S5443TopPulseProfileTb.v

@@ -72,8 +72,8 @@ module S5443TopPulseProfileTb;
 	//COMMANDS	FOR REG_MAP
 	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
 	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
-	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
-	parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
+	parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
+	// parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
 	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};

S5443_S/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DIVIDE		(6),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5443_S/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -35,7 +35,7 @@ module Win_calc	(
 //  REG/WIRE
 //================================================================================
 	
-	reg			[2:0]	calc_cycle;
+	reg			[3:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -136,30 +136,36 @@ always	@(*)	begin
 	end
 end
 
-always	@(posedge	wind_clk)	begin
+always	@(negedge	wind_clk)	begin
 	if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				3'd0: 	
+				4'd1: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
-							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				3'd1:	
+				4'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				3'd2:	
+				4'd3:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
+		// end	else	begin
+			// a1	<=	18'b0;
+			// c1	<=	18'b0;
+			// c2	<=	18'b0;
+			// b	<=	18'b0;
+		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -167,6 +173,33 @@ always	@(posedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
+
+// always	@(*)	begin
+	// if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
+			// case	(calc_cycle)
+				// 3'd1: 	
+						// begin
+							// a1	=	A5;
+							// c1	=	A4;
+							// c2	=	A3;
+							// b	=	bCurr;
+						// end
+			// endcase
+		// end	else	begin
+			// a1	=	18'b0;
+			// c1	=	18'b0;
+			// c2	=	18'b0;
+			// b	=	18'b0;
+		// end
+	// end	else	begin
+		// a1	=	18'b0;
+		// c1	=	18'b0;
+		// c2	=	18'b0;
+		// b	=	18'b0;
+	// end
+// end
+
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -209,13 +242,17 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-			if	(calc_cycle	!=	3'd2)	begin
-				calc_cycle	<=	calc_cycle	+	3'd1;
+		if	(MeasWind_i)	begin
+			if	(calc_cycle	!=	4'd3)	begin
+				calc_cycle	<=	calc_cycle	+	4'd1;
 			end	else	begin
-				calc_cycle	<=	3'd0;
+				calc_cycle	<=	4'd0;
 			end
+		end	else	begin
+			calc_cycle	<=	4'd0;
+		end
 	end	else	begin
-		calc_cycle	<=	3'd0;
+		calc_cycle	<=	4'd0;
 	end
 end
 
@@ -247,7 +284,7 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
    )
 FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
@@ -273,8 +310,8 @@ FirstStage (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      // .CLK(1'b0),                       // 1-bit input: Clock input
+      .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -295,7 +332,7 @@ FirstStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -305,8 +342,8 @@ FirstStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -385,8 +422,8 @@ SecondStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -395,8 +432,8 @@ SecondStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule