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Shalambala 2 anos atrás
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S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.dcp


Diferenças do arquivo suprimidas por serem muito extensas
+ 12458 - 12458
S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v


Diferenças do arquivo suprimidas por serem muito extensas
+ 13680 - 13680
S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.vhdl


+ 18 - 9
S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -74,15 +74,15 @@ module	DspInterface
 	output	LpOutClk_o,
 	output	[ODataWidth-1:0]	LpOutData_o,
 	
-	input	[ResultWidth-1:0]	Adc1T1ImResult_i,	//T1_FIRST_IM
-	input	[ResultWidth-1:0]	Adc1T1ReResult_i,	//T1_FIRST_RE
-	input	[ResultWidth-1:0]	Adc1R1ImResult_i,	//T2_FIRST_IM
-	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	//T2_FIRST_RE
-	
-	input	[ResultWidth-1:0]	Adc2R2ImResult_i,	//T2_SECOND_IM
-	input	[ResultWidth-1:0]	Adc2R2ReResult_i,	//T2_SECOND_RE
-	input	[ResultWidth-1:0]	Adc2T2ImResult_i,	//T1_SECOND_IM
-	input	[ResultWidth-1:0]	Adc2T2ReResult_i,	//T1_SECOND_RE
+	input	[ResultWidth-1:0]	Adc1T1ImResult_i,	//T1_FIRST_IM->T2_I_F
+	input	[ResultWidth-1:0]	Adc1T1ReResult_i,	//T1_FIRST_RE->T2_Q_F
+	input	[ResultWidth-1:0]	Adc1R1ImResult_i,	
+	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	
+	
+	input	[ResultWidth-1:0]	Adc2R2ImResult_i,	
+	input	[ResultWidth-1:0]	Adc2R2ReResult_i,	
+	input	[ResultWidth-1:0]	Adc2T2ImResult_i,	//T1_SECOND_IM->T2_I_S
+	input	[ResultWidth-1:0]	Adc2T2ReResult_i,	//T1_SECOND_RE->T2_Q_S
 	input	[ChNum-1:0]			ServiseRegData_i,
 
 	input	LpOutStart_i
@@ -138,6 +138,15 @@ module	DspInterface
 	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	32'h40a0_0000;	//5 in float
 	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	32'h4000_0000;	//2 in float
 	
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	32'h4000_0000;	//2 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	32'h4040_0000;	//3 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	32'h0;	//4 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	32'h0;	//9 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	32'h4000_0000;	//2 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	32'h4040_0000;	//3 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	32'h0;	//5 in float
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	32'h0;	//2 in float
+	
 	assign	OscDataRdFlag_o	=	measDataValTx;
 	
 //================================================================================

+ 4 - 4
S5443_M/S5443.srcs/sources_1/new/InternalDsp/CordicNco.v

@@ -90,10 +90,10 @@ module CordicNco
 	assign precompAngle[11] = 32'd333772;
 	assign precompAngle[12] = 32'd166886;
 	assign precompAngle[13] = 32'd83443;
-	assign precompAngle[14] = 32'd41722;
-	assign precompAngle[15] = 32'd20861;
-	assign precompAngle[16] = 32'd10430;
-	assign precompAngle[17] = 32'd5215;
+	// assign precompAngle[14] = 32'd41722;
+	// assign precompAngle[15] = 32'd20861;
+	// assign precompAngle[16] = 32'd10430;
+	// assign precompAngle[17] = 32'd5215;
 	//assign precompAngle[18] = 32'd2608;
 
 	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;

+ 12 - 12
S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -145,10 +145,10 @@ module InternalDsp
 //================================================================================
 //  ASSIGNMENTS
 
-	// assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	// assign	adcDataBus	[ChNum-1]	=	18'h0;
+	// assign	adcDataBus	[ChNum-2]	=	18'h0;
+	// assign	adcDataBus	[ChNum-3]	=	18'h0;
+	// assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};	//T2
 		
 	assign	adcDataBus	[ChNum-1]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
 	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
@@ -165,15 +165,15 @@ module InternalDsp
 	assign	gatedAdcDataBus	[ChNum-3]	=	adc1ChR1DataGated;
 	assign	gatedAdcDataBus	[ChNum-4]	=	adc1ChT1DataGated;
 	
-	assign	Adc1ImT1Data_o	=	resultImBus	[ChNum-4];
-	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
-	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
-	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
+	assign	Adc1ImT1Data_o	=	resultImBus	[ChNum-4];	//T1->T2_F_I
+	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];	//T1->T2_F_Q
+	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];	
+	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];	
 	//adc2                 
-	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-1];
-	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-1];
-	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-2];
-	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-2];
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-1];	
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-1];	
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-2];	//T1->R2_S_I
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-2];	//T1->R2_S_Q
 	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;