module Clk200Gen 
(
    input	Clk_i,
    input	Rst_i,
	output	Clk200_o,
	output	Clk10Timers_o,
	output	Clk150_o,
	
	output	Locked_o
);

wire	ClkFb;
wire	rxFb;

PLLE2_ADV #(
      	.BANDWIDTH		("OPTIMIZED"),
      	.CLKFBOUT_MULT		(24),
      	.CLKFBOUT_PHASE		(0.0),
      	.CLKIN1_PERIOD		(20),
      	.CLKIN2_PERIOD		(),
      	.CLKOUT0_DIVIDE		(6),
      	.CLKOUT0_DUTY_CYCLE	(0.5),
      	.CLKOUT0_PHASE		(0.0),
      	.CLKOUT1_DIVIDE		(120),
      	.CLKOUT1_DUTY_CYCLE	(0.5),
      	.CLKOUT1_PHASE		(0.0),
      	.CLKOUT2_DIVIDE		(8),
      	.CLKOUT2_DUTY_CYCLE	(0.5),
      	.CLKOUT2_PHASE		(0.0),
      	.CLKOUT3_DIVIDE		(120),
      	.CLKOUT3_DUTY_CYCLE	(0.5),
      	.CLKOUT3_PHASE		(0.0),
      	.CLKOUT4_DIVIDE		(7),
      	.CLKOUT4_DUTY_CYCLE	(0.5),
      	.CLKOUT4_PHASE		(0.0),
      	.CLKOUT5_DIVIDE		(7),
      	.CLKOUT5_DUTY_CYCLE	(0.5),
      	.CLKOUT5_PHASE		(0.0),
      	.COMPENSATION		("BUF_IN"),
      	.DIVCLK_DIVIDE		(1),
      	.REF_JITTER1		(0.100))
CommonPll (
      	.CLKFBOUT		(ClkFb),
      	.CLKOUT0		(rx_mmcmout_200),
      	.CLKOUT1		(rx_mmcmout_10),
      	.CLKOUT2		(rx_mmcmout_150),
      	.CLKOUT3		(),
      	.CLKOUT4		(),
      	.CLKOUT5		(),
      	.DO				(),
      	.DRDY			(),
      	.PWRDWN			(1'b0),
      	.LOCKED			(Locked_o),
      	.CLKFBIN		(rxFb),
      	.CLKIN1			(Clk_i),
      	.CLKIN2			(1'b0),
      	.CLKINSEL		(1'b1),
      	.DADDR			(7'h00),
      	.DCLK			(1'b0),
      	.DEN			(1'b0),
      	.DI				(16'h0000),
      	.DWE			(1'b0),
      	.RST			(1'b0)
) ;


BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;

BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
BUFG	ctrlClk150 (.I(rx_mmcmout_150), .O(Clk150_o)) ;

endmodule