//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    PulseGen 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	PGenRstGenerator	
#(	
	parameter	PgenNum	=	7
)
(
	input	Rst_i,
	input	Clk_i,
	
	input	[PgenNum-1:0]	PGenRst_i,
	
	output	reg	[PgenNum-1:0]	PGenRst_o,
	output	reg	RstDone_o
);	

//================================================================================
//  LOCALPARAM
//================================================================================
	localparam	IDLE	=	2'h0;
	localparam	RST		=	2'h1;
	localparam	DEL		=	2'h2;
	
//================================================================================
//  REG/WIRE
//================================================================================
	reg	[1:0]	currState;
	
	reg	[PgenNum-1:0]	pGenRstReg;
	
	wire	orPGenRstReg	=	|pGenRstReg;
//================================================================================
//  ASSIGNMENTS
//================================================================================

//================================================================================
//  CODING
//================================================================================

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		pGenRstReg		<=	PGenRst_i;
	end	else	begin
		pGenRstReg		<=	0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		case(currState)
		IDLE	:	begin
						if (orPGenRstReg)	begin
							currState 	<= RST;
							PGenRst_o	<=	pGenRstReg;
							RstDone_o	<=	1'b1;
						end	else begin
							currState <= IDLE;
							PGenRst_o	<=	0;
							RstDone_o	<=	0;
						end
					end
					
		RST	:		begin
						if	(RstDone_o)	begin
							PGenRst_o	<=	0;
							RstDone_o	<=	0;
							currState 	<= DEL;
						end	else begin
							currState 	<= RST;
							PGenRst_o	<=	0;
							RstDone_o	<=	0;
						end
					end
					
		DEL	:		begin
						PGenRst_o	<=	0;
						RstDone_o	<=	0;
						currState 	<= IDLE;
					end
		endcase
	end	else	begin
		currState	<=	IDLE;
		PGenRst_o	<=	0;
		RstDone_o	<=	0;
	end
end

endmodule