`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 18.09.2020 15:31:58
// Design Name: 
// Module Name: RegMap
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// нужно доработать модуль для получения возможности обновления регистров как снаружи (внешний dsp) так и изнутри (информацией из других модулей в системе).
//////////////////////////////////////////////////////////////////////////////////

module	RegMap	
#(	
	parameter	CmdRegWidth				=	32,
	parameter	HeaderWidth				=	7,
	parameter	CmdDataRegWith			=	24
)
(
	input	Clk_i,
	input	Rst_i,
	input	PGenRstDone_i,
	
	input	Val_i,
	input	CalDone_i,
	input	[CmdRegWidth-1:0]		Data_i,
	input	[HeaderWidth-1:0]		AnsAddr_i,
	output	[CmdDataRegWith-1:0]	AnsDataReg_o,
	
	input	[CmdDataRegWith-1:0]	OverCtrlReg_i,
	
	output	[CmdDataRegWith-1:0]	GainCtrlReg_o,
	output	[CmdDataRegWith-1:0]	GainLowThreshT1Reg_o,
	output	[CmdDataRegWith-1:0]	GainHighThreshT1Reg_o,	
	output	[CmdDataRegWith-1:0]	GainLowThreshR1Reg_o,
	output	[CmdDataRegWith-1:0]	GainHighThreshR1Reg_o,
	output	[CmdDataRegWith-1:0]	GainLowThreshT2Reg_o,
	output	[CmdDataRegWith-1:0]	GainHighThreshT2Reg_o,
	output	[CmdDataRegWith-1:0]	GainLowThreshR2Reg_o,
	output	[CmdDataRegWith-1:0]	GainHighThreshR2Reg_o,
	output	[CmdDataRegWith-1:0]	OverThreshReg_o,
	output	[CmdDataRegWith-1:0]	DitherCtrlReg_o,
	output	[CmdDataRegWith-1:0]	MeasCtrlReg_o,
	output	[CmdDataRegWith-1:0]	AdcCtrlReg_o,
	output	[CmdDataRegWith-1:0]	AdcDirectRd0Reg_o,
	output	[CmdDataRegWith-1:0]	AdcDirectRd1Reg_o,
	output	[CmdDataRegWith-1:0]	IfFtwRegL_o,
	output	[CmdDataRegWith-1:0]	IfFtwRegH_o,
	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegL_o,
	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegH_o,
	output	[CmdDataRegWith-1:0]	DspTrigInReg_o,		
	output	[CmdDataRegWith-1:0]	DspTrigOutReg_o,
	output	[CmdDataRegWith-1:0]	DspTrigIn1Reg_o,		
	output	[CmdDataRegWith-1:0]	DspTrigIn2Reg_o,
	output	[CmdDataRegWith-1:0]	DspTrigOut1Reg_o,		
	output	[CmdDataRegWith-1:0]	DspTrigOut2Reg_o,
	//PG1 Regs
	output	[CmdDataRegWith-1:0]	PG1P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG1P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG1P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG1P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG1P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG1P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG1P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG1P123WidthReg_o,
	
	//PG2 Regs	
	output	[CmdDataRegWith-1:0]	PG2P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG2P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG2P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG2P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG2P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG2P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG2P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG2P123WidthReg_o,	
	
	//PG3 Regs	
	output	[CmdDataRegWith-1:0]	PG3P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG3P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG3P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG3P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG3P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG3P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG3P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG3P123WidthReg_o,
	
	//PG4 Regs	
	output	[CmdDataRegWith-1:0]	PG4P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG4P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG4P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG4P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG4P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG4P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG4P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG4P123WidthReg_o,
	
	//PG5 Regs	
	output	[CmdDataRegWith-1:0]	PG5P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG5P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG5P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG5P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG5P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG5P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG5P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG5P123WidthReg_o,
	
	//PG6 Regs	
	output	[CmdDataRegWith-1:0]	PG6P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG6P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG6P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG6P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG6P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG6P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG6P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG6P123WidthReg_o,
	
	//PG7 Regs	
	output	[CmdDataRegWith-1:0]	PG7P1DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG7P2DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG7P3DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG7P123DelayReg_o,
	output	[CmdDataRegWith-1:0]	PG7P1WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG7P2WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG7P3WidthReg_o,
	output	[CmdDataRegWith-1:0]	PG7P123WidthReg_o,
	
	output	[CmdDataRegWith-1:0]	MeasNum1Reg_o,
	output	[CmdDataRegWith-1:0]	MeasNum2Reg_o,
	
	output	[CmdDataRegWith-1:0]	PgMode0Reg_o,
	output	[CmdDataRegWith-1:0]	PgMode1Reg_o,
	
	output	[CmdDataRegWith-1:0]	MuxCtrl1Reg_o,
	output	[CmdDataRegWith-1:0]	MuxCtrl2Reg_o,
	output	[CmdDataRegWith-1:0]	MuxCtrl3Reg_o,
	output	[CmdDataRegWith-1:0]	MuxCtrl4Reg_o
);
//================================================================================
//	LOCALPARAMS
//================================================================================
	localparam	GainCtrlRegAddr			=	7'h0;
	localparam	GainLowThreshT1RegAddr	=	7'h1;
	localparam	GainHighThreshT1RegAddr	=	7'h2;
	localparam	GainLowThreshR1RegAddr	=	7'h3;
	localparam	GainHighThreshR1RegAddr	=	7'h4;
	localparam	GainLowThreshT2RegAddr	=	7'h5;
	localparam	GainHighThreshT2RegAddr	=	7'h6;
	localparam	GainLowThreshR2RegAddr	=	7'h7;
	localparam	GainHighThreshR2RegAddr	=	7'h8;
	localparam	OverCtrlRegAddr			=	7'h9;
	localparam	OverThreshRegAddr		=	7'hA;
	localparam	DitherCtrlRegAddr		=	7'hE;
	localparam	MeasCtrlRegAddr			=	7'h11;
	localparam	AdcCtrlRegAddr			=	7'h12;
	localparam	AdcDirectRd0RegAddr		=	7'h13;
	localparam	AdcDirectRd1RegAddr		=	7'h14;
	localparam	IfFtwRegHAddr			=	7'h15;
	localparam	IfFtwRegLAddr			=	7'h16;
	localparam	FilterCorrCoefHAddr		=	7'h17;
	localparam	FilterCorrCoefLAddr		=	7'h18;
	localparam	DspTrigInAddr			=	7'h19;	
	localparam	DspTrigOutAddr			=	7'h1a;	
	localparam	DspTrigIn1Addr			=	7'h5a;	
	localparam	DspTrigIn2Addr			=	7'h5b;	
	localparam	DspTrigOut1Addr			=	7'h5c;	
	localparam	DspTrigOut2Addr			=	7'h5d;	
	
	//Pulse meas regs
	
	//PG7 Addr
	localparam	PG7P1DelayRegAddr		=	7'h20;
	localparam	PG7P2DelayRegAddr		=	7'h21;
	localparam	PG7P3DelayRegAddr		=	7'h22;
	localparam	PG7P123DelayRegAddr		=	7'h23;
	localparam	PG7P1WidthRegAddr		=	7'h24;
	localparam	PG7P2WidthRegAddr		=	7'h25;
	localparam	PG7P3WidthRegAddr		=	7'h26;
	localparam	PG7P123WidthRegAddr		=	7'h27;

	//PG1 Addr
	localparam	PG1P1DelayRegAddr		=	7'h28;
	localparam	PG1P2DelayRegAddr		=	7'h29;
	localparam	PG1P3DelayRegAddr		=	7'h2a;
	localparam	PG1P123DelayRegAddr		=	7'h2b;
	localparam	PG1P1WidthRegAddr		=	7'h2c;
	localparam	PG1P2WidthRegAddr		=	7'h2d;
	localparam	PG1P3WidthRegAddr		=	7'h2e;
	localparam	PG1P123WidthRegAddr		=	7'h2f;	
	
	//PG2 Addr
	localparam	PG2P1DelayRegAddr		=	7'h30;
	localparam	PG2P2DelayRegAddr		=	7'h31;
	localparam	PG2P3DelayRegAddr		=	7'h32;
	localparam	PG2P123DelayRegAddr		=	7'h33;
	localparam	PG2P1WidthRegAddr		=	7'h34;
	localparam	PG2P2WidthRegAddr		=	7'h35;
	localparam	PG2P3WidthRegAddr		=	7'h36;
	localparam	PG2P123WidthRegAddr		=	7'h37;
	
	//PG3 Addr
	localparam	PG3P1DelayRegAddr		=	7'h38;
	localparam	PG3P2DelayRegAddr		=	7'h39;
	localparam	PG3P3DelayRegAddr		=	7'h3a;
	localparam	PG3P123DelayRegAddr		=	7'h3b;
	localparam	PG3P1WidthRegAddr		=	7'h3c;
	localparam	PG3P2WidthRegAddr		=	7'h3d;
	localparam	PG3P3WidthRegAddr		=	7'h3e;
	localparam	PG3P123WidthRegAddr		=	7'h3f;
	
	//PG4 Addr
	localparam	PG4P1DelayRegAddr		=	7'h40;
	localparam	PG4P2DelayRegAddr		=	7'h41;
	localparam	PG4P3DelayRegAddr		=	7'h42;
	localparam	PG4P123DelayRegAddr		=	7'h43;
	localparam	PG4P1WidthRegAddr		=	7'h44;
	localparam	PG4P2WidthRegAddr		=	7'h45;
	localparam	PG4P3WidthRegAddr		=	7'h46;
	localparam	PG4P123WidthRegAddr		=	7'h47;
	
	//PG5 Addr
	localparam	PG5P1DelayRegAddr		=	7'h48;
	localparam	PG5P2DelayRegAddr		=	7'h49;
	localparam	PG5P3DelayRegAddr		=	7'h4a;
	localparam	PG5P123DelayRegAddr		=	7'h4b;
	localparam	PG5P1WidthRegAddr		=	7'h4c;
	localparam	PG5P2WidthRegAddr		=	7'h4d;
	localparam	PG5P3WidthRegAddr		=	7'h4e;
	localparam	PG5P123WidthRegAddr		=	7'h4f;
	
	//PG6 Addr
	localparam	PG6P1DelayRegAddr		=	7'h50;
	localparam	PG6P2DelayRegAddr		=	7'h51;
	localparam	PG6P3DelayRegAddr		=	7'h52;
	localparam	PG6P123DelayRegAddr		=	7'h53;
	localparam	PG6P1WidthRegAddr		=	7'h54;
	localparam	PG6P2WidthRegAddr		=	7'h55;
	localparam	PG6P3WidthRegAddr		=	7'h56;
	localparam	PG6P123WidthRegAddr		=	7'h57;
	
	localparam	MeasNum1RegAddr			=	7'h58;
	localparam	MeasNum2RegAddr			=	7'h59;
	localparam	PGMode0RegAddr			=	7'h0b;
	localparam	PGMode1RegAddr			=	7'h1b;
	
	localparam	MuxCtrl1RegAddr			=	7'h1c;
	localparam	MuxCtrl2RegAddr			=	7'h1d;
	localparam	MuxCtrl3RegAddr			=	7'h1e;
	localparam	MuxCtrl4RegAddr			=	7'h1f;

//================================================================================
//	REG/WIRE
//================================================================================
	// common regs
	reg	[CmdDataRegWith-1:0]	gainCtrlReg;		//Use the same reg for store gain ctrl lines on both working modes 
	reg	[CmdDataRegWith-1:0]	gainLowThreshT1Reg;
	reg	[CmdDataRegWith-1:0]	gainHighThreshT1Reg;
	reg	[CmdDataRegWith-1:0]	gainLowThreshR1Reg;
	reg	[CmdDataRegWith-1:0]	gainHighThreshR1Reg;
	reg	[CmdDataRegWith-1:0]	gainLowThreshT2Reg;
	reg	[CmdDataRegWith-1:0]	gainHighThreshT2Reg;
	reg	[CmdDataRegWith-1:0]	gainLowThreshR2Reg;
	reg	[CmdDataRegWith-1:0]	gainHighThreshR2Reg;
	reg	[CmdDataRegWith-1:0]	overCtrlReg;
	reg	[CmdDataRegWith-1:0]	overThreshReg;
	reg	[CmdDataRegWith-1:0]	ditherCtrlReg;
	reg	[CmdDataRegWith-1:0]	measCtrlReg;
	reg	[CmdDataRegWith-1:0]	adcCtrlReg;
	reg	[CmdDataRegWith-1:0]	adcDirectRd0Reg;
	reg	[CmdDataRegWith-1:0]	adcDirectRd1Reg;
	reg	[CmdDataRegWith-1:0]	ifFtwRegL;
	reg	[CmdDataRegWith-1:0]	ifFtwRegH;
	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegL;
	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegH;
	reg	[CmdDataRegWith-1:0]	dspTrigInReg;
	reg	[CmdDataRegWith-1:0]	dspTrigOutReg;
	reg	[CmdDataRegWith-1:0]	dspTrigIn1Reg;
	reg	[CmdDataRegWith-1:0]	dspTrigIn2Reg;
	reg	[CmdDataRegWith-1:0]	dspTrigOut1Reg;
	reg	[CmdDataRegWith-1:0]	dspTrigOut2Reg;
	//pulse meas regs
	reg	[CmdDataRegWith-1:0]	pGMode0Reg;
	reg	[CmdDataRegWith-1:0]	pGMode1Reg;
	reg	[CmdDataRegWith-1:0]	measNum1Reg;	
	reg	[CmdDataRegWith-1:0]	measNum2Reg;
	reg	[CmdDataRegWith-1:0]	muxCtrl1Reg;
	reg	[CmdDataRegWith-1:0]	muxCtrl2Reg;
	reg	[CmdDataRegWith-1:0]	muxCtrl3Reg;
	reg	[CmdDataRegWith-1:0]	muxCtrl4Reg;
	
	//PG1 Regs
	reg	[CmdDataRegWith-1:0]	pG1P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG1P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG1P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG1P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG1P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG1P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG1P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG1P123WidthReg;
	
	//PG2 Regs	
	reg	[CmdDataRegWith-1:0]	pG2P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG2P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG2P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG2P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG2P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG2P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG2P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG2P123WidthReg;	
	
	//PG3 Regs	
	reg	[CmdDataRegWith-1:0]	pG3P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG3P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG3P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG3P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG3P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG3P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG3P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG3P123WidthReg;
	
	//PG4 Regs	
	reg	[CmdDataRegWith-1:0]	pG4P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG4P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG4P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG4P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG4P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG4P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG4P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG4P123WidthReg;
	
	//PG5 Regs	
	reg	[CmdDataRegWith-1:0]	pG5P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG5P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG5P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG5P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG5P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG5P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG5P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG5P123WidthReg;

	//PG6 Regs	
	reg	[CmdDataRegWith-1:0]	pG6P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG6P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG6P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG6P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG6P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG6P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG6P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG6P123WidthReg;

	//PG7 Regs	
	reg	[CmdDataRegWith-1:0]	pG7P1DelayReg;
	reg	[CmdDataRegWith-1:0]	pG7P2DelayReg;
	reg	[CmdDataRegWith-1:0]	pG7P3DelayReg;
	reg	[CmdDataRegWith-1:0]	pG7P123DelayReg;
	reg	[CmdDataRegWith-1:0]	pG7P1WidthReg;
	reg	[CmdDataRegWith-1:0]	pG7P2WidthReg;
	reg	[CmdDataRegWith-1:0]	pG7P3WidthReg;
	reg	[CmdDataRegWith-1:0]	pG7P123WidthReg;	

	//ans reg
	reg	[CmdDataRegWith-1:0]	ansReg;
//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign	GainCtrlReg_o			=	gainCtrlReg;		
	assign	GainLowThreshT1Reg_o	=	gainLowThreshT1Reg;
	assign	GainHighThreshT1Reg_o	=	gainHighThreshT1Reg;		
	assign	GainLowThreshR1Reg_o	=	gainLowThreshR1Reg;
	assign	GainHighThreshR1Reg_o	=	gainHighThreshR1Reg;
	assign	GainLowThreshT2Reg_o	=	gainLowThreshT2Reg;
	assign	GainHighThreshT2Reg_o	=	gainHighThreshT2Reg;
	assign	GainLowThreshR2Reg_o	=	gainLowThreshR2Reg;
	assign	GainHighThreshR2Reg_o	=	gainHighThreshR2Reg;
	assign	OverThreshReg_o			=	overThreshReg;
	assign	DitherCtrlReg_o			=	ditherCtrlReg;
	assign	MeasCtrlReg_o			=	measCtrlReg;
	assign	AdcCtrlReg_o			=	adcCtrlReg;
	assign	AdcDirectRd0Reg_o		=	adcDirectRd0Reg;
	assign	AdcDirectRd1Reg_o		=	adcDirectRd1Reg;
	assign	IfFtwRegL_o				=	ifFtwRegL;
	assign	IfFtwRegH_o				=	ifFtwRegH;
	assign	FilterCorrCoefRegL_o	=	filterCorrCoefRegL;
	assign	FilterCorrCoefRegH_o	=	filterCorrCoefRegH;	
	assign	DspTrigInReg_o			=	dspTrigInReg;		
	assign	DspTrigOutReg_o			=	dspTrigOutReg;
	assign	DspTrigIn1Reg_o			=	dspTrigIn1Reg;		
	assign	DspTrigIn2Reg_o			=	dspTrigIn2Reg;
	assign	DspTrigOut1Reg_o		=	dspTrigOut1Reg;		
	assign	DspTrigOut2Reg_o		=	dspTrigOut2Reg;
	
	//PG1 Regs
	assign	PG1P1DelayReg_o		=	pG1P1DelayReg;
	assign	PG1P2DelayReg_o		=	pG1P2DelayReg;
	assign	PG1P3DelayReg_o		=	pG1P3DelayReg;
	assign	PG1P123DelayReg_o	=	pG1P123DelayReg;
	assign	PG1P1WidthReg_o		=	pG1P1WidthReg;
	assign	PG1P2WidthReg_o		=	pG1P2WidthReg;
	assign	PG1P3WidthReg_o		=	pG1P3WidthReg;
	assign	PG1P123WidthReg_o	=	pG1P123WidthReg;
   
	//PG2 Regs	                    
	assign	PG2P1DelayReg_o		=	pG2P1DelayReg;
	assign	PG2P2DelayReg_o		=	pG2P2DelayReg;
	assign	PG2P3DelayReg_o		=	pG2P3DelayReg;
	assign	PG2P123DelayReg_o	=	pG2P123DelayReg;
	assign	PG2P1WidthReg_o		=	pG2P1WidthReg;
	assign	PG2P2WidthReg_o		=	pG2P2WidthReg;
	assign	PG2P3WidthReg_o		=	pG2P3WidthReg;
	assign	PG2P123WidthReg_o	=	pG2P123WidthReg;
	
	//PG3 Regs	                    
	assign	PG3P1DelayReg_o		=	pG3P1DelayReg;
	assign	PG3P2DelayReg_o		=	pG3P2DelayReg;
	assign	PG3P3DelayReg_o		=	pG3P3DelayReg;
	assign	PG3P123DelayReg_o	=	pG3P123DelayReg;
	assign	PG3P1WidthReg_o		=	pG3P1WidthReg;
	assign	PG3P2WidthReg_o		=	pG3P2WidthReg;
	assign	PG3P3WidthReg_o		=	pG3P3WidthReg;
	assign	PG3P123WidthReg_o	=	pG3P123WidthReg;

	//PG4 Regs	                    
	assign	PG4P1DelayReg_o		=	pG4P1DelayReg;
	assign	PG4P2DelayReg_o		=	pG4P2DelayReg;
	assign	PG4P3DelayReg_o		=	pG4P3DelayReg;
	assign	PG4P123DelayReg_o	=	pG4P123DelayReg;
	assign	PG4P1WidthReg_o		=	pG4P1WidthReg;
	assign	PG4P2WidthReg_o		=	pG4P2WidthReg;
	assign	PG4P3WidthReg_o		=	pG4P3WidthReg;
	assign	PG4P123WidthReg_o	=	pG4P123WidthReg;

	//PG5 Regs	                    
	assign	PG5P1DelayReg_o		=	pG5P1DelayReg;
	assign	PG5P2DelayReg_o		=	pG5P2DelayReg;
	assign	PG5P3DelayReg_o		=	pG5P3DelayReg;
	assign	PG5P123DelayReg_o	=	pG5P123DelayReg;
	assign	PG5P1WidthReg_o		=	pG5P1WidthReg;
	assign	PG5P2WidthReg_o		=	pG5P2WidthReg;
	assign	PG5P3WidthReg_o		=	pG5P3WidthReg;
	assign	PG5P123WidthReg_o	=	pG5P123WidthReg;
	
	//PG6 Regs	                    
	assign	PG6P1DelayReg_o		=	pG6P1DelayReg;
	assign	PG6P2DelayReg_o		=	pG6P2DelayReg;
	assign	PG6P3DelayReg_o		=	pG6P3DelayReg;
	assign	PG6P123DelayReg_o	=	pG6P123DelayReg;
	assign	PG6P1WidthReg_o		=	pG6P1WidthReg;
	assign	PG6P2WidthReg_o		=	pG6P2WidthReg;
	assign	PG6P3WidthReg_o		=	pG6P3WidthReg;
	assign	PG6P123WidthReg_o	=	pG6P123WidthReg;
	
	//PG7 Regs	                    
	assign	PG7P1DelayReg_o		=	pG7P1DelayReg;
	assign	PG7P2DelayReg_o		=	pG7P2DelayReg;
	assign	PG7P3DelayReg_o		=	pG7P3DelayReg;
	assign	PG7P123DelayReg_o	=	pG7P123DelayReg;
	assign	PG7P1WidthReg_o		=	pG7P1WidthReg;
	assign	PG7P2WidthReg_o		=	pG7P2WidthReg;
	assign	PG7P3WidthReg_o		=	pG7P3WidthReg;
	assign	PG7P123WidthReg_o	=	pG7P123WidthReg;
	
	assign	MeasNum1Reg_o		=	measNum1Reg;
	assign	MeasNum2Reg_o		=	measNum2Reg;
	
	assign	PgMode0Reg_o		=	pGMode0Reg;
	assign	PgMode1Reg_o		=	pGMode1Reg;
	
	assign	MuxCtrl1Reg_o		=	muxCtrl1Reg;
	assign	MuxCtrl2Reg_o		=	muxCtrl2Reg;
	assign	MuxCtrl3Reg_o		=	muxCtrl3Reg;
	assign	MuxCtrl4Reg_o		=	muxCtrl4Reg;
	
	assign	AnsDataReg_o		=	ansReg;
//================================================================================
//	CODING
//================================================================================
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(Val_i)	begin
				case	(Data_i[CmdRegWidth-2-:HeaderWidth])
					GainCtrlRegAddr:		begin
												gainCtrlReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainLowThreshT1RegAddr:	begin
												gainLowThreshT1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainHighThreshT1RegAddr:begin
												gainHighThreshT1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainLowThreshR1RegAddr:	begin
												gainLowThreshR1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainHighThreshR1RegAddr:begin
												gainHighThreshR1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainLowThreshT2RegAddr:	begin
												gainLowThreshT2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainHighThreshT2RegAddr:begin
												gainHighThreshT2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainLowThreshR2RegAddr:	begin
												gainLowThreshR2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					GainHighThreshR2RegAddr:begin
												gainHighThreshR2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					OverThreshRegAddr:		begin
												overThreshReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DitherCtrlRegAddr:		begin
												ditherCtrlReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					MeasCtrlRegAddr:		begin
												measCtrlReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					AdcDirectRd0RegAddr:	begin
												adcDirectRd0Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					AdcDirectRd1RegAddr:	begin
												adcDirectRd1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					IfFtwRegLAddr:			begin
												ifFtwRegL	<=	Data_i	[CmdDataRegWith-1:0];
											end
					IfFtwRegHAddr:			begin
												ifFtwRegH	<=	Data_i	[CmdDataRegWith-1:0];
											end
					FilterCorrCoefLAddr:	begin
												filterCorrCoefRegL	<=	Data_i	[CmdDataRegWith-1:0];
											end
					FilterCorrCoefHAddr:	begin
												filterCorrCoefRegH	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigInAddr:			begin
												dspTrigInReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigOutAddr:			begin
												dspTrigOutReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P1DelayRegAddr:		begin
												pG1P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P2DelayRegAddr:		begin
												pG1P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P3DelayRegAddr:		begin
												pG1P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P123DelayRegAddr:	begin
												pG1P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P1WidthRegAddr:		begin
												pG1P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P2WidthRegAddr:		begin
												pG1P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P3WidthRegAddr:		begin
												pG1P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG1P123WidthRegAddr:	begin
												pG1P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P1DelayRegAddr:		begin
												pG2P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P2DelayRegAddr:		begin
												pG2P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P3DelayRegAddr:		begin
												pG2P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P123DelayRegAddr:	begin
												pG2P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P1WidthRegAddr:		begin
												pG2P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P2WidthRegAddr:		begin
												pG2P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P3WidthRegAddr:		begin
												pG2P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG2P123WidthRegAddr:	begin
												pG2P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end		
					PG3P1DelayRegAddr:		begin
												pG3P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P2DelayRegAddr:		begin
												pG3P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P3DelayRegAddr:		begin
												pG3P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P123DelayRegAddr:	begin
												pG3P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P1WidthRegAddr:		begin
												pG3P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P2WidthRegAddr:		begin
												pG3P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P3WidthRegAddr:		begin
												pG3P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG3P123WidthRegAddr:	begin
												pG3P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					PG4P1DelayRegAddr:		begin
												pG4P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P2DelayRegAddr:		begin
												pG4P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P3DelayRegAddr:		begin
												pG4P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P123DelayRegAddr:	begin
												pG4P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P1WidthRegAddr:		begin
												pG4P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P2WidthRegAddr:		begin
												pG4P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P3WidthRegAddr:		begin
												pG4P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG4P123WidthRegAddr:	begin
												pG4P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					PG5P1DelayRegAddr:		begin
												pG5P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P2DelayRegAddr:		begin
												pG5P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P3DelayRegAddr:		begin
												pG5P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P123DelayRegAddr:	begin
												pG5P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P1WidthRegAddr:		begin
												pG5P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P2WidthRegAddr:		begin
												pG5P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P3WidthRegAddr:		begin
												pG5P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG5P123WidthRegAddr:	begin
												pG5P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end		
					PG6P1DelayRegAddr:		begin
												pG6P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P2DelayRegAddr:		begin
												pG6P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P3DelayRegAddr:		begin
												pG6P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P123DelayRegAddr:	begin
												pG6P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P1WidthRegAddr:		begin
												pG6P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P2WidthRegAddr:		begin
												pG6P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P3WidthRegAddr:		begin
												pG6P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG6P123WidthRegAddr:	begin
												pG6P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					PG7P1DelayRegAddr:		begin
												pG7P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P2DelayRegAddr:		begin
												pG7P2DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P3DelayRegAddr:		begin
												pG7P3DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P123DelayRegAddr:	begin
												pG7P123DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P1WidthRegAddr:		begin
												pG7P1WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P2WidthRegAddr:		begin
												pG7P2WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P3WidthRegAddr:		begin
												pG7P3WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					PG7P123WidthRegAddr:	begin
												pG7P123WidthReg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					MeasNum1RegAddr:			begin
												measNum1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					MeasNum2RegAddr:			begin
												measNum2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					PGMode0RegAddr:			begin
												pGMode0Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					// PGMode1RegAddr:			begin
												// pGMode1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											// end	
					MuxCtrl1RegAddr:		begin
												muxCtrl1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					MuxCtrl2RegAddr:		begin
												muxCtrl2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end	
					MuxCtrl3RegAddr:		begin
												muxCtrl3Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					MuxCtrl4RegAddr:		begin
												muxCtrl4Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigIn1Addr:			begin
												dspTrigIn1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigIn2Addr:			begin
												dspTrigIn2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigOut1Addr:		begin
												dspTrigOut1Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end
					DspTrigOut2Addr:		begin
												dspTrigOut2Reg	<=	Data_i	[CmdDataRegWith-1:0];
											end											
				endcase
			end
		end	else	begin
			gainCtrlReg			<=	{CmdDataRegWith{1'b0}};
			gainLowThreshT1Reg	<=	{CmdDataRegWith{1'b0}};
			gainHighThreshT1Reg	<=	{CmdDataRegWith{1'b0}};
			gainLowThreshR1Reg	<=	{CmdDataRegWith{1'b0}};
			gainHighThreshR1Reg	<=	{CmdDataRegWith{1'b0}};
			gainLowThreshT2Reg	<=	{CmdDataRegWith{1'b0}};
			gainHighThreshT2Reg	<=	{CmdDataRegWith{1'b0}};
			gainLowThreshR2Reg	<=	{CmdDataRegWith{1'b0}};
			gainHighThreshR2Reg	<=	{CmdDataRegWith{1'b0}};
			overThreshReg		<=	{CmdDataRegWith{1'b0}};
			ditherCtrlReg		<=	{CmdDataRegWith{1'b0}};
			measCtrlReg			<=	{CmdDataRegWith{1'b0}};
			adcDirectRd0Reg		<=	{CmdDataRegWith{1'b0}};
			adcDirectRd1Reg		<=	{CmdDataRegWith{1'b0}};
			ifFtwRegL			<=	{CmdDataRegWith{1'b0}};
			ifFtwRegH			<=	{CmdDataRegWith{1'b0}};
			filterCorrCoefRegL	<=	{CmdDataRegWith{1'b0}};
			filterCorrCoefRegH	<=	{CmdDataRegWith{1'b0}};
			dspTrigInReg		<=	{CmdDataRegWith{1'b0}};
			dspTrigOutReg		<=	{CmdDataRegWith{1'b0}};
			dspTrigIn1Reg		<=	{CmdDataRegWith{1'b0}};
			dspTrigIn2Reg		<=	{CmdDataRegWith{1'b0}};
			dspTrigOut1Reg		<=	{CmdDataRegWith{1'b0}};
			dspTrigOut2Reg		<=	{CmdDataRegWith{1'b0}};
			
			pG1P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG1P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG1P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG1P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG1P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG1P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG1P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG1P123WidthReg		<=	{CmdDataRegWith{1'b0}};
				
			pG2P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG2P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG2P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG2P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG2P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG2P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG2P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG2P123WidthReg		<=	{CmdDataRegWith{1'b0}};	
				
			pG3P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG3P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG3P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG3P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG3P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG3P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG3P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG3P123WidthReg		<=	{CmdDataRegWith{1'b0}};
				
			pG4P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG4P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG4P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG4P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG4P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG4P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG4P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG4P123WidthReg		<=	{CmdDataRegWith{1'b0}};
				
			pG5P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG5P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG5P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG5P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG5P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG5P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG5P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG5P123WidthReg		<=	{CmdDataRegWith{1'b0}};
			
			pG6P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG6P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG6P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG6P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG6P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG6P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG6P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG6P123WidthReg		<=	{CmdDataRegWith{1'b0}};
			
			pG7P1DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG7P2DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG7P3DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG7P123DelayReg		<=	{CmdDataRegWith{1'b0}};
			pG7P1WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG7P2WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG7P3WidthReg		<=	{CmdDataRegWith{1'b0}};
			pG7P123WidthReg		<=	{CmdDataRegWith{1'b0}};
			
			measNum1Reg			<=	{CmdDataRegWith{1'b0}};	
			measNum2Reg			<=	{CmdDataRegWith{1'b0}};	
			pGMode0Reg			<=	{CmdDataRegWith{1'b0}};	
			// pGMode1Reg			<=	{CmdDataRegWith{1'b0}};	
			muxCtrl1Reg			<=	{CmdDataRegWith{1'b0}};	
			muxCtrl2Reg			<=	{CmdDataRegWith{1'b0}};	
			muxCtrl3Reg			<=	{CmdDataRegWith{1'b0}};	
			muxCtrl4Reg			<=	{CmdDataRegWith{1'b0}};	
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(Val_i)	begin
				if	((Data_i[CmdRegWidth-2-:HeaderWidth])	==	PGMode1RegAddr)	begin
					pGMode1Reg	<=	Data_i	[CmdDataRegWith-1:0];
				end
			end	else	begin
				if	(PGenRstDone_i)	begin
					pGMode1Reg	<=	{pGMode1Reg[CmdDataRegWith-1:7],7'b0};
				end
			end
		end	else	begin
			pGMode1Reg			<=	{CmdDataRegWith{1'b0}};	
		end
	end
	
	
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(Val_i)	begin
				case	(Data_i[CmdRegWidth-2-:HeaderWidth])
					AdcCtrlRegAddr:			begin
												adcCtrlReg	<=	Data_i	[CmdDataRegWith-1:0];
											end		
				endcase
			end	else	if	(CalDone_i)	begin
				adcCtrlReg	[1]	<=	1'b0;
			end
		end	else	begin
			adcCtrlReg			<=	{CmdDataRegWith{1'b0}};
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			overCtrlReg	<=	OverCtrlReg_i;
		end
	end
	
	always	@(*)	begin
		if	(!Rst_i)	begin
				case	(AnsAddr_i)
					GainCtrlRegAddr:		begin
												ansReg	=	gainCtrlReg;
											end
					GainLowThreshT1RegAddr:	begin
												ansReg	=	gainLowThreshT1Reg;
											end
					GainHighThreshT1RegAddr:begin
												ansReg	=	gainHighThreshT1Reg;
											end
					GainLowThreshR1RegAddr:	begin
												ansReg	=	gainLowThreshR1Reg;
											end
					GainHighThreshR1RegAddr:begin
												ansReg	=	gainHighThreshR1Reg;
											end
					GainLowThreshT2RegAddr:	begin
												ansReg	=	gainLowThreshT2Reg;
											end
					GainHighThreshT2RegAddr:begin
												ansReg	=	gainHighThreshT2Reg;
											end
					GainLowThreshR2RegAddr:	begin
												ansReg	=	gainLowThreshR2Reg;
											end
					GainHighThreshR2RegAddr:begin
												ansReg	=	gainHighThreshR2Reg;
											end
					OverCtrlRegAddr			:begin
												ansReg	=	overCtrlReg;
											end
					OverThreshRegAddr:		begin
												ansReg	=	overThreshReg;
											end
					DitherCtrlRegAddr:		begin
												ansReg	=	ditherCtrlReg;
											end
					MeasCtrlRegAddr:		begin
												ansReg	=	measCtrlReg;
											end
					AdcCtrlRegAddr:			begin
												ansReg	=	adcCtrlReg;
											end
					AdcDirectRd0RegAddr:	begin
												ansReg	=	adcDirectRd0Reg;
											end
					AdcDirectRd1RegAddr:	begin
												ansReg	=	adcDirectRd1Reg;
											end
					IfFtwRegLAddr:			begin
												ansReg	=	ifFtwRegL;
											end
					IfFtwRegHAddr:			begin
												ansReg	=	ifFtwRegH;
											end
					FilterCorrCoefLAddr:	begin
												ansReg	=	filterCorrCoefRegL;
											end
					FilterCorrCoefHAddr:	begin
												ansReg	=	filterCorrCoefRegH;
											end
					DspTrigInAddr:			begin
												ansReg	=	dspTrigInReg;
											end
					DspTrigOutAddr:			begin
												ansReg	=	dspTrigOutReg;
											end
					DspTrigIn1Addr:			begin
												ansReg	=	dspTrigIn1Reg;
											end
					DspTrigIn2Addr:			begin
												ansReg	=	dspTrigIn2Reg;
											end
					DspTrigOut1Addr:		begin
												ansReg	=	dspTrigOut1Reg;
											end
					DspTrigOut2Addr:		begin
												ansReg	=	dspTrigOut2Reg;
											end
					default:				begin
												ansReg	=	0;
											end
				endcase
		end	else	begin
			ansReg	=	{CmdDataRegWith{1'b0}};
		end
	end
	
endmodule