`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
//////////////////////////////////////////////////////////////////////////////////
module	ActivePortSelector	
#(	
	parameter	PortsNum	=	4
)
(
	input	Rst_i,
	
	input	Mod_i,
	input	[PortsNum-1:0]	Ctrl_i,
	
	output	reg	[PortsNum-1:0]	Ctrl_o
);	

//================================================================================
//  LOCALPARAM
//================================================================================
	localparam	LutNum		=	2**PortsNum;
	localparam	PortsNone	=	4'b0000;
	localparam	Ports_1		=	4'b0001;
	localparam	Ports_2		=	4'b0010;
	localparam	Ports_21	=	4'b0011;
	localparam	Ports_3		=	4'b0100;
	localparam	Ports_31	=	4'b0101;
	localparam	Ports_32	=	4'b0110;
	localparam	Ports_321	=	4'b0111;
	localparam	Ports_4		=	4'b1000;
	localparam	Ports_41	=	4'b1001;
	localparam	Ports_42	=	4'b1010;
	localparam	Ports_421	=	4'b1011;
	localparam	Ports_43	=	4'b1100;
	localparam	Ports_431	=	4'b1101;
	localparam	Ports_432	=	4'b1110;
	localparam	Ports_4321	=	4'b1111;
	
//================================================================================
//	REG/WIRE
//================================================================================
	wire		[PortsNum-1:0]	Lut	[LutNum-1:0];

//================================================================================
//  ASSIGNMENTS
//================================================================================
	assign	Lut	[0]		=	~(4'b0000);
	assign	Lut	[1]		=	~({3'b000,Mod_i});
	assign	Lut	[2]		=	~({2'b00,Mod_i,1'b0});
	assign	Lut	[3]		=	~({2'b00,Mod_i,Mod_i});
	assign	Lut	[4]		=	~({1'b0,Mod_i,2'b0});
	assign	Lut	[5]		=	~({1'b0,Mod_i,1'b0,Mod_i});
	assign	Lut	[6]		=	~({1'b0,Mod_i,Mod_i,1'b0});
	assign	Lut	[7]		=	~({1'b0,Mod_i,Mod_i,Mod_i});
	assign	Lut	[8]		=	~({Mod_i,3'b000});
	assign	Lut	[9]		=	~({Mod_i,2'b00,Mod_i});
	assign	Lut	[10]	=	~({Mod_i,1'b0,Mod_i,1'd0});
	assign	Lut	[11]	=	~({Mod_i,1'b0,Mod_i,Mod_i});
	assign	Lut	[12]	=	~({Mod_i,Mod_i,2'b00});
	assign	Lut	[13]	=	~({Mod_i,Mod_i,1'b0,Mod_i});
	assign	Lut	[14]	=	~({Mod_i,Mod_i,Mod_i,1'b0});
	assign	Lut	[15]	=	~({Mod_i,Mod_i,Mod_i,Mod_i});

//================================================================================
//  CODING
always	@(*)	begin
	if	(!Rst_i)	begin
		case	(Ctrl_i)
			PortsNone:	begin
							Ctrl_o	=	Lut[0];
						end
			Ports_1:	begin
							Ctrl_o	=	Lut[1];
						end	
			Ports_2:	begin
							Ctrl_o	=	Lut[2];
						end
			Ports_21:	begin
							Ctrl_o	=	Lut[3];
						end	
			Ports_3:	begin
							Ctrl_o	=	Lut[4];
						end		
			Ports_31:	begin
							Ctrl_o	=	Lut[5];
						end	
			Ports_32:	begin
							Ctrl_o	=	Lut[6];
						end	
			Ports_321:	begin
							Ctrl_o	=	Lut[7];
						end
			Ports_4:	begin
							Ctrl_o	=	Lut[8];
						end		
			Ports_41:	begin
							Ctrl_o	=	Lut[9];
						end	
			Ports_42:	begin
							Ctrl_o	=	Lut[10];
						end	
			Ports_421:	begin
							Ctrl_o	=	Lut[11];
						end
			Ports_43:	begin
							Ctrl_o	=	Lut[12];
						end	
			Ports_431:	begin
							Ctrl_o	=	Lut[13];
						end
			Ports_432:	begin
							Ctrl_o	=	Lut[14];
						end
			Ports_4321:	begin
							Ctrl_o	=	Lut[15];
						end
		endcase
	end	else	begin
		Ctrl_o	=	4'd0;
	end
end


endmodule