module InitRst (
    clk_i,
    signal_o
);

//================================================================================
//
//  FUNCTIONS
//
//================================================================================

    function integer bit_num;
        input integer value;
        begin
            bit_num = 0;
            while (value > 0) begin
                value   = value >> 1;
                bit_num = bit_num + 1;
            end
        end
    endfunction

//================================================================================
//
//  PARAMETER/LOCALPARAM
//
//================================================================================

    parameter   DELAY_VALUE     = 20;
    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);

//================================================================================
//
//  PORTS
//
//================================================================================

    input           clk_i;
    output  reg     signal_o;

//================================================================================
//
//  STATE MACHINE STATES
//
//================================================================================

    localparam      SM_RST_S    = 1'b0;
    localparam      SM_DONE_S   = 1'b1;

//================================================================================
//
//  REG/WIRE
//
//================================================================================

    reg                         curr_state  = SM_RST_S;
    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
    reg                         delay_flag  = 1'b0;

    reg                         next_state;
    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
    reg                         signal_next;

//================================================================================
//
//  CODING
//
//================================================================================

initial begin
    curr_state  = SM_RST_S;
    delay_cnt   = {DELAY_CNT_W{1'b0}};
    signal_o    = 1'b1;
    delay_flag  = 1'b0;
end

always @(posedge clk_i) begin
    curr_state  <= next_state;
    delay_cnt   <= delay_cnt_next;
    signal_o    <= signal_next;
    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
end

always @(*) begin
    next_state      = SM_RST_S;
    delay_cnt_next  = delay_cnt;
    signal_next     = 1'b1;
    case(curr_state)
        SM_RST_S    : begin
            if (delay_flag) begin
                next_state      = SM_DONE_S;
            end else begin
                next_state      = SM_RST_S;
                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
            end
        end
        SM_DONE_S   : begin
            signal_next = 1'b0;
            next_state  = SM_DONE_S;
        end
    endcase
end

endmodule