S5443/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.veo

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// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 5

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
MeasDataFifo your_instance_name (
  .clk(clk),      // input wire clk
  .srst(srst),    // input wire srst
  .din(din),      // input wire [255 : 0] din
  .wr_en(wr_en),  // input wire wr_en
  .rd_en(rd_en),  // input wire rd_en
  .dout(dout),    // output wire [255 : 0] dout
  .full(full),    // output wire full
  .empty(empty)  // output wire empty
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file MeasDataFifo.v when simulating
// the core, MeasDataFifo. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.