S5443/S5443_S/S5443.srcs/sources_1/new/DitherGen/DitherGen.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:		Churbanov S.
// 
// Create Date:    10:00:14 13/08/2019 
// Design Name: 
// Module Name:    DspPpiOut 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DitherGen
#(	
	parameter	CmdDataRegWith		=	24,
	parameter	FrAmpWordWidth		=	8
)
(
	input	Rst_i,
	input	Clk_i,	
	
	input	[CmdDataRegWith-1:0]	DitherCmd_i,
	output	DitherCtrlT2R2_o,
	output	DitherCtrlT1R1_o
);
//================================================================================
//  REG/WIRE
//================================================================================
	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
	wire	[FrAmpWordWidth-1:0]	ditherAmp	=	DitherCmd_i[CmdDataRegWith-FrAmpWordWidth-1-:FrAmpWordWidth];

	wire	ditherT2R2	=	DitherCmd_i[1];
	wire	ditherT1R1	=	DitherCmd_i[0];
	
	reg	[FrAmpWordWidth-1:0]	freqCnt;
	reg	[FrAmpWordWidth-1:0]	ampCnt;
	
	wire	DitherReg	=	((freqCnt<=ditherFreq/2)&&(ampCnt<=ditherAmp))?	1'b1:1'b0;
	
	wire	ClkDiv	=	(freqCnt<=ditherFreq/2)?	1'b1:1'b0;
//================================================================================
//  ASSIGNMENTS
//================================================================================	
	assign	DitherCtrlT2R2_o	=	(ditherT2R2)?	DitherReg:1'b0;
	assign	DitherCtrlT1R1_o	=	(ditherT1R1)?	DitherReg:1'b0;
//================================================================================
//  CODING
//================================================================================	

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(freqCnt!=ditherFreq-1)	begin
			freqCnt<=freqCnt+1;
		end	else	begin
			freqCnt<=0;
		end
	end	else	begin
		freqCnt<=0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(ampCnt!=ditherFreq-1)	begin
			ampCnt<=ampCnt+1;
		end	else	begin
			ampCnt<=0;
		end
	end	else	begin
		ampCnt<=0;
	end
end

endmodule