MeasDataFifoWrapper.v 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. `timescale 1ns / 1ns
  2. module MeasDataFifoWrapper
  3. #(
  4. parameter DataWidth = 32,
  5. parameter ChNum = 4
  6. )
  7. (
  8. input Clk_i,
  9. input Rst_i,
  10. input PpiBusy_i,
  11. input StartMeasDsp_i,
  12. input DspReadyForRx_i,
  13. input [DataWidth-1:0] MeasNum_i,
  14. input [DataWidth*(ChNum*2)-1:0] MeasDataBus_i,
  15. input MeasDataVal_i,
  16. output [DataWidth*(ChNum*2)-1:0] MeasDataBus_o,
  17. output MeasDataVal_o
  18. );
  19. //================================================================================
  20. // REG/WIRE
  21. //================================================================================
  22. wire fullFlag;
  23. wire emptyFlag;
  24. wire wrEn;
  25. wire rdEn;
  26. reg startMeasDspReg;
  27. wire startMeasDspNeg;
  28. wire startMeasDspPos;
  29. reg ppiBusyReg;
  30. reg rstFromDsp;
  31. wire trueRstFromDsp;
  32. integer i;
  33. reg [0:0] rstFromDspPipe [49:0];
  34. reg [13:0] rdCnt;
  35. wire rstOr;
  36. //================================================================================
  37. // ASSIGNMENTS
  38. //================================================================================
  39. assign rstOr = Rst_i|startMeasDspPos;
  40. assign MeasDataVal_o = rdEn;
  41. assign startMeasDspPos = (StartMeasDsp_i&(!startMeasDspReg));
  42. //================================================================================
  43. // CODING
  44. //================================================================================
  45. always @(posedge Clk_i) begin
  46. if (!rstOr) begin
  47. if (rdEn) begin
  48. rdCnt <= rdCnt+14'd1;
  49. end
  50. end else begin
  51. rdCnt <= 14'd0;
  52. end
  53. end
  54. always @(posedge Clk_i) begin
  55. if (!Rst_i) begin
  56. startMeasDspReg <= StartMeasDsp_i;
  57. end else begin
  58. startMeasDspReg <= 1'b0;
  59. end
  60. end
  61. MeasDataFifo MeasDataFifoInst
  62. (
  63. .clk (Clk_i),
  64. .srst (Rst_i|startMeasDspPos),
  65. .din (MeasDataBus_i),
  66. .wr_en (wrEn),
  67. .rd_en (rdEn),
  68. .dout (MeasDataBus_o),
  69. .full (fullFlag),
  70. .empty (emptyFlag)
  71. );
  72. FifoController FifoControllerInst
  73. (
  74. .Clk_i (Clk_i),
  75. .Rst_i (Rst_i|startMeasDspPos),
  76. .DspReadyForRx_i (DspReadyForRx_i),
  77. .PpiBusy_i (PpiBusy_i),
  78. .MeasNum_i (MeasNum_i),
  79. .MeasDataVal_i (MeasDataVal_i),
  80. .FullFlag_i (fullFlag),
  81. .EmptyFlag_i (emptyFlag),
  82. .MeasDataVal_o (),
  83. .WrEn_o (wrEn),
  84. .RdEn_o (rdEn)
  85. );
  86. endmodule