S5443/S5443_M/S5443.srcs/sources_1/new/P2P5meas.txt

// `timescale 1ns / 1ns
module S5443TopPMTb;
	
	//=================================================================================================================================================================================================================
	//COMMANDS	FOR REG_MAP
	parameter	[31:0]	MeasCmd 			= {8'h11,8'h0,8'h72,8'h0};
	parameter	[31:0]	IfFtwH 				= {8'h15,16'h0,8'h23};
	parameter	[31:0]	IfFtwL 				= {8'h16,24'h51eb85};
	
	
	
	
	
	parameter	[31:0]	PulseMeasCtrlCmd 		=	{8'h1b,12'h0,4'h0,8'h1};	
	parameter	[31:0]	PG12ModeRegCmd			=	{8'h0b,8'h0,8'h1,8'h1};	
	parameter	[31:0]	PG34GModeRegCmd			=	{8'h0c,8'h0,8'h1,8'h1};
	parameter	[31:0]	GGPnumRegCmd			=	{8'h0d,24'h1};
	//PG1 Cmd
	parameter	[31:0]	PG1P1DelayRegCmd		=	{8'h28,24'd10};
	parameter	[31:0]	PG1P2DelayRegCmd		=	{8'h29,24'd50};
	parameter	[31:0]	PG1P3DelayRegCmd		=	{8'h2a,24'd90};
	parameter	[31:0]	PG1P123DelayRegCmd		=	{8'h2b,24'd0};
	parameter	[31:0]	PG1P1WidthRegCmd		=	{8'h2c,24'd30};
	parameter	[31:0]	PG1P2WidthRegCmd		=	{8'h2d,24'd30};
	parameter	[31:0]	PG1P3WidthRegCmd		=	{8'h2e,24'd30};
	parameter	[31:0]	PG1P123WidthRegCmd		=	{8'h2f,24'd0};

	//SSG Cmd
	parameter	[31:0]	SSGP1DelayRegCmd		=	{8'h4e,24'd20};
	parameter	[31:0]	SSGP2DelayRegCmd		=	{8'h4f,24'd35};
	parameter	[31:0]	SSGP12DelNumRegCmd		=	{8'h50,24'd0};
	parameter	[31:0]	SSGPNumRegCmd			=	{8'h51,24'd1};
	
	parameter	[31:0]	RefSeqPerRegCmd			=	{8'h52,24'd59};
	parameter	[31:0]	MeasNumRegCmd			=	{8'h53,24'd5};
	parameter	[31:0]	RefSeqPerMNumRegCmd		=	{8'h54,24'd0};
	
	
	
	
	
	//PG1-4 Cmd
	parameter	[31:0]	PG1PNumRegCmd			=	{8'h48,24'd1};
	parameter	[31:0]	PG2PNumRegCmd			=	{8'h49,24'd1};
	parameter	[31:0]	PG3PNumRegCmd			=	{8'h4a,24'd1};
	parameter	[31:0]	PG4PNumRegCmd			=	{8'h4b,24'd1};
	parameter	[31:0]	PG12PNumRegCmd			=	{8'h4c,24'd0};
	parameter	[31:0]	PG34GPNumRegCmd			=	{8'h4d,24'd0};

	//Gating Gen Cmd
	parameter	[31:0]	GGP1DelayRegCmd			=	{8'h1c,24'd6};
	parameter	[31:0]	GGP2DelayRegCmd			=	{8'h1d,24'd16};
	parameter	[31:0]	GGP3DelayRegCmd			=	{8'h1e,24'd31};
	parameter	[31:0]	GGP123DelayRegCmd		=	{8'h1f,24'd0};
	parameter	[31:0]	GGP1WidthRegCmd			=	{8'h20,24'd45};
	parameter	[31:0]	GGP2WidthRegCmd			=	{8'h21,24'd5};
	parameter	[31:0]	GGP3WidthRegCmd			=	{8'h22,24'd6};
	parameter	[31:0]	GGP123WidthRegCmd		=	{8'h23,24'd0};
	

	
	parameter	[31:0]	FilterCorrCmdH 		= {8'h17,24'hD70A3D};
	parameter	[31:0]	FilterCorrCmdL 		= {8'h18,24'hD70A3D};
	
		
	//PG2 Cmd
	parameter	[31:0]	PG2P1DelayRegCmd		=	{8'h30,24'd5};
	parameter	[31:0]	PG2P2DelayRegCmd		=	{8'h31,24'd15};
	parameter	[31:0]	PG2P3DelayRegCmd		=	{8'h32,24'd30};
	parameter	[31:0]	PG2P123DelayRegCmd		=	{8'h33,24'd0};
	parameter	[31:0]	PG2P1WidthRegCmd		=	{8'h34,24'd5};
	parameter	[31:0]	PG2P2WidthRegCmd		=	{8'h35,24'd6};
	parameter	[31:0]	PG2P3WidthRegCmd		=	{8'h36,24'd7};
	parameter	[31:0]	PG2P123WidthRegCmd		=	{8'h37,24'd0};
	
	//PG3 Cmd
	parameter	[31:0]	PG3P1DelayRegCmd		=	{8'h38,24'd5};
	parameter	[31:0]	PG3P2DelayRegCmd		=	{8'h39,24'd15};
	parameter	[31:0]	PG3P3DelayRegCmd		=	{8'h3a,24'd30};
	parameter	[31:0]	PG3P123DelayRegCmd		=	{8'h3b,24'd0};
	parameter	[31:0]	PG3P1WidthRegCmd		=	{8'h3c,24'd5};
	parameter	[31:0]	PG3P2WidthRegCmd		=	{8'h3d,24'd6};
	parameter	[31:0]	PG3P3WidthRegCmd		=	{8'h3e,24'd7};
	parameter	[31:0]	PG3P123WidthRegCmd		=	{8'h3f,24'd0};
	
	//PG4 Cmd
	parameter	[31:0]	PG4P1DelayRegCmd		=	{8'h40,24'd5};
	parameter	[31:0]	PG4P2DelayRegCmd		=	{8'h41,24'd15};
	parameter	[31:0]	PG4P3DelayRegCmd		=	{8'h42,24'd30};
	parameter	[31:0]	PG4P123DelayRegCmd		=	{8'h43,24'd0};
	parameter	[31:0]	PG4P1WidthRegCmd		=	{8'h44,24'd5};
	parameter	[31:0]	PG4P2WidthRegCmd		=	{8'h45,24'd6};
	parameter	[31:0]	PG4P3WidthRegCmd		=	{8'h46,24'd7};
	parameter	[31:0]	PG4P123WidthRegCmd		=	{8'h47,24'd0};
	
	//=================================================================================================================================================================================================================
	
	reg		Clk41;
	reg		Clk82;
	reg		Clk50;
	reg		Clk70;
	reg		Dclk175;
	reg		Clk350;
	reg		Clk125;
	
	reg	[31:0]	tb_cnt=4'd0;
	reg	rst;
	reg	mosi_i	=	1'b0;
	reg	Miso_i	=	1'b0;
	reg	ss_i;
	reg	clk_i	=	1'b0;
	
	
	reg	[31:0]	DspSpiData;
	reg		startCalcCmdReg;
	wire	startCalcCmdRegO;
						
	wire	[13:0]	cos_value;	
	wire	[17:0]	sin_value;				

	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
	
	// wire	ExtTrigger0		=	(tb_cnt	<=	150)?	ExtDspTrigPos0:ExtDspTrigNeg0;
	wire	ExtTrigger0		=	ExtDspTrigNeg0;
	
	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
	wire	endMeas;
	reg	[31:0]	cmdCnt;
	
	reg	trig0;
	reg	trig1;
	
	wire	trig0R;
    wire	trig1R;
	
	assign	trig0R	=	trig0;
    assign	trig1R	=	trig1;
	
//==========================================================================================
//clocks gen
	always	#10 Clk50	=	~Clk50;
	always	#8 Clk125	=	~Clk125;
	always	#14.285714285714 Clk70	=	~Clk70;
	always	#10 clk_i	=	~clk_i;
	always	#(24.390243902439/2)	Clk41	=	~Clk41;
	
	reg	Dclk175Reg;
	wire	sck_i;	
//==========================================================================================
initial begin
	Clk50	=	1'b1;
	Clk70	=	1'b1;
	Clk125	=	1'b1;
	rst		=	1'b1;
	Clk41	=	1'b0;
	startCalcCmdReg	=	1'b0;
	trig0	=	1'b0;
	trig1	=	1'b0;
#100;
	rst		=	1'b0;
#400;
	Clk41	=	1'b0;
end		
	
reg	endMeasReg;
always	@(posedge	Clk41)	begin
	endMeasReg	<=	endMeas;
end

wire	endMeasNeg	=	!endMeas&endMeasReg;

always	@(posedge	Clk70)	begin
	if	(tb_cnt	==	3000)	begin
		startCalcCmdReg	<=	1'b1;
	end	else	if	(endMeas)	begin
		startCalcCmdReg	<=	1'b0;
	end	
end

always	@(negedge	Clk41)	begin
	if	(!rst)		begin
		tb_cnt	<=	tb_cnt+1;
	end	else	begin
		tb_cnt	<=	0;
	end
end

reg	startMeasSync;
always	@(posedge	Clk41)	begin
	startMeasSync	<=	startCalcCmdRegO;
end

wire	Adc1DataDa0P;
wire	Adc1DataDa1P;

wire	[31:0]	test	=	32'h2351eb85;
CordicNco		
#(	.ODatWidth	(18),
	.PhIncWidth	(32),
	.IterNum	(10),
	.EnSinN		(0))
ncoInst
(
	.Clk_i				(Clk50),
	.Rst_i				(rst),
	.Val_i				(1'b1),
	.PhaseInc_i			(test>>1),
	.WindVal_i			(1'b1),
	.WinType_i			(),
	.Wind_o				(),
	.Sin_o				(sin_value),
	.Cos_o				(cos_value),
	.Val_o				()
);

wire	[13:0]	TPSK1		=	14'h1;
wire	[13:0]	TPSKN1		=	14'b11111111111111;
wire	[13:0]	I			=	(tb_cnt	>=	300	&&	tb_cnt	<=	500)?	TPSK1:TPSKN1;
wire	[13:0]	Q			=	(tb_cnt	>=	200	&&	tb_cnt	<=	500)?	TPSKN1:TPSK1;

//----------------------------------------------
// Module generates wind for measurement
wire	[17:0]	wind;
wire	[13:0]	adcWind;
CordicNco		
#(	
	.ODatWidth	(18),
	.PhIncWidth	(32),
	.IterNum	(10),
	.EnSinN		(0),
	.WinTypeW	(3)
)
winGenInst
(
	.Clk_i		(Clk50),
	.Rst_i		(1'b0),
	.Val_i		(1'b1),
	.PhaseInc_i	(32'h45>>1),
	.WinType_i	(0),
	.WindVal_i	(1'b1),
	.Wind_o		(wind),
	.Sin_o		(),
	.Cos_o		(),
	.Val_o		()
);

SimpleMult	
#(	
	.FactorAWidth	(18),
	.FactorBWidth	(18),
	.OutputWidth	(14)
)
AdcWindMult	
(
	.Rst_i		(1'b0),
	.Clk_i		(Clk50),
	.Val_i		(1'b1),
	.FactorA_i	(sin_value),
	.FactorB_i	(wind),
	.Result_o	(adcWind),
	.ResultVal_o()
);


S5443Top uut (
	.Clk_i				(Clk50),
	.Led_o				(),
//------------------------------------------	
    .Adc1FclkP_i		(Clk70),		
    .Adc1FclkN_i		(~Clk70),		
		
    .Adc1DataDa0P_i		(Adc1DataDa0P),
	.Adc1DataDa0N_i		(~Adc1DataDa0P),		
    .Adc1DataDa1P_i		(Adc1DataDa1P),
    .Adc1DataDa1N_i		(~Adc1DataDa1P),
    	
	.Adc1DataDb0P_i		(Adc1DataDa0P),
    .Adc1DataDb0N_i		(~Adc1DataDa0P),		
    .Adc1DataDb1P_i		(Adc1DataDa1P),
    .Adc1DataDb1N_i		(~Adc1DataDa1P),
//------------------------------------------	
    .Adc2FclkP_i		(Clk70),		
    .Adc2FclkN_i		(~Clk70),		
			
    .Adc2DataDa0P_i		(1'b1),
    .Adc2DataDa0N_i		(1'b0),		
    .Adc2DataDa1P_i		(1'b1),
    .Adc2DataDa1N_i		(1'b0),
  
	.Adc2DataDb0P_i		(1'b1),
    .Adc2DataDb0N_i		(1'b0),		
    .Adc2DataDb1P_i		(1'b1),
    .Adc2DataDb1N_i		(1'b0),
//------------------------------------------
	.AdcInitMosi_o		(),
	.AdcInitClk_o		(),			
	.Adc1InitCs_o		(),
	.Adc2InitCs_o		(),
	.AdcInitRst_o		(),
//------------------------------------------	
	
	.Mosi_i				(mosi_i),
	.Sck_i				(~sck_i),
	.Ss_i				(ss_i),
		
	.LpOutClk_o			(),
	.LpOutFs_o			(),			
	.LpOutData_o		(),
	
	//fpga-dsp signals
	.StartMeas_i		(startCalcCmdReg),
	.StartMeas_o		(),
	.EndMeas_o			(endMeas),
	.TimersClk_o		(),
	
	.Trig0_io			(trig0R),		//Trigger0 from/to external device
	.Trig0Dir_o			(),		//Trigger0 direction 
	
	.Trig1_io			(trig1R),		//Trigger0 from/to external device	
	.Trig1Dir_o			(),				//Trigger0 direction 
	
	.TrigFromDsp_i		(),				//Trig from DSP
	.TrigToDsp_o		(),				//Trig To DSP
	
	.OverloadS_i		(1'b0),
	.Overload_o			(),
	
	//mod out line
	
	.Mod_o				(),	
	
	//gain lines
	.SensEnS_i			(1'b0),
	.AmpEn_o			(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
	.AdcData_i			(adcWind)
);

parameter	IDLE	=	2'h0;
parameter	CMD		=	2'h1;
parameter	TX		=	2'h2;
parameter	PAUSE	=	2'h3;

reg	[1:0]	txCurrState;
reg	[1:0]	txNextState;

wire	txWork	=	tb_cnt	>=	23;
wire	txStop	=	cmdCnt	>=	62;


reg	[6:0]	txCnt;
reg	[3:0]	pauseCnt;

always	@(posedge	Clk41)	begin
	if	(!rst)	begin
		if	(txCurrState	==	CMD)	begin
			if	(!txStop)	begin
				cmdCnt	<=	cmdCnt+1;
			end
		end
	end	else	begin
		cmdCnt	<=	0;
	end
end

always	@(posedge	Clk41)	begin
	if	(!rst)	begin
		if	(txCurrState	==	TX)	begin
			txCnt	<=	txCnt+1;
		end	else	begin
			txCnt	<=	0;
		end
	end	else	begin
		txCnt	<=	0;
	end
end

always	@(posedge	Clk41)	begin
	if	(!rst)	begin
		if	(txCurrState	==	PAUSE)	begin
			pauseCnt	<=	pauseCnt+1;
		end	else	begin
			pauseCnt	<=	0;
		end
	end	else	begin
		pauseCnt	<=	0;
	end
end
	

always	@(posedge	Clk41)	begin
	if	(txCurrState	==	CMD)	begin
		if	(cmdCnt	==	0)	begin
			DspSpiData		<=	MeasCmd;
		end	else	if	(cmdCnt	==	1)	begin
			DspSpiData		<=	IfFtwH;
		end	else	if	(cmdCnt	==	2)	begin
			DspSpiData		<=	IfFtwL;
		end	else	if	(cmdCnt	==	3)	begin
			DspSpiData		<=	RefSeqPerMNumRegCmd;
		end else	if	(cmdCnt	==	4)	begin
			DspSpiData		<=	PG12ModeRegCmd;
		end	else	if	(cmdCnt	==	5)	begin
			DspSpiData		<=	PG34GModeRegCmd;
		end	else	if	(cmdCnt	==	6)	begin
			DspSpiData		<=	GGPnumRegCmd;	
		end	else	if	(cmdCnt	==	7)	begin
			DspSpiData		<=	PG1P1DelayRegCmd;
		end	else	if	(cmdCnt	==	8)	begin
			DspSpiData		<=	PG1P2DelayRegCmd;
		end	else	if	(cmdCnt	==	9)	begin
			DspSpiData		<=	PG1P3DelayRegCmd;
		end	else	if	(cmdCnt	==	10)	begin
			DspSpiData		<=	PG1P123DelayRegCmd;
		end	else	if	(cmdCnt	==	11)	begin
			DspSpiData		<=	PG1P1WidthRegCmd;
		end	else	if	(cmdCnt	==	12)	begin
			DspSpiData		<=	PG1P2WidthRegCmd;
		end	else	if	(cmdCnt	==	13)	begin
			DspSpiData		<=	PG1P3WidthRegCmd;
		end	else	if	(cmdCnt	==	14)	begin
			DspSpiData		<=	PG1P123WidthRegCmd;
		end	else	if	(cmdCnt	==	15)	begin
			DspSpiData		<=	PG2P1DelayRegCmd;
		end	else	if	(cmdCnt	==	16)	begin
			DspSpiData		<=	PG2P2DelayRegCmd;
		end	else	if	(cmdCnt	==	17)	begin
			DspSpiData		<=	PG2P3DelayRegCmd;	
		end	else	if	(cmdCnt	==	18)	begin
			DspSpiData		<=	PG2P123DelayRegCmd;
		end	else	if	(cmdCnt	==	19)	begin
			DspSpiData		<=	PG2P1WidthRegCmd;
		end	else	if	(cmdCnt	==	20)	begin
			DspSpiData		<=	PG2P2WidthRegCmd;
		end	else	if	(cmdCnt	==	21)	begin
			DspSpiData		<=	PG2P3WidthRegCmd;
		end	else	if	(cmdCnt	==	22)	begin
			DspSpiData		<=	PG2P123WidthRegCmd;
		end	else	if	(cmdCnt	==	23)	begin
			DspSpiData		<=	PG3P1DelayRegCmd;
		end	else	if	(cmdCnt	==	24)	begin
			DspSpiData		<=	PG3P2DelayRegCmd;
		end	else	if	(cmdCnt	==	25)	begin
			DspSpiData		<=	PG3P3DelayRegCmd;	
		end	else	if	(cmdCnt	==	26)	begin
			DspSpiData		<=	PG3P123DelayRegCmd;
		end	else	if	(cmdCnt	==	27)	begin
			DspSpiData		<=	PG3P1WidthRegCmd;
		end	else	if	(cmdCnt	==	28)	begin
			DspSpiData		<=	PG3P2WidthRegCmd;
		end	else	if	(cmdCnt	==	29)	begin
			DspSpiData		<=	PG3P3WidthRegCmd;
		end	else	if	(cmdCnt	==	30)	begin
			DspSpiData		<=	PG3P123WidthRegCmd;
		end	else	if	(cmdCnt	==	31)	begin
			DspSpiData		<=	PG4P1DelayRegCmd;
		end	else	if	(cmdCnt	==	32)	begin
			DspSpiData		<=	PG4P2DelayRegCmd;
		end	else	if	(cmdCnt	==	33)	begin
			DspSpiData		<=	PG4P3DelayRegCmd;	
		end	else	if	(cmdCnt	==	34)	begin
			DspSpiData		<=	PG4P123DelayRegCmd;
		end	else	if	(cmdCnt	==	35)	begin
			DspSpiData		<=	PG4P1WidthRegCmd;
		end	else	if	(cmdCnt	==	36)	begin
			DspSpiData		<=	PG4P2WidthRegCmd;
		end	else	if	(cmdCnt	==	37)	begin
			DspSpiData		<=	PG4P3WidthRegCmd;
		end	else	if	(cmdCnt	==	38)	begin
			DspSpiData		<=	PG4P123WidthRegCmd;
		end	else	if	(cmdCnt	==	39)	begin
			DspSpiData		<=	PG1PNumRegCmd;
		end	else	if	(cmdCnt	==	40)	begin
			DspSpiData		<=	PG2PNumRegCmd;
		end	else	if	(cmdCnt	==	41)	begin
			DspSpiData		<=	PG3PNumRegCmd;
		end	else	if	(cmdCnt	==	42)	begin
			DspSpiData		<=	PG4PNumRegCmd;
		end	else	if	(cmdCnt	==	43)	begin
			DspSpiData		<=	PG12PNumRegCmd;
		end	else	if	(cmdCnt	==	44)	begin
			DspSpiData		<=	PG34GPNumRegCmd;
		end	else	if	(cmdCnt	==	45)	begin
			DspSpiData		<=	GGP1DelayRegCmd;
		end	else	if	(cmdCnt	==	46)	begin
			DspSpiData		<=	GGP2DelayRegCmd;
		end	else	if	(cmdCnt	==	47)	begin
			DspSpiData		<=	GGP3DelayRegCmd;
		end	else	if	(cmdCnt	==	48)	begin
			DspSpiData		<=	GGP123DelayRegCmd;
		end	else	if	(cmdCnt	==	49)	begin
			DspSpiData		<=	GGP1WidthRegCmd;
		end	else	if	(cmdCnt	==	50)	begin
			DspSpiData		<=	GGP2WidthRegCmd;
		end	else	if	(cmdCnt	==	51)	begin
			DspSpiData		<=	GGP3WidthRegCmd;
		end	else	if	(cmdCnt	==	52)	begin
			DspSpiData		<=	GGP123WidthRegCmd;
		end	else	if	(cmdCnt	==	53)	begin
			DspSpiData		<=	SSGP1DelayRegCmd;
		end	else	if	(cmdCnt	==	54)	begin
			DspSpiData		<=	SSGP2DelayRegCmd;
		end	else	if	(cmdCnt	==	55)	begin
			DspSpiData		<=	SSGP12DelNumRegCmd;
		end	else	if	(cmdCnt	==	56)	begin
			DspSpiData		<=	SSGPNumRegCmd;
		end	else	if	(cmdCnt	==	57)	begin
			DspSpiData		<=	RefSeqPerRegCmd;
		end	else	if	(cmdCnt	==	58)	begin
			DspSpiData		<=	MeasNumRegCmd;
		end else	if	(cmdCnt	==	59)	begin
			DspSpiData		<=	PulseMeasCtrlCmd;
		end	else	if	(cmdCnt	==	60)	begin
			DspSpiData		<=	FilterCorrCmdH;
		end else	if	(cmdCnt	==	61)	begin
			DspSpiData		<=	FilterCorrCmdL;
		end
	end	else	if	(txCurrState	==	TX)	begin
		DspSpiData	<=	DspSpiData<<1;
	end
end

always	@(posedge Clk41)	begin
	if	(txCurrState	==	TX)	begin
		if	(txCnt	>=	7'd0)	begin
			mosi_i	<=	DspSpiData[31];
		end	else	begin
			mosi_i	<=	1'b1;
		end
	end	else	begin
		mosi_i	<=	1'b1;
	end
end

always	@(posedge	Clk41)	begin
	if	(txCurrState	==	TX)	begin
		ss_i	<=	1'b0;
	end	else	begin
		ss_i	<=	1'b1;
	end
end

assign	sck_i	=	Clk41;

always	@(posedge	Clk41)	begin
	if	(rst)	begin
		txCurrState	<=	IDLE;
	end	else	begin
		txCurrState	<=	txNextState;
	end
end


always @(*) begin
	txNextState	=	IDLE;
	case(txCurrState)
	IDLE	:	begin
					if (txWork)	begin
						txNextState = CMD;
					end	else begin
						txNextState = IDLE;
					end
				end
				
	CMD	:		begin
					if (!txStop)	begin
						txNextState = TX;
					end	else begin
						txNextState = IDLE;
					end
				end

	TX		:	begin
					if (txCnt==6'd31) begin
						txNextState  = PAUSE;
					end	else begin
						txNextState  = TX;
					end
				end
        
	PAUSE	:	begin
					if (pauseCnt==4'd10) begin
						txNextState  = CMD;
					end	else begin
						txNextState  = PAUSE;
					end
				end
	endcase
end























endmodule