TriggerCtrlTb.v 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231
  1. `timescale 1ns / 1ps
  2. module TriggerCtrlTb;
  3. parameter [31:0] DirectWriteCmd = {1'b0,7'h13,24'h5};
  4. parameter [31:0] NotDirectWriteCmd = {1'b0,7'h9,24'h5};
  5. parameter [31:0] DirectReadCmd = {1'b1,7'h13,24'h5};
  6. parameter [31:0] NotDirectReadCmd = {1'b1,7'h10,24'b1};
  7. parameter [31:0] DirectReadAns = {1'b0,7'h13,24'h5};
  8. parameter [31:0] ExtPosTrig0Cmd = {8'hE,16'h32,8'h7};
  9. parameter [31:0] ExtNegTrig0Cmd = {8'hE,16'h32,8'h5};
  10. parameter [31:0] IntPosTrig0Cmd = {8'hE,16'h32,8'h3};
  11. parameter [31:0] IntNegTrig0Cmd = {8'hE,16'h32,8'h1};
  12. reg clk_50;
  13. reg [31:0] tb_cnt=4'd0;
  14. reg rst;
  15. reg mosi_i = 1'b0;
  16. reg Miso_i = 1'b0;
  17. reg ss_i;
  18. reg clk_i = 1'b0;
  19. wire sck_i = (tb_cnt >= 20 && tb_cnt < 52 |tb_cnt >= 110 && tb_cnt < 142|tb_cnt >= 200 && tb_cnt < 232|tb_cnt >= 300 && tb_cnt < 332|tb_cnt >= 400 && tb_cnt < 432) ? clk_i:1'b1;
  20. reg [31:0] DspSpiData;
  21. reg StartCalcCmdReg ;
  22. wire [35:0] sincos_value_transit;
  23. wire [13:0] cos_value = sincos_value_transit [35:22];
  24. wire [13:0] sin_value = sincos_value_transit [17:4];
  25. wire TrigFromExtDev = (tb_cnt == 60|tb_cnt == 160);
  26. wire TrigFromExtDSp = (tb_cnt == 250|tb_cnt == 350);
  27. //==========================================================================================
  28. //clocks gen
  29. always #10 clk_50 = ~clk_50;
  30. always #10 clk_i = ~clk_i;
  31. //==========================================================================================
  32. initial begin
  33. clk_50 = 1'b1;
  34. rst = 1'b1;
  35. StartCalcCmdReg = 1'b1;
  36. #100;
  37. rst = 1'b0;
  38. #100;
  39. StartCalcCmdReg = 1'b0;
  40. end
  41. always @(negedge clk_50) begin
  42. if (!rst) begin
  43. tb_cnt <= tb_cnt+1;
  44. end else begin
  45. tb_cnt <= 0;
  46. end
  47. end
  48. always @(posedge clk_50) begin
  49. if (tb_cnt >= 20 && tb_cnt < 52 |tb_cnt >= 110 && tb_cnt < 142|tb_cnt >= 200 && tb_cnt < 232|tb_cnt >= 300 && tb_cnt < 332|tb_cnt >= 400 && tb_cnt < 432) begin
  50. ss_i <= 1'b0;
  51. end else begin
  52. ss_i <= 1'b1;
  53. end
  54. end
  55. always @(posedge clk_50) begin
  56. if (tb_cnt == 19) begin
  57. DspSpiData <= ExtPosTrig0Cmd;
  58. end else if (tb_cnt == 109) begin
  59. DspSpiData <= ExtNegTrig0Cmd;
  60. end else if (tb_cnt == 199) begin
  61. DspSpiData <= IntPosTrig0Cmd;
  62. end else if (tb_cnt == 299) begin
  63. DspSpiData <= IntNegTrig0Cmd;
  64. end else if (tb_cnt == 399) begin
  65. DspSpiData <= ExtPosTrig0Cmd;
  66. end else begin
  67. DspSpiData <= DspSpiData<<1;
  68. end
  69. end
  70. always @(posedge clk_50) begin
  71. if (!rst) begin
  72. if (tb_cnt >= 20 && tb_cnt < 52 |tb_cnt >= 110 && tb_cnt < 142|tb_cnt >= 200 && tb_cnt < 232|tb_cnt >= 300 && tb_cnt < 332|tb_cnt >= 400 && tb_cnt < 432) begin
  73. mosi_i <= DspSpiData[31];
  74. end else begin
  75. mosi_i <= 1'b1;
  76. end
  77. end
  78. end
  79. always @(posedge clk_50) begin
  80. if (tb_cnt >= 100 && tb_cnt < 132) begin
  81. Miso_i <= DspSpiData[31];
  82. end else begin
  83. Miso_i <= 1'b1;
  84. end
  85. end
  86. reg [5:0] testCnt = 0;
  87. always @(posedge sck_i) begin
  88. if (~ss_i) begin
  89. testCnt <= testCnt +1;
  90. end
  91. end
  92. CordicNco
  93. #( .ODatWidth (14),
  94. .PhIncWidth (32),
  95. .IterNum (10),
  96. .EnSinN (0))
  97. ncoInst
  98. (
  99. .Clk_i (clk_50),
  100. .Rst_i (rst),
  101. .Val_i (1'b1),
  102. .PhaseInc_i (32'h25604189),
  103. .WindVal_i (1'b1),
  104. .WinType_i (),
  105. .Wind_o (),
  106. .Sin_o (sin_value),
  107. .Cos_o (),
  108. .Val_o ()
  109. );
  110. S5443Top uut (
  111. .Clk_i (clk_50),
  112. .Led_o (),
  113. //------------------------------------------
  114. .Adc1FclkP_i (),
  115. .Adc1FclkN_i (),
  116. .Adc1DataDa0P_i (),
  117. .Adc1DataDa0N_i (),
  118. .Adc1DataDa1P_i (),
  119. .Adc1DataDa1N_i (),
  120. .Adc1DataDb0P_i (),
  121. .Adc1DataDb0N_i (),
  122. .Adc1DataDb1P_i (),
  123. .Adc1DataDb1N_i (),
  124. //------------------------------------------
  125. .Adc2FclkP_i (),
  126. .Adc2FclkN_i (),
  127. .Adc2DataDa0P_i (),
  128. .Adc2DataDa0N_i (),
  129. .Adc2DataDa1P_i (),
  130. .Adc2DataDa1N_i (),
  131. .Adc2DataDb0P_i (),
  132. .Adc2DataDb0N_i (),
  133. .Adc2DataDb1P_i (),
  134. .Adc2DataDb1N_i (),
  135. //------------------------------------------
  136. .AdcInitMosi_o (),
  137. .AdcInitClk_o (),
  138. .Adc1InitCs_o (),
  139. .Adc2InitCs_o (),
  140. .AdcInitRst_o (),
  141. //------------------------------------------
  142. .Mosi_i (mosi_i),
  143. .Sck_i (sck_i),
  144. .Ss_i (ss_i),
  145. .Miso_i (Miso_i),
  146. .LpOutClk_o (),
  147. .LpOutFs_o (),
  148. .LpOutData_o (),
  149. //fpga-dsp signals
  150. .StartMeas_i (StartCalcCmdReg),
  151. .StartMeas_o (),
  152. .StopMeas_i (),
  153. .Stopmeas_o (),
  154. .EndMeas_o (),
  155. .TimersClk_o (),
  156. //trigger's
  157. .ExtDevTrig0_io (TrigFromExtDev),
  158. .ExtDevTrig0Dir_o (),
  159. .ExtDevTrig1_io (),
  160. .ExtDevTrig1Dir_o (),
  161. .ExtDspTrig0_io (TrigFromExtDSp),
  162. .ExtDspTrig0Dir_o (),
  163. .ExtDspTrig1_io (),
  164. .ExtDspTrig1Dir_o (),
  165. //overload lines
  166. .Overload_o (),
  167. .OverloadS_i (),
  168. //gain lines
  169. .GainControl_o ()// 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  170. );
  171. endmodule