MeasDataFifo.v 15 KB

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  2. //
  3. // This file contains confidential and proprietary information
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  5. // international copyright and other intellectual property
  6. // laws.
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  10. // rights to the materials distributed herewith. Except as
  11. // otherwise provided in a valid license issued to you by
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  13. // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
  14. // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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  28. // possibility of the same.
  29. //
  30. // CRITICAL APPLICATIONS
  31. // Xilinx products are not designed or intended to be fail-
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  33. // performance, such as life-support or safety devices or
  34. // systems, Class III medical devices, nuclear facilities,
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  36. // other applications that could lead to death, personal
  37. // injury, or severe property or environmental damage
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  39. // Applications"). Customer assumes the sole risk and
  40. // liability of any use of Xilinx products in Critical
  41. // Applications, subject only to applicable laws and
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  43. //
  44. // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
  45. // PART OF THIS FILE AT ALL TIMES.
  46. //
  47. // DO NOT MODIFY THIS FILE.
  48. // IP VLNV: xilinx.com:ip:fifo_generator:13.2
  49. // IP Revision: 5
  50. `timescale 1ns/1ps
  51. (* DowngradeIPIdentifiedWarnings = "yes" *)
  52. module MeasDataFifo (
  53. clk,
  54. srst,
  55. din,
  56. wr_en,
  57. rd_en,
  58. dout,
  59. full,
  60. empty
  61. );
  62. (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
  63. (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 core_clk CLK" *)
  64. input wire clk;
  65. input wire srst;
  66. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
  67. input wire [255 : 0] din;
  68. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
  69. input wire wr_en;
  70. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
  71. input wire rd_en;
  72. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
  73. output wire [255 : 0] dout;
  74. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
  75. output wire full;
  76. (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
  77. output wire empty;
  78. fifo_generator_v13_2_5 #(
  79. .C_COMMON_CLOCK(1),
  80. .C_SELECT_XPM(0),
  81. .C_COUNT_TYPE(0),
  82. .C_DATA_COUNT_WIDTH(12),
  83. .C_DEFAULT_VALUE("BlankString"),
  84. .C_DIN_WIDTH(256),
  85. .C_DOUT_RST_VAL("0"),
  86. .C_DOUT_WIDTH(256),
  87. .C_ENABLE_RLOCS(0),
  88. .C_FAMILY("spartan7"),
  89. .C_FULL_FLAGS_RST_VAL(0),
  90. .C_HAS_ALMOST_EMPTY(0),
  91. .C_HAS_ALMOST_FULL(0),
  92. .C_HAS_BACKUP(0),
  93. .C_HAS_DATA_COUNT(0),
  94. .C_HAS_INT_CLK(0),
  95. .C_HAS_MEMINIT_FILE(0),
  96. .C_HAS_OVERFLOW(0),
  97. .C_HAS_RD_DATA_COUNT(0),
  98. .C_HAS_RD_RST(0),
  99. .C_HAS_RST(0),
  100. .C_HAS_SRST(1),
  101. .C_HAS_UNDERFLOW(0),
  102. .C_HAS_VALID(0),
  103. .C_HAS_WR_ACK(0),
  104. .C_HAS_WR_DATA_COUNT(0),
  105. .C_HAS_WR_RST(0),
  106. .C_IMPLEMENTATION_TYPE(0),
  107. .C_INIT_WR_PNTR_VAL(0),
  108. .C_MEMORY_TYPE(1),
  109. .C_MIF_FILE_NAME("BlankString"),
  110. .C_OPTIMIZATION_MODE(0),
  111. .C_OVERFLOW_LOW(0),
  112. .C_PRELOAD_LATENCY(1),
  113. .C_PRELOAD_REGS(0),
  114. .C_PRIM_FIFO_TYPE("4kx9"),
  115. .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
  116. .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
  117. .C_PROG_EMPTY_TYPE(0),
  118. .C_PROG_FULL_THRESH_ASSERT_VAL(4094),
  119. .C_PROG_FULL_THRESH_NEGATE_VAL(4093),
  120. .C_PROG_FULL_TYPE(0),
  121. .C_RD_DATA_COUNT_WIDTH(12),
  122. .C_RD_DEPTH(4096),
  123. .C_RD_FREQ(1),
  124. .C_RD_PNTR_WIDTH(12),
  125. .C_UNDERFLOW_LOW(0),
  126. .C_USE_DOUT_RST(1),
  127. .C_USE_ECC(0),
  128. .C_USE_EMBEDDED_REG(0),
  129. .C_USE_PIPELINE_REG(0),
  130. .C_POWER_SAVING_MODE(0),
  131. .C_USE_FIFO16_FLAGS(0),
  132. .C_USE_FWFT_DATA_COUNT(0),
  133. .C_VALID_LOW(0),
  134. .C_WR_ACK_LOW(0),
  135. .C_WR_DATA_COUNT_WIDTH(12),
  136. .C_WR_DEPTH(4096),
  137. .C_WR_FREQ(1),
  138. .C_WR_PNTR_WIDTH(12),
  139. .C_WR_RESPONSE_LATENCY(1),
  140. .C_MSGON_VAL(1),
  141. .C_ENABLE_RST_SYNC(1),
  142. .C_EN_SAFETY_CKT(0),
  143. .C_ERROR_INJECTION_TYPE(0),
  144. .C_SYNCHRONIZER_STAGE(2),
  145. .C_INTERFACE_TYPE(0),
  146. .C_AXI_TYPE(1),
  147. .C_HAS_AXI_WR_CHANNEL(1),
  148. .C_HAS_AXI_RD_CHANNEL(1),
  149. .C_HAS_SLAVE_CE(0),
  150. .C_HAS_MASTER_CE(0),
  151. .C_ADD_NGC_CONSTRAINT(0),
  152. .C_USE_COMMON_OVERFLOW(0),
  153. .C_USE_COMMON_UNDERFLOW(0),
  154. .C_USE_DEFAULT_SETTINGS(0),
  155. .C_AXI_ID_WIDTH(1),
  156. .C_AXI_ADDR_WIDTH(32),
  157. .C_AXI_DATA_WIDTH(64),
  158. .C_AXI_LEN_WIDTH(8),
  159. .C_AXI_LOCK_WIDTH(1),
  160. .C_HAS_AXI_ID(0),
  161. .C_HAS_AXI_AWUSER(0),
  162. .C_HAS_AXI_WUSER(0),
  163. .C_HAS_AXI_BUSER(0),
  164. .C_HAS_AXI_ARUSER(0),
  165. .C_HAS_AXI_RUSER(0),
  166. .C_AXI_ARUSER_WIDTH(1),
  167. .C_AXI_AWUSER_WIDTH(1),
  168. .C_AXI_WUSER_WIDTH(1),
  169. .C_AXI_BUSER_WIDTH(1),
  170. .C_AXI_RUSER_WIDTH(1),
  171. .C_HAS_AXIS_TDATA(1),
  172. .C_HAS_AXIS_TID(0),
  173. .C_HAS_AXIS_TDEST(0),
  174. .C_HAS_AXIS_TUSER(1),
  175. .C_HAS_AXIS_TREADY(1),
  176. .C_HAS_AXIS_TLAST(0),
  177. .C_HAS_AXIS_TSTRB(0),
  178. .C_HAS_AXIS_TKEEP(0),
  179. .C_AXIS_TDATA_WIDTH(8),
  180. .C_AXIS_TID_WIDTH(1),
  181. .C_AXIS_TDEST_WIDTH(1),
  182. .C_AXIS_TUSER_WIDTH(4),
  183. .C_AXIS_TSTRB_WIDTH(1),
  184. .C_AXIS_TKEEP_WIDTH(1),
  185. .C_WACH_TYPE(0),
  186. .C_WDCH_TYPE(0),
  187. .C_WRCH_TYPE(0),
  188. .C_RACH_TYPE(0),
  189. .C_RDCH_TYPE(0),
  190. .C_AXIS_TYPE(0),
  191. .C_IMPLEMENTATION_TYPE_WACH(1),
  192. .C_IMPLEMENTATION_TYPE_WDCH(1),
  193. .C_IMPLEMENTATION_TYPE_WRCH(1),
  194. .C_IMPLEMENTATION_TYPE_RACH(1),
  195. .C_IMPLEMENTATION_TYPE_RDCH(1),
  196. .C_IMPLEMENTATION_TYPE_AXIS(1),
  197. .C_APPLICATION_TYPE_WACH(0),
  198. .C_APPLICATION_TYPE_WDCH(0),
  199. .C_APPLICATION_TYPE_WRCH(0),
  200. .C_APPLICATION_TYPE_RACH(0),
  201. .C_APPLICATION_TYPE_RDCH(0),
  202. .C_APPLICATION_TYPE_AXIS(0),
  203. .C_PRIM_FIFO_TYPE_WACH("512x36"),
  204. .C_PRIM_FIFO_TYPE_WDCH("1kx36"),
  205. .C_PRIM_FIFO_TYPE_WRCH("512x36"),
  206. .C_PRIM_FIFO_TYPE_RACH("512x36"),
  207. .C_PRIM_FIFO_TYPE_RDCH("1kx36"),
  208. .C_PRIM_FIFO_TYPE_AXIS("1kx18"),
  209. .C_USE_ECC_WACH(0),
  210. .C_USE_ECC_WDCH(0),
  211. .C_USE_ECC_WRCH(0),
  212. .C_USE_ECC_RACH(0),
  213. .C_USE_ECC_RDCH(0),
  214. .C_USE_ECC_AXIS(0),
  215. .C_ERROR_INJECTION_TYPE_WACH(0),
  216. .C_ERROR_INJECTION_TYPE_WDCH(0),
  217. .C_ERROR_INJECTION_TYPE_WRCH(0),
  218. .C_ERROR_INJECTION_TYPE_RACH(0),
  219. .C_ERROR_INJECTION_TYPE_RDCH(0),
  220. .C_ERROR_INJECTION_TYPE_AXIS(0),
  221. .C_DIN_WIDTH_WACH(1),
  222. .C_DIN_WIDTH_WDCH(64),
  223. .C_DIN_WIDTH_WRCH(2),
  224. .C_DIN_WIDTH_RACH(32),
  225. .C_DIN_WIDTH_RDCH(64),
  226. .C_DIN_WIDTH_AXIS(1),
  227. .C_WR_DEPTH_WACH(16),
  228. .C_WR_DEPTH_WDCH(1024),
  229. .C_WR_DEPTH_WRCH(16),
  230. .C_WR_DEPTH_RACH(16),
  231. .C_WR_DEPTH_RDCH(1024),
  232. .C_WR_DEPTH_AXIS(1024),
  233. .C_WR_PNTR_WIDTH_WACH(4),
  234. .C_WR_PNTR_WIDTH_WDCH(10),
  235. .C_WR_PNTR_WIDTH_WRCH(4),
  236. .C_WR_PNTR_WIDTH_RACH(4),
  237. .C_WR_PNTR_WIDTH_RDCH(10),
  238. .C_WR_PNTR_WIDTH_AXIS(10),
  239. .C_HAS_DATA_COUNTS_WACH(0),
  240. .C_HAS_DATA_COUNTS_WDCH(0),
  241. .C_HAS_DATA_COUNTS_WRCH(0),
  242. .C_HAS_DATA_COUNTS_RACH(0),
  243. .C_HAS_DATA_COUNTS_RDCH(0),
  244. .C_HAS_DATA_COUNTS_AXIS(0),
  245. .C_HAS_PROG_FLAGS_WACH(0),
  246. .C_HAS_PROG_FLAGS_WDCH(0),
  247. .C_HAS_PROG_FLAGS_WRCH(0),
  248. .C_HAS_PROG_FLAGS_RACH(0),
  249. .C_HAS_PROG_FLAGS_RDCH(0),
  250. .C_HAS_PROG_FLAGS_AXIS(0),
  251. .C_PROG_FULL_TYPE_WACH(0),
  252. .C_PROG_FULL_TYPE_WDCH(0),
  253. .C_PROG_FULL_TYPE_WRCH(0),
  254. .C_PROG_FULL_TYPE_RACH(0),
  255. .C_PROG_FULL_TYPE_RDCH(0),
  256. .C_PROG_FULL_TYPE_AXIS(0),
  257. .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
  258. .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
  259. .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
  260. .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
  261. .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
  262. .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
  263. .C_PROG_EMPTY_TYPE_WACH(0),
  264. .C_PROG_EMPTY_TYPE_WDCH(0),
  265. .C_PROG_EMPTY_TYPE_WRCH(0),
  266. .C_PROG_EMPTY_TYPE_RACH(0),
  267. .C_PROG_EMPTY_TYPE_RDCH(0),
  268. .C_PROG_EMPTY_TYPE_AXIS(0),
  269. .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
  270. .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
  271. .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
  272. .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
  273. .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
  274. .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
  275. .C_REG_SLICE_MODE_WACH(0),
  276. .C_REG_SLICE_MODE_WDCH(0),
  277. .C_REG_SLICE_MODE_WRCH(0),
  278. .C_REG_SLICE_MODE_RACH(0),
  279. .C_REG_SLICE_MODE_RDCH(0),
  280. .C_REG_SLICE_MODE_AXIS(0)
  281. ) inst (
  282. .backup(1'D0),
  283. .backup_marker(1'D0),
  284. .clk(clk),
  285. .rst(1'D0),
  286. .srst(srst),
  287. .wr_clk(1'D0),
  288. .wr_rst(1'D0),
  289. .rd_clk(1'D0),
  290. .rd_rst(1'D0),
  291. .din(din),
  292. .wr_en(wr_en),
  293. .rd_en(rd_en),
  294. .prog_empty_thresh(12'B0),
  295. .prog_empty_thresh_assert(12'B0),
  296. .prog_empty_thresh_negate(12'B0),
  297. .prog_full_thresh(12'B0),
  298. .prog_full_thresh_assert(12'B0),
  299. .prog_full_thresh_negate(12'B0),
  300. .int_clk(1'D0),
  301. .injectdbiterr(1'D0),
  302. .injectsbiterr(1'D0),
  303. .sleep(1'D0),
  304. .dout(dout),
  305. .full(full),
  306. .almost_full(),
  307. .wr_ack(),
  308. .overflow(),
  309. .empty(empty),
  310. .almost_empty(),
  311. .valid(),
  312. .underflow(),
  313. .data_count(),
  314. .rd_data_count(),
  315. .wr_data_count(),
  316. .prog_full(),
  317. .prog_empty(),
  318. .sbiterr(),
  319. .dbiterr(),
  320. .wr_rst_busy(),
  321. .rd_rst_busy(),
  322. .m_aclk(1'D0),
  323. .s_aclk(1'D0),
  324. .s_aresetn(1'D0),
  325. .m_aclk_en(1'D0),
  326. .s_aclk_en(1'D0),
  327. .s_axi_awid(1'B0),
  328. .s_axi_awaddr(32'B0),
  329. .s_axi_awlen(8'B0),
  330. .s_axi_awsize(3'B0),
  331. .s_axi_awburst(2'B0),
  332. .s_axi_awlock(1'B0),
  333. .s_axi_awcache(4'B0),
  334. .s_axi_awprot(3'B0),
  335. .s_axi_awqos(4'B0),
  336. .s_axi_awregion(4'B0),
  337. .s_axi_awuser(1'B0),
  338. .s_axi_awvalid(1'D0),
  339. .s_axi_awready(),
  340. .s_axi_wid(1'B0),
  341. .s_axi_wdata(64'B0),
  342. .s_axi_wstrb(8'B0),
  343. .s_axi_wlast(1'D0),
  344. .s_axi_wuser(1'B0),
  345. .s_axi_wvalid(1'D0),
  346. .s_axi_wready(),
  347. .s_axi_bid(),
  348. .s_axi_bresp(),
  349. .s_axi_buser(),
  350. .s_axi_bvalid(),
  351. .s_axi_bready(1'D0),
  352. .m_axi_awid(),
  353. .m_axi_awaddr(),
  354. .m_axi_awlen(),
  355. .m_axi_awsize(),
  356. .m_axi_awburst(),
  357. .m_axi_awlock(),
  358. .m_axi_awcache(),
  359. .m_axi_awprot(),
  360. .m_axi_awqos(),
  361. .m_axi_awregion(),
  362. .m_axi_awuser(),
  363. .m_axi_awvalid(),
  364. .m_axi_awready(1'D0),
  365. .m_axi_wid(),
  366. .m_axi_wdata(),
  367. .m_axi_wstrb(),
  368. .m_axi_wlast(),
  369. .m_axi_wuser(),
  370. .m_axi_wvalid(),
  371. .m_axi_wready(1'D0),
  372. .m_axi_bid(1'B0),
  373. .m_axi_bresp(2'B0),
  374. .m_axi_buser(1'B0),
  375. .m_axi_bvalid(1'D0),
  376. .m_axi_bready(),
  377. .s_axi_arid(1'B0),
  378. .s_axi_araddr(32'B0),
  379. .s_axi_arlen(8'B0),
  380. .s_axi_arsize(3'B0),
  381. .s_axi_arburst(2'B0),
  382. .s_axi_arlock(1'B0),
  383. .s_axi_arcache(4'B0),
  384. .s_axi_arprot(3'B0),
  385. .s_axi_arqos(4'B0),
  386. .s_axi_arregion(4'B0),
  387. .s_axi_aruser(1'B0),
  388. .s_axi_arvalid(1'D0),
  389. .s_axi_arready(),
  390. .s_axi_rid(),
  391. .s_axi_rdata(),
  392. .s_axi_rresp(),
  393. .s_axi_rlast(),
  394. .s_axi_ruser(),
  395. .s_axi_rvalid(),
  396. .s_axi_rready(1'D0),
  397. .m_axi_arid(),
  398. .m_axi_araddr(),
  399. .m_axi_arlen(),
  400. .m_axi_arsize(),
  401. .m_axi_arburst(),
  402. .m_axi_arlock(),
  403. .m_axi_arcache(),
  404. .m_axi_arprot(),
  405. .m_axi_arqos(),
  406. .m_axi_arregion(),
  407. .m_axi_aruser(),
  408. .m_axi_arvalid(),
  409. .m_axi_arready(1'D0),
  410. .m_axi_rid(1'B0),
  411. .m_axi_rdata(64'B0),
  412. .m_axi_rresp(2'B0),
  413. .m_axi_rlast(1'D0),
  414. .m_axi_ruser(1'B0),
  415. .m_axi_rvalid(1'D0),
  416. .m_axi_rready(),
  417. .s_axis_tvalid(1'D0),
  418. .s_axis_tready(),
  419. .s_axis_tdata(8'B0),
  420. .s_axis_tstrb(1'B0),
  421. .s_axis_tkeep(1'B0),
  422. .s_axis_tlast(1'D0),
  423. .s_axis_tid(1'B0),
  424. .s_axis_tdest(1'B0),
  425. .s_axis_tuser(4'B0),
  426. .m_axis_tvalid(),
  427. .m_axis_tready(1'D0),
  428. .m_axis_tdata(),
  429. .m_axis_tstrb(),
  430. .m_axis_tkeep(),
  431. .m_axis_tlast(),
  432. .m_axis_tid(),
  433. .m_axis_tdest(),
  434. .m_axis_tuser(),
  435. .axi_aw_injectsbiterr(1'D0),
  436. .axi_aw_injectdbiterr(1'D0),
  437. .axi_aw_prog_full_thresh(4'B0),
  438. .axi_aw_prog_empty_thresh(4'B0),
  439. .axi_aw_data_count(),
  440. .axi_aw_wr_data_count(),
  441. .axi_aw_rd_data_count(),
  442. .axi_aw_sbiterr(),
  443. .axi_aw_dbiterr(),
  444. .axi_aw_overflow(),
  445. .axi_aw_underflow(),
  446. .axi_aw_prog_full(),
  447. .axi_aw_prog_empty(),
  448. .axi_w_injectsbiterr(1'D0),
  449. .axi_w_injectdbiterr(1'D0),
  450. .axi_w_prog_full_thresh(10'B0),
  451. .axi_w_prog_empty_thresh(10'B0),
  452. .axi_w_data_count(),
  453. .axi_w_wr_data_count(),
  454. .axi_w_rd_data_count(),
  455. .axi_w_sbiterr(),
  456. .axi_w_dbiterr(),
  457. .axi_w_overflow(),
  458. .axi_w_underflow(),
  459. .axi_w_prog_full(),
  460. .axi_w_prog_empty(),
  461. .axi_b_injectsbiterr(1'D0),
  462. .axi_b_injectdbiterr(1'D0),
  463. .axi_b_prog_full_thresh(4'B0),
  464. .axi_b_prog_empty_thresh(4'B0),
  465. .axi_b_data_count(),
  466. .axi_b_wr_data_count(),
  467. .axi_b_rd_data_count(),
  468. .axi_b_sbiterr(),
  469. .axi_b_dbiterr(),
  470. .axi_b_overflow(),
  471. .axi_b_underflow(),
  472. .axi_b_prog_full(),
  473. .axi_b_prog_empty(),
  474. .axi_ar_injectsbiterr(1'D0),
  475. .axi_ar_injectdbiterr(1'D0),
  476. .axi_ar_prog_full_thresh(4'B0),
  477. .axi_ar_prog_empty_thresh(4'B0),
  478. .axi_ar_data_count(),
  479. .axi_ar_wr_data_count(),
  480. .axi_ar_rd_data_count(),
  481. .axi_ar_sbiterr(),
  482. .axi_ar_dbiterr(),
  483. .axi_ar_overflow(),
  484. .axi_ar_underflow(),
  485. .axi_ar_prog_full(),
  486. .axi_ar_prog_empty(),
  487. .axi_r_injectsbiterr(1'D0),
  488. .axi_r_injectdbiterr(1'D0),
  489. .axi_r_prog_full_thresh(10'B0),
  490. .axi_r_prog_empty_thresh(10'B0),
  491. .axi_r_data_count(),
  492. .axi_r_wr_data_count(),
  493. .axi_r_rd_data_count(),
  494. .axi_r_sbiterr(),
  495. .axi_r_dbiterr(),
  496. .axi_r_overflow(),
  497. .axi_r_underflow(),
  498. .axi_r_prog_full(),
  499. .axi_r_prog_empty(),
  500. .axis_injectsbiterr(1'D0),
  501. .axis_injectdbiterr(1'D0),
  502. .axis_prog_full_thresh(10'B0),
  503. .axis_prog_empty_thresh(10'B0),
  504. .axis_data_count(),
  505. .axis_wr_data_count(),
  506. .axis_rd_data_count(),
  507. .axis_sbiterr(),
  508. .axis_dbiterr(),
  509. .axis_overflow(),
  510. .axis_underflow(),
  511. .axis_prog_full(),
  512. .axis_prog_empty()
  513. );
  514. endmodule