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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 10:02:35 04/20/2020
- // Design Name:
- // Module Name: mult_module
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module ModOutMux
- #(
- parameter CmdDataRegWith = 24,
- parameter PGenNum = 4
- )
- (
- input Rst_i,
- input Clk_i,
-
- input [CmdDataRegWith-1:0] PMeasCtrl_i,
-
- input [PGenNum-1:0] Pulses_i,
- input Trig0_i,
- input Trig1_i,
-
- output Mod_o
- );
- //================================================================================
- // LOCALPARAM
- //================================================================================
- // REG/WIRE
-
- reg modOut;
-
- wire pulseMeasEn = PMeasCtrl_i[0];
- wire intExtSel = PMeasCtrl_i[4];
- wire extPortSel = PMeasCtrl_i[5];
- wire [PGenNum-1:0] pGenSel = PMeasCtrl_i[11:8];
- //================================================================================
- // ASSIGNMENTS
- assign Mod_o = modOut;
- //================================================================================
- // CODING
- always @(*) begin
- if (!Rst_i) begin
- if (pulseMeasEn) begin
- if (intExtSel) begin
- if (extPortSel) begin
- modOut <= Trig1_i;
- end else begin
- modOut <= Trig0_i;
- end
- end else begin
- modOut <= Pulses_i[pGenSel];
- end
- end else begin
- modOut <= 1'b0;
- end
- end else begin
- modOut <= 1'b0;
- end
- end
- endmodule
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