S5443TopSimpleMeasTb.v 19 KB

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  1. `timescale 1ns / 1ps
  2. //=============================================================================================================
  3. // Тестовая конфигурация:
  4. //
  5. // Режим измерения "Точка в импульсе".
  6. // Количество измерений = 1.
  7. // Выбраный фильтр = 2МГц.
  8. //
  9. // PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
  10. // PG2 -> модулятор. | Шаблон 1 имп.
  11. // PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
  12. // PG4 -> Gating Generator. | Шаблон 1 имп.
  13. //
  14. // Настройки мультиплексоров генераторов:
  15. // PG1MUX_OUT -> INT_TRIG.
  16. // PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
  17. // PG3MUX_OUT -> PG1.
  18. // PG4MUX_OUT -> PG1.
  19. // PG5MUX_OUT -> PG1.
  20. // PG6MUX_OUT -> PG1.
  21. // PG7MUX_OUT -> PG1.
  22. //
  23. // Настройки остальных мультиплексоров:
  24. // MODMUX_OUT -> PG2.
  25. // GATINGMUX_OUT -> PG4.
  26. // SAMPLSTROBEMUX_OUT -> PG3.
  27. // EXTSTARTMUX -> DSPSTART.
  28. //=============================================================================================================
  29. module S5443TopSimpleMeasTb;
  30. localparam [31:0] FIRST = {4'b0,14'h2000,14'h2000};
  31. localparam [31:0] SECOND = {4'b0,14'h1fff,14'h2000};
  32. localparam [31:0] THIRD = {4'b0,14'h1fff,14'h1fff};
  33. localparam [31:0] FOURTH = {4'b0,14'h2000,14'h1fff};
  34. localparam [3:0] EP1MUXCMD = 4'd1;
  35. localparam [3:0] EP2MUXCMD = 4'd1;
  36. localparam [3:0] EP3MUXCMD = 4'd1;
  37. localparam [3:0] EP4MUXCMD = 4'd1;
  38. localparam [3:0] EP5MUXCMD = 4'd1;
  39. localparam [3:0] EP6MUXCMD = 4'd1;
  40. localparam [3:0] PG1MUXCMD = 4'd13;
  41. localparam [3:0] PG2MUXCMD = 4'd0;
  42. localparam [3:0] PG3MUXCMD = 4'd0;
  43. localparam [3:0] PG4MUXCMD = 4'd0;
  44. localparam [3:0] PG5MUXCMD = 4'd0;
  45. localparam [3:0] PG6MUXCMD = 4'd0;
  46. localparam [3:0] PG7MUXCMD = 4'd0;
  47. localparam [2:0] PG1MODE = 3'd1;
  48. localparam [2:0] PG2MODE = 3'd1;
  49. localparam [2:0] PG3MODE = 3'd1;
  50. localparam [2:0] PG4MODE = 3'd1;
  51. localparam [2:0] PG5MODE = 3'd0;
  52. localparam [2:0] PG6MODE = 3'd0;
  53. localparam [2:0] PG7MODE = 3'd0;
  54. localparam PG1POL = 1'b0;
  55. localparam PG2POL = 1'b1;
  56. localparam PG3POL = 1'b1;
  57. localparam PG4POL = 1'b0;
  58. localparam PG5POL = 1'b0;
  59. localparam PG6POL = 1'b0;
  60. localparam PG7POL = 1'b0;
  61. localparam [3:0] EXTTRIGMUXCMD = 4'd15;
  62. localparam [3:0] MODMUXCMD = 4'd1;
  63. localparam [3:0] GATINGMUXCMD = 4'd2;
  64. localparam [3:0] SMPLSTRBMUXCMD = 4'd3;
  65. localparam [3:0] DTIMUXCMD = 4'd7;
  66. //COMMANDS FOR REG_MAP
  67. parameter [31:0] MeasCmd = {8'h11,8'h1,8'h71,8'h0};
  68. parameter [31:0] SensCtrlCmd = {31'h0,1'b0};
  69. // parameter [31:0] MeasCmd = {8'h11,8'h0,8'h64,8'h0};
  70. parameter [31:0] AdcCtrl = {8'h12,24'h2};
  71. parameter [31:0] IfFtwH = {8'h15,16'h0,8'h38};
  72. parameter [31:0] IfFtwL = {8'h16,24'h51eb85};
  73. parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
  74. parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
  75. //PG7 Cmd
  76. parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
  77. parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd0};
  78. parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd0};
  79. parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd0};
  80. parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
  81. parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd0};
  82. parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd0};
  83. parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
  84. //PG1 Cmd
  85. parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
  86. parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd0};
  87. parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
  88. parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
  89. parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd1};
  90. parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
  91. parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
  92. parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
  93. //PG2 Cmd
  94. parameter [31:0] PG2P1DelayRegCmd = {8'h30,24'd0};
  95. parameter [31:0] PG2P2DelayRegCmd = {8'h31,24'd0};
  96. parameter [31:0] PG2P3DelayRegCmd = {8'h32,24'd0};
  97. parameter [31:0] PG2P123DelayRegCmd = {8'h33,24'd0};
  98. parameter [31:0] PG2P1WidthRegCmd = {8'h34,24'd1};
  99. parameter [31:0] PG2P2WidthRegCmd = {8'h35,24'd0};
  100. parameter [31:0] PG2P3WidthRegCmd = {8'h36,24'd0};
  101. parameter [31:0] PG2P123WidthRegCmd = {8'h37,24'd0};
  102. //PG3 Cmd
  103. parameter [31:0] PG3P1DelayRegCmd = {8'h38,24'd0};
  104. parameter [31:0] PG3P2DelayRegCmd = {8'h39,24'd0};
  105. parameter [31:0] PG3P3DelayRegCmd = {8'h3a,24'd0};
  106. parameter [31:0] PG3P123DelayRegCmd = {8'h3b,24'd0};
  107. parameter [31:0] PG3P1WidthRegCmd = {8'h3c,24'd1};
  108. parameter [31:0] PG3P2WidthRegCmd = {8'h3d,24'd0};
  109. parameter [31:0] PG3P3WidthRegCmd = {8'h3e,24'd0};
  110. parameter [31:0] PG3P123WidthRegCmd = {8'h3f,24'd0};
  111. //PG4 Cmd
  112. parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
  113. parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd0};
  114. parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
  115. parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
  116. parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd1};
  117. parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd0};
  118. parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd0};
  119. parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
  120. //PG5 Cmd
  121. parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
  122. parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
  123. parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
  124. parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
  125. parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd1};
  126. parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
  127. parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
  128. parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
  129. //PG6 Cmd
  130. parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd5};
  131. parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd15};
  132. parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd30};
  133. parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
  134. parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd5};
  135. parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd6};
  136. parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd7};
  137. parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
  138. parameter [31:0] MeasNum0RegCmd = {8'h58,24'd1};
  139. parameter [31:0] MeasNum1RegCmd = {8'h59,24'd0};
  140. parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
  141. parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'b0};
  142. parameter [31:0] MuxCtrl1RegCmd = {8'h1c,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD};
  143. parameter [31:0] MuxCtrl2RegCmd = {8'h1d,DTIMUXCMD,SMPLSTRBMUXCMD,GATINGMUXCMD,MODMUXCMD,EXTTRIGMUXCMD,PG7MUXCMD};
  144. parameter [31:0] MuxCtrl3RegCmd = {8'h1e,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD,EP2MUXCMD,EP1MUXCMD};
  145. //=================================================================================================================================================================================================================
  146. reg Clk41;
  147. reg Clk50;
  148. reg Clk70;
  149. reg [31:0] tb_cnt=4'd0;
  150. reg [31:0] tb_cnt1=4'd0;
  151. reg rst;
  152. reg mosi_i = 1'b0;
  153. reg Miso_i = 1'b0;
  154. reg ss_i;
  155. reg clk_i = 1'b0;
  156. reg [31:0] DspSpiData;
  157. reg startCalcCmdReg;
  158. wire startMeasS;
  159. wire [5:0] trig6to1_io;
  160. reg [5:0] trig6to1;
  161. wire [5:0] trigDir;
  162. wire [17:0] cos_value;
  163. wire [17:0] sin_value;
  164. wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
  165. wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
  166. wire ExtTrigger0 = ExtDspTrigNeg0;
  167. wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
  168. wire endMeas;
  169. reg [31:0] cmdCnt;
  170. reg trig0;
  171. reg trig1;
  172. reg dspTrigOut;
  173. reg sensEnReg;
  174. reg sensEnNewR;
  175. wire sensEnS;
  176. wire sensEnM;
  177. // trior sensEn;
  178. wire sensEn;
  179. pullup (sensEn);
  180. wand sensEnNew = sensEn;
  181. // wire sensEnPos = (sensEn&!sensEnReg);
  182. reg sensEnPos;
  183. //(tb_cnt1==32'd4283)?
  184. wire trig0R;
  185. wire trig1R;
  186. assign trig0R = trig0;
  187. assign trig1R = trig1;
  188. assign trig6to1_io[0] = (!trigDir[0])? trig6to1[0]:1'bz;
  189. assign trig6to1_io[1] = (!trigDir[1])? trig6to1[1]:1'bz;
  190. assign trig6to1_io[2] = (!trigDir[2])? trig6to1[2]:1'bz;
  191. assign trig6to1_io[3] = (!trigDir[3])? trig6to1[3]:1'bz;
  192. assign trig6to1_io[4] = (!trigDir[4])? trig6to1[4]:1'bz;
  193. assign trig6to1_io[5] = (!trigDir[5])? trig6to1[5]:1'bz;
  194. //==========================================================================================
  195. //clocks gen
  196. always #10 Clk50 = ~Clk50;
  197. always #(14.285714285714/2) Clk70 = ~Clk70;
  198. always #10 clk_i = ~clk_i;
  199. always #(24.390243902439/2) Clk41 = ~Clk41;
  200. wire sck_i;
  201. //==========================================================================================
  202. initial begin
  203. Clk50 = 1'b1;
  204. Clk70 = 1'b1;
  205. rst = 1'b1;
  206. Clk41 = 1'b0;
  207. trig0 = 1'b0;
  208. trig1 = 1'b0;
  209. trig6to1 = 6'b000000;
  210. #100;
  211. rst = 1'b0;
  212. #400;
  213. Clk41 = 1'b0;
  214. end
  215. // always @(*) begin
  216. // if (tb_cnt == 3501) begin
  217. // trig6to1 <= 6'b000001;
  218. // end else begin
  219. // trig6to1 <= 1'b000000;
  220. // end
  221. // end
  222. always @(*) begin
  223. if (tb_cnt == 3501) begin
  224. dspTrigOut <= 1'b1;
  225. end else begin
  226. dspTrigOut <= 1'b0;
  227. end
  228. end
  229. reg endMeasReg;
  230. always @(posedge Clk41) begin
  231. endMeasReg <= endMeas;
  232. end
  233. always @(posedge Clk50) begin
  234. if (!rst) begin
  235. sensEnReg <= sensEn;
  236. sensEnNewR <= sensEnNew;
  237. end else begin
  238. sensEnReg <= 0;
  239. sensEnNewR <= 0;
  240. end
  241. end
  242. always @(posedge Clk50) begin
  243. sensEnPos <= (sensEn&!sensEnReg);
  244. end
  245. wire endMeasNeg = !endMeas&endMeasReg;
  246. always @(posedge Clk70) begin
  247. if (!rst) begin
  248. if (!endMeas) begin
  249. if (tb_cnt == 3501) begin
  250. startCalcCmdReg <= 1'b1;
  251. end
  252. end else begin
  253. startCalcCmdReg <= 1'b0;
  254. end
  255. end else begin
  256. startCalcCmdReg <= 1'b0;
  257. end
  258. end
  259. always @(negedge Clk41) begin
  260. if (!rst) begin
  261. tb_cnt <= tb_cnt+1;
  262. end else begin
  263. tb_cnt <= 0;
  264. end
  265. end
  266. always @(posedge Clk50) begin
  267. if (!rst) begin
  268. tb_cnt1 <= tb_cnt1+1;
  269. end else begin
  270. tb_cnt1 <= 0;
  271. end
  272. end
  273. wire Adc1DataDa0P;
  274. wire Adc1DataDa1P;
  275. // wire [31:0] test = 32'h2351eb85;
  276. wire [31:0] test = 32'h3851eb85;
  277. CordicNco
  278. #( .ODatWidth (18),
  279. .PhIncWidth (32),
  280. .IterNum (10),
  281. .EnSinN (0))
  282. ncoInst
  283. (
  284. .Clk_i (Clk50),
  285. .Rst_i (rst),
  286. .Val_i (1'b1),
  287. .PhaseInc_i (test),
  288. .WindVal_i (1'b1),
  289. .WinType_i (),
  290. .Wind_o (),
  291. .Sin_o (sin_value),
  292. .Cos_o (cos_value),
  293. .Val_o ()
  294. );
  295. S5243Top MasterFpga
  296. (
  297. .ClkP_i (Clk50),
  298. .ClkN_i (~Clk50),
  299. .Led_o (),
  300. //------------------------------------------
  301. .Adc1FclkP_i (),
  302. .Adc1FclkN_i (),
  303. .Adc1DataDa0P_i (Adc1DataDa0P),
  304. .Adc1DataDa0N_i (~Adc1DataDa0P),
  305. .Adc1DataDa1P_i (Adc1DataDa1P),
  306. .Adc1DataDa1N_i (~Adc1DataDa1P),
  307. .Adc1DataDb0P_i (Adc1DataDa0P),
  308. .Adc1DataDb0N_i (~Adc1DataDa0P),
  309. .Adc1DataDb1P_i (Adc1DataDa1P),
  310. .Adc1DataDb1N_i (~Adc1DataDa1P),
  311. //------------------------------------------
  312. .Adc2FclkP_i (),
  313. .Adc2FclkN_i (),
  314. .Adc2DataDa0P_i (1'b1),
  315. .Adc2DataDa0N_i (1'b0),
  316. .Adc2DataDa1P_i (1'b1),
  317. .Adc2DataDa1N_i (1'b0),
  318. .Adc2DataDb0P_i (1'b1),
  319. .Adc2DataDb0N_i (1'b0),
  320. .Adc2DataDb1P_i (1'b1),
  321. .Adc2DataDb1N_i (1'b0),
  322. //------------------------------------------
  323. // .AdcInitMosi_o (),
  324. // .AdcInitClk_o (),
  325. .Adc1InitCs_o (),
  326. .Adc2InitCs_o (),
  327. // .AdcInitRst_o (),
  328. //------------------------------------------
  329. .Mosi_i (mosi_i),
  330. .Sck_i (~sck_i),
  331. .Ss_i (ss_i),
  332. .LpOutClk_o (),
  333. .LpOutFs_o (),
  334. .LpOutData_o (),
  335. //fpga-dsp signals
  336. .StartMeas_i (startCalcCmdReg),
  337. // .StartMeasEvent_o (startMeasS),
  338. .EndMeas_o (endMeas),
  339. .TimersClk_o (),
  340. .Trig6to1_io (),
  341. .Trig6to1Dir_o (),
  342. .DspTrigOut_i (Clk41), //Trig from DSP
  343. .DspTrigIn_o (), //Trig To DSP
  344. // .OverloadS_i (1'b0),
  345. .Overload_o (),
  346. .PortSel_o (),
  347. // .PortSelDir_o (),
  348. //mod out line
  349. .Mod_o (),
  350. //gain lines
  351. .DspReadyForRx_i (1'b0),
  352. // .DspReadyForRxToFpgaS_o (),
  353. .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  354. .AdcData_i (sin_value[17-:14])
  355. // .AdcData_i (Data_i)
  356. );
  357. parameter IDLE = 2'h0;
  358. parameter CMD = 2'h1;
  359. parameter TX = 2'h2;
  360. parameter PAUSE = 2'h3;
  361. reg [1:0] txCurrState;
  362. reg [1:0] txNextState;
  363. wire txWork = tb_cnt >= 23;
  364. wire txStop = cmdCnt >= 69;
  365. reg [6:0] txCnt;
  366. reg [3:0] pauseCnt;
  367. always @(posedge Clk41) begin
  368. if (!rst) begin
  369. if (txCurrState == CMD) begin
  370. if (!txStop) begin
  371. cmdCnt <= cmdCnt+1;
  372. end
  373. end
  374. end else begin
  375. cmdCnt <= 0;
  376. end
  377. end
  378. always @(posedge Clk41) begin
  379. if (!rst) begin
  380. if (txCurrState == TX) begin
  381. txCnt <= txCnt+1;
  382. end else begin
  383. txCnt <= 0;
  384. end
  385. end else begin
  386. txCnt <= 0;
  387. end
  388. end
  389. always @(posedge Clk41) begin
  390. if (!rst) begin
  391. if (txCurrState == PAUSE) begin
  392. pauseCnt <= pauseCnt+1;
  393. end else begin
  394. pauseCnt <= 0;
  395. end
  396. end else begin
  397. pauseCnt <= 0;
  398. end
  399. end
  400. always @(posedge Clk41) begin
  401. if (txCurrState == CMD) begin
  402. if (cmdCnt == 0) begin
  403. DspSpiData <= MeasCmd;
  404. end else if (cmdCnt == 1) begin
  405. DspSpiData <= IfFtwH;
  406. end else if (cmdCnt == 2) begin
  407. DspSpiData <= IfFtwL;
  408. end else if (cmdCnt == 3) begin
  409. DspSpiData <= FilterCorrCmdH;
  410. end else if (cmdCnt == 4) begin
  411. DspSpiData <= FilterCorrCmdL;
  412. end else if (cmdCnt == 5) begin
  413. DspSpiData <= PG1P1DelayRegCmd;
  414. end else if (cmdCnt == 6) begin
  415. DspSpiData <= PG1P2DelayRegCmd;
  416. end else if (cmdCnt == 7) begin
  417. DspSpiData <= PG1P3DelayRegCmd;
  418. end else if (cmdCnt == 8) begin
  419. DspSpiData <= PG1P123DelayRegCmd;
  420. end else if (cmdCnt == 9) begin
  421. DspSpiData <= PG1P1WidthRegCmd;
  422. end else if (cmdCnt == 10) begin
  423. DspSpiData <= PG1P2WidthRegCmd;
  424. end else if (cmdCnt == 11) begin
  425. DspSpiData <= PG1P3WidthRegCmd;
  426. end else if (cmdCnt == 12) begin
  427. DspSpiData <= PG1P123WidthRegCmd;
  428. end else if (cmdCnt == 13) begin
  429. DspSpiData <= PG2P1DelayRegCmd;
  430. end else if (cmdCnt == 14) begin
  431. DspSpiData <= PG2P2DelayRegCmd;
  432. end else if (cmdCnt == 15) begin
  433. DspSpiData <= PG2P3DelayRegCmd;
  434. end else if (cmdCnt == 16) begin
  435. DspSpiData <= PG2P123DelayRegCmd;
  436. end else if (cmdCnt == 17) begin
  437. DspSpiData <= PG2P1WidthRegCmd;
  438. end else if (cmdCnt == 18) begin
  439. DspSpiData <= PG2P2WidthRegCmd;
  440. end else if (cmdCnt == 19) begin
  441. DspSpiData <= PG2P3WidthRegCmd;
  442. end else if (cmdCnt == 20) begin
  443. DspSpiData <= PG2P123WidthRegCmd;
  444. end else if (cmdCnt == 21) begin
  445. DspSpiData <= PG3P1DelayRegCmd;
  446. end else if (cmdCnt == 22) begin
  447. DspSpiData <= PG3P2DelayRegCmd;
  448. end else if (cmdCnt == 23) begin
  449. DspSpiData <= PG3P3DelayRegCmd;
  450. end else if (cmdCnt == 24) begin
  451. DspSpiData <= PG3P123DelayRegCmd;
  452. end else if (cmdCnt == 25) begin
  453. DspSpiData <= PG3P1WidthRegCmd;
  454. end else if (cmdCnt == 26) begin
  455. DspSpiData <= PG3P2WidthRegCmd;
  456. end else if (cmdCnt == 27) begin
  457. DspSpiData <= PG3P3WidthRegCmd;
  458. end else if (cmdCnt == 28) begin
  459. DspSpiData <= PG3P123WidthRegCmd;
  460. end else if (cmdCnt == 29) begin
  461. DspSpiData <= PG4P1DelayRegCmd;
  462. end else if (cmdCnt == 30) begin
  463. DspSpiData <= PG4P2DelayRegCmd;
  464. end else if (cmdCnt == 31) begin
  465. DspSpiData <= PG4P3DelayRegCmd;
  466. end else if (cmdCnt == 32) begin
  467. DspSpiData <= PG4P123DelayRegCmd;
  468. end else if (cmdCnt == 33) begin
  469. DspSpiData <= PG4P1WidthRegCmd;
  470. end else if (cmdCnt == 34) begin
  471. DspSpiData <= PG4P2WidthRegCmd;
  472. end else if (cmdCnt == 35) begin
  473. DspSpiData <= PG4P3WidthRegCmd;
  474. end else if (cmdCnt == 36) begin
  475. DspSpiData <= PG4P123WidthRegCmd;
  476. end else if (cmdCnt == 37) begin
  477. DspSpiData <= PG5P1DelayRegCmd;
  478. end else if (cmdCnt == 38) begin
  479. DspSpiData <= PG5P2DelayRegCmd;
  480. end else if (cmdCnt == 39) begin
  481. DspSpiData <= PG5P3DelayRegCmd;
  482. end else if (cmdCnt == 40) begin
  483. DspSpiData <= PG5P123DelayRegCmd;
  484. end else if (cmdCnt == 41) begin
  485. DspSpiData <= PG5P1WidthRegCmd;
  486. end else if (cmdCnt == 42) begin
  487. DspSpiData <= PG5P2WidthRegCmd;
  488. end else if (cmdCnt == 43) begin
  489. DspSpiData <= PG5P3WidthRegCmd;
  490. end else if (cmdCnt == 44) begin
  491. DspSpiData <= PG5P123WidthRegCmd;
  492. end else if (cmdCnt == 45) begin
  493. DspSpiData <= PG6P1DelayRegCmd;
  494. end else if (cmdCnt == 46) begin
  495. DspSpiData <= PG6P2DelayRegCmd;
  496. end else if (cmdCnt == 47) begin
  497. DspSpiData <= PG6P3DelayRegCmd;
  498. end else if (cmdCnt == 48) begin
  499. DspSpiData <= PG6P123DelayRegCmd;
  500. end else if (cmdCnt == 49) begin
  501. DspSpiData <= PG6P1WidthRegCmd;
  502. end else if (cmdCnt == 50) begin
  503. DspSpiData <= PG6P2WidthRegCmd;
  504. end else if (cmdCnt == 51) begin
  505. DspSpiData <= PG6P3WidthRegCmd;
  506. end else if (cmdCnt == 52) begin
  507. DspSpiData <= PG6P123WidthRegCmd;
  508. end else if (cmdCnt == 53) begin
  509. DspSpiData <= PG7P1DelayRegCmd;
  510. end else if (cmdCnt == 54) begin
  511. DspSpiData <= PG7P2DelayRegCmd;
  512. end else if (cmdCnt == 55) begin
  513. DspSpiData <= PG7P3DelayRegCmd;
  514. end else if (cmdCnt == 56) begin
  515. DspSpiData <= PG7P123DelayRegCmd;
  516. end else if (cmdCnt == 57) begin
  517. DspSpiData <= PG7P1WidthRegCmd;
  518. end else if (cmdCnt == 58) begin
  519. DspSpiData <= PG7P2WidthRegCmd;
  520. end else if (cmdCnt == 59) begin
  521. DspSpiData <= PG7P3WidthRegCmd;
  522. end else if (cmdCnt == 60) begin
  523. DspSpiData <= PG7P123WidthRegCmd;
  524. end else if (cmdCnt == 61) begin
  525. DspSpiData <= MeasNum0RegCmd;
  526. end else if (cmdCnt == 62) begin
  527. DspSpiData <= MeasNum1RegCmd;
  528. end else if (cmdCnt == 63) begin
  529. DspSpiData <= PGMode0RegCmd;
  530. end else if (cmdCnt == 64) begin
  531. DspSpiData <= PGMode1RegCmd;
  532. end else if (cmdCnt == 65) begin
  533. DspSpiData <= MuxCtrl1RegCmd;
  534. end else if (cmdCnt == 66) begin
  535. DspSpiData <= MuxCtrl2RegCmd;
  536. end else if (cmdCnt == 67) begin
  537. DspSpiData <= MuxCtrl3RegCmd;
  538. end else if (cmdCnt == 68) begin
  539. DspSpiData <= SensCtrlCmd;
  540. end
  541. end else if (txCurrState == TX) begin
  542. DspSpiData <= DspSpiData<<1;
  543. end
  544. end
  545. always @(posedge Clk41) begin
  546. if (txCurrState == TX) begin
  547. if (txCnt >= 7'd0) begin
  548. mosi_i <= DspSpiData[31];
  549. end else begin
  550. mosi_i <= 1'b1;
  551. end
  552. end else begin
  553. mosi_i <= 1'b1;
  554. end
  555. end
  556. always @(posedge Clk41) begin
  557. if (txCurrState == TX) begin
  558. ss_i <= 1'b0;
  559. end else begin
  560. ss_i <= 1'b1;
  561. end
  562. end
  563. assign sck_i = Clk41;
  564. always @(posedge Clk41) begin
  565. if (rst) begin
  566. txCurrState <= IDLE;
  567. end else begin
  568. txCurrState <= txNextState;
  569. end
  570. end
  571. always @(*) begin
  572. txNextState = IDLE;
  573. case(txCurrState)
  574. IDLE : begin
  575. if (txWork) begin
  576. txNextState = CMD;
  577. end else begin
  578. txNextState = IDLE;
  579. end
  580. end
  581. CMD : begin
  582. if (!txStop) begin
  583. txNextState = TX;
  584. end else begin
  585. txNextState = IDLE;
  586. end
  587. end
  588. TX : begin
  589. if (txCnt==6'd31) begin
  590. txNextState = PAUSE;
  591. end else begin
  592. txNextState = TX;
  593. end
  594. end
  595. PAUSE : begin
  596. if (pauseCnt==4'd10) begin
  597. txNextState = CMD;
  598. end else begin
  599. txNextState = PAUSE;
  600. end
  601. end
  602. endcase
  603. end
  604. endmodule