S5443/S5443_M/S5443.srcs/sources_1/new/TriggerCtrl/TriggerCtrlModule.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	TriggerCtrlModule	
#(	
	parameter	CmdDataRegWith	=	24
)	
(
	input	Rst_i,
	input	Clk_i,
	
	input	[CmdDataRegWith-1:0]	TrigCmd_i,
	
	input	TrigFromExtDev_i,		//trigger from some ext device
	input	TrigFromExtDsp_i,		//trigger from ext DSP

	output	IntTrigToDsp_o,		//trigger to ext DSP
	output	IntTrigToExtDev_o,	//trigger to some ext device
	
	output	DelayDoneFlag_o,
	output	TrigEn_o,
	output	TrigDir_o
);	

//================================================================================
//  LOCALPARAM
	localparam	DelayValueWidth	=	16;
//================================================================================
//  REG/WIRE
	reg	[DelayValueWidth-1:0]	delayCnt;
	
	wire	[DelayValueWidth-1:0]	delayValue	=	TrigCmd_i[CmdDataRegWith-1-:DelayValueWidth];
	
	wire	trigDir	=	TrigCmd_i[2];	//direction of the trigger 1-input trig (from ext dev) 0-output trig (to ext device)
	wire	trigPl	=	TrigCmd_i[1];	//polarity of the trigger	1-'1' active, 0-'0' active
	wire	trigEn	=	TrigCmd_i[0];	//using rigger or not
	
	reg	intTrigToDsp;
	reg	intTrigToExtDev;
	
	reg	extTrigPosReg;
	reg	extTrigNegReg;
	
	wire	extTrigPos	=	(trigDir)?	!extTrigPosReg&&TrigFromExtDev_i:!extTrigPosReg&&TrigFromExtDsp_i;
	wire	extTrigNeg	=	(trigDir)?	extTrigNegReg&&!TrigFromExtDev_i:extTrigNegReg&&!TrigFromExtDsp_i;
	
	wire	delayDoneFlag	=	delayCnt==delayValue-1;
	
	reg		delayStartFlag;
//================================================================================
//  ASSIGNMENTS
	assign	TrigDir_o	=	trigDir;

	assign	IntTrigToDsp_o		=	intTrigToDsp;
	assign	IntTrigToExtDev_o	=	intTrigToExtDev;
	
	assign	DelayDoneFlag_o	=	delayDoneFlag;
	assign	TrigEn_o		=	trigEn;
	assign	TrigDir_o		=	trigDir;
//================================================================================
//  CODING

	always	@(posedge	Clk_i)	begin
		if	(Rst_i||!trigEn)	begin
			extTrigPosReg	<=	1'bz;
			extTrigNegReg	<=	1'bz;
		end	else	begin
			if	(trigDir)	begin
				if	(trigPl)	begin
					extTrigPosReg	<=	TrigFromExtDev_i;
				end	else	begin
					extTrigNegReg	<=	TrigFromExtDev_i;
				end
			end	else	begin
				if	(trigPl)	begin
					extTrigPosReg	<=	TrigFromExtDsp_i;
				end	else	begin
					extTrigNegReg	<=	TrigFromExtDsp_i;
				end
			end
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(Rst_i)	begin
			delayStartFlag	<=	1'b0;
		end	else	begin
			if	(!delayDoneFlag)	begin
				if	(extTrigPos|extTrigNeg)	begin
					delayStartFlag	<=	1'b1;
				end	
			end	else	begin
				delayStartFlag	<=	1'b0;
			end
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(Rst_i|!trigEn)	begin
			delayCnt	<=	{DelayValueWidth{1'b0}};
		end	else	if	(delayStartFlag)	begin
			if	(!delayDoneFlag)	begin
				if	(delayCnt	!=	delayValue)	begin
					delayCnt	<=	delayCnt+{{{DelayValueWidth-1{1'b0}},1'b1}};
				end
			end	else	begin
				delayCnt	<=	{DelayValueWidth{1'b0}};
			end
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(Rst_i||!trigEn)	begin
			intTrigToDsp	<=	1'b0;
			intTrigToExtDev	<=	1'b0;
		end	else	begin
			if	(trigDir)	begin
				if	(delayDoneFlag)	begin			
					intTrigToDsp	<=	1'b1;
				end	else	begin
					intTrigToDsp	<=	1'b0;
				end
			end	else	begin
				if	(trigPl)	begin
					intTrigToExtDev	<=	1'b0;
				end	else	begin
					intTrigToExtDev	<=	1'b1;
				end
				
				if	(delayDoneFlag	&&	trigPl)	begin
					intTrigToExtDev	<=	1'b1;
				end	else	if	(delayDoneFlag	&&	!trigPl)	begin
					intTrigToExtDev	<=	1'b0;
				end
			end
		end
	end
	
endmodule