S5443TopSimpleMeasTb.v 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735
  1. `timescale 1ns / 1ps
  2. //=============================================================================================================
  3. // Тестовая конфигурация:
  4. //
  5. // Режим измерения "Точка в импульсе".
  6. // Количество измерений = 1.
  7. // Выбраный фильтр = 2МГц.
  8. //
  9. // PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
  10. // PG2 -> модулятор. | Шаблон 1 имп.
  11. // PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
  12. // PG4 -> Gating Generator. | Шаблон 1 имп.
  13. //
  14. // Настройки мультиплексоров генераторов:
  15. // PG1MUX_OUT -> INT_TRIG.
  16. // PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
  17. // PG3MUX_OUT -> PG1.
  18. // PG4MUX_OUT -> PG1.
  19. // PG5MUX_OUT -> PG1.
  20. // PG6MUX_OUT -> PG1.
  21. // PG7MUX_OUT -> PG1.
  22. //
  23. // Настройки остальных мультиплексоров:
  24. // MODMUX_OUT -> PG2.
  25. // GATINGMUX_OUT -> PG4.
  26. // SAMPLSTROBEMUX_OUT -> PG3.
  27. // EXTSTARTMUX -> DSPSTART.
  28. //=============================================================================================================
  29. module S5443TopSimpleMeasTb;
  30. localparam [31:0] FIRST = {4'b0,14'h2000,14'h2000};
  31. localparam [31:0] SECOND = {4'b0,14'h1fff,14'h2000};
  32. localparam [31:0] THIRD = {4'b0,14'h1fff,14'h1fff};
  33. localparam [31:0] FOURTH = {4'b0,14'h2000,14'h1fff};
  34. localparam [3:0] EP1MUXCMD = 4'd1;
  35. localparam [3:0] EP2MUXCMD = 4'd1;
  36. localparam [3:0] EP3MUXCMD = 4'd1;
  37. localparam [3:0] EP4MUXCMD = 4'd1;
  38. localparam [3:0] EP5MUXCMD = 4'd1;
  39. localparam [3:0] EP6MUXCMD = 4'd1;
  40. localparam [3:0] PG1MUXCMD = 4'd13;
  41. localparam [3:0] PG2MUXCMD = 4'd0;
  42. localparam [3:0] PG3MUXCMD = 4'd0;
  43. localparam [3:0] PG4MUXCMD = 4'd0;
  44. localparam [3:0] PG5MUXCMD = 4'd0;
  45. localparam [3:0] PG6MUXCMD = 4'd0;
  46. localparam [3:0] PG7MUXCMD = 4'd0;
  47. localparam [2:0] PG1MODE = 3'd1;
  48. localparam [2:0] PG2MODE = 3'd1;
  49. localparam [2:0] PG3MODE = 3'd1;
  50. localparam [2:0] PG4MODE = 3'd1;
  51. localparam [2:0] PG5MODE = 3'd0;
  52. localparam [2:0] PG6MODE = 3'd0;
  53. localparam [2:0] PG7MODE = 3'd0;
  54. localparam PG1POL = 1'b0;
  55. localparam PG2POL = 1'b1;
  56. localparam PG3POL = 1'b1;
  57. localparam PG4POL = 1'b0;
  58. localparam PG5POL = 1'b0;
  59. localparam PG6POL = 1'b0;
  60. localparam PG7POL = 1'b0;
  61. localparam [3:0] EXTTRIGMUXCMD = 4'd15;
  62. localparam [3:0] MODMUXCMD = 4'd1;
  63. localparam [3:0] GATINGMUXCMD = 4'd2;
  64. localparam [3:0] SMPLSTRBMUXCMD = 4'd3;
  65. localparam [3:0] DTIMUXCMD = 4'd7;
  66. //COMMANDS FOR REG_MAP
  67. parameter [31:0] MeasCmd = {8'h11,8'h1,8'h71,8'h0};
  68. parameter [31:0] SensCtrlCmd = {31'h0,1'b0};
  69. // parameter [31:0] MeasCmd = {8'h11,8'h0,8'h64,8'h0};
  70. parameter [31:0] AdcCtrl = {8'h12,24'h2};
  71. parameter [31:0] IfFtwH = {8'h15,16'h0,8'h38};
  72. parameter [31:0] IfFtwL = {8'h16,24'h51eb85};
  73. parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
  74. parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
  75. //PG7 Cmd
  76. parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
  77. parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd0};
  78. parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd0};
  79. parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd0};
  80. parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
  81. parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd0};
  82. parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd0};
  83. parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
  84. //PG1 Cmd
  85. parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
  86. parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd0};
  87. parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
  88. parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
  89. parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd1};
  90. parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
  91. parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
  92. parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
  93. //PG2 Cmd
  94. parameter [31:0] PG2P1DelayRegCmd = {8'h30,24'd0};
  95. parameter [31:0] PG2P2DelayRegCmd = {8'h31,24'd0};
  96. parameter [31:0] PG2P3DelayRegCmd = {8'h32,24'd0};
  97. parameter [31:0] PG2P123DelayRegCmd = {8'h33,24'd0};
  98. parameter [31:0] PG2P1WidthRegCmd = {8'h34,24'd1};
  99. parameter [31:0] PG2P2WidthRegCmd = {8'h35,24'd0};
  100. parameter [31:0] PG2P3WidthRegCmd = {8'h36,24'd0};
  101. parameter [31:0] PG2P123WidthRegCmd = {8'h37,24'd0};
  102. //PG3 Cmd
  103. parameter [31:0] PG3P1DelayRegCmd = {8'h38,24'd0};
  104. parameter [31:0] PG3P2DelayRegCmd = {8'h39,24'd0};
  105. parameter [31:0] PG3P3DelayRegCmd = {8'h3a,24'd0};
  106. parameter [31:0] PG3P123DelayRegCmd = {8'h3b,24'd0};
  107. parameter [31:0] PG3P1WidthRegCmd = {8'h3c,24'd1};
  108. parameter [31:0] PG3P2WidthRegCmd = {8'h3d,24'd0};
  109. parameter [31:0] PG3P3WidthRegCmd = {8'h3e,24'd0};
  110. parameter [31:0] PG3P123WidthRegCmd = {8'h3f,24'd0};
  111. //PG4 Cmd
  112. parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
  113. parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd0};
  114. parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
  115. parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
  116. parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd1};
  117. parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd0};
  118. parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd0};
  119. parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
  120. //PG5 Cmd
  121. parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
  122. parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
  123. parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
  124. parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
  125. parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd1};
  126. parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
  127. parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
  128. parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
  129. //PG6 Cmd
  130. parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd5};
  131. parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd15};
  132. parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd30};
  133. parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
  134. parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd5};
  135. parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd6};
  136. parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd7};
  137. parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
  138. parameter [31:0] MeasNum0RegCmd = {8'h58,24'd1};
  139. parameter [31:0] MeasNum1RegCmd = {8'h59,24'd0};
  140. parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
  141. parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'b0};
  142. parameter [31:0] MuxCtrl1RegCmd = {8'h1c,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD};
  143. parameter [31:0] MuxCtrl2RegCmd = {8'h1d,DTIMUXCMD,SMPLSTRBMUXCMD,GATINGMUXCMD,MODMUXCMD,EXTTRIGMUXCMD,PG7MUXCMD};
  144. parameter [31:0] MuxCtrl3RegCmd = {8'h1e,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD,EP2MUXCMD,EP1MUXCMD};
  145. //=================================================================================================================================================================================================================
  146. reg Clk41;
  147. reg Clk50;
  148. reg Clk70;
  149. reg [31:0] tb_cnt=4'd0;
  150. reg [31:0] tb_cnt1=4'd0;
  151. reg rst;
  152. reg mosi_i = 1'b0;
  153. reg Miso_i = 1'b0;
  154. reg ss_i;
  155. reg clk_i = 1'b0;
  156. reg [31:0] DspSpiData;
  157. reg startCalcCmdReg;
  158. wire startMeasS;
  159. wire [5:0] trig6to1_io;
  160. reg [5:0] trig6to1;
  161. wire [5:0] trigDir;
  162. wire [17:0] cos_value;
  163. wire [17:0] sin_value;
  164. wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
  165. wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
  166. wire ExtTrigger0 = ExtDspTrigNeg0;
  167. wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
  168. wire endMeas;
  169. reg [31:0] cmdCnt;
  170. reg trig0;
  171. reg trig1;
  172. reg dspTrigOut;
  173. reg sensEnReg;
  174. reg sensEnNewR;
  175. wire sensEnS;
  176. wire sensEnM;
  177. // trior sensEn;
  178. wire sensEn;
  179. pullup (sensEn);
  180. wand sensEnNew = sensEn;
  181. // wire sensEnPos = (sensEn&!sensEnReg);
  182. reg sensEnPos;
  183. //(tb_cnt1==32'd4283)?
  184. wire trig0R;
  185. wire trig1R;
  186. assign trig0R = trig0;
  187. assign trig1R = trig1;
  188. assign trig6to1_io[0] = (!trigDir[0])? trig6to1[0]:1'bz;
  189. assign trig6to1_io[1] = (!trigDir[1])? trig6to1[1]:1'bz;
  190. assign trig6to1_io[2] = (!trigDir[2])? trig6to1[2]:1'bz;
  191. assign trig6to1_io[3] = (!trigDir[3])? trig6to1[3]:1'bz;
  192. assign trig6to1_io[4] = (!trigDir[4])? trig6to1[4]:1'bz;
  193. assign trig6to1_io[5] = (!trigDir[5])? trig6to1[5]:1'bz;
  194. //==========================================================================================
  195. //clocks gen
  196. always #10 Clk50 = ~Clk50;
  197. always #(14.285714285714/2) Clk70 = ~Clk70;
  198. always #10 clk_i = ~clk_i;
  199. always #(24.390243902439/2) Clk41 = ~Clk41;
  200. wire sck_i;
  201. //==========================================================================================
  202. initial begin
  203. Clk50 = 1'b1;
  204. Clk70 = 1'b1;
  205. rst = 1'b1;
  206. Clk41 = 1'b0;
  207. trig0 = 1'b0;
  208. trig1 = 1'b0;
  209. trig6to1 = 6'b000000;
  210. #100;
  211. rst = 1'b0;
  212. #400;
  213. Clk41 = 1'b0;
  214. end
  215. // always @(*) begin
  216. // if (tb_cnt == 3501) begin
  217. // trig6to1 <= 6'b000001;
  218. // end else begin
  219. // trig6to1 <= 1'b000000;
  220. // end
  221. // end
  222. always @(*) begin
  223. if (tb_cnt == 3501) begin
  224. dspTrigOut <= 1'b1;
  225. end else begin
  226. dspTrigOut <= 1'b0;
  227. end
  228. end
  229. reg endMeasReg;
  230. always @(posedge Clk41) begin
  231. endMeasReg <= endMeas;
  232. end
  233. always @(posedge Clk50) begin
  234. if (!rst) begin
  235. sensEnReg <= sensEn;
  236. sensEnNewR <= sensEnNew;
  237. end else begin
  238. sensEnReg <= 0;
  239. sensEnNewR <= 0;
  240. end
  241. end
  242. always @(posedge Clk50) begin
  243. sensEnPos <= (sensEn&!sensEnReg);
  244. end
  245. wire endMeasNeg = !endMeas&endMeasReg;
  246. always @(posedge Clk70) begin
  247. if (!rst) begin
  248. if (!endMeas) begin
  249. if (tb_cnt == 3501) begin
  250. startCalcCmdReg <= 1'b1;
  251. end
  252. end else begin
  253. startCalcCmdReg <= 1'b0;
  254. end
  255. end else begin
  256. startCalcCmdReg <= 1'b0;
  257. end
  258. end
  259. always @(negedge Clk41) begin
  260. if (!rst) begin
  261. tb_cnt <= tb_cnt+1;
  262. end else begin
  263. tb_cnt <= 0;
  264. end
  265. end
  266. always @(posedge Clk50) begin
  267. if (!rst) begin
  268. tb_cnt1 <= tb_cnt1+1;
  269. end else begin
  270. tb_cnt1 <= 0;
  271. end
  272. end
  273. wire Adc1DataDa0P;
  274. wire Adc1DataDa1P;
  275. // wire [31:0] test = 32'h2351eb85;
  276. wire [31:0] test = 32'h3851eb85;
  277. CordicNco
  278. #( .ODatWidth (18),
  279. .PhIncWidth (32),
  280. .IterNum (10),
  281. .EnSinN (0))
  282. ncoInst
  283. (
  284. .Clk_i (Clk50),
  285. .Rst_i (rst),
  286. .Val_i (1'b1),
  287. .PhaseInc_i (test),
  288. .WindVal_i (1'b1),
  289. .WinType_i (),
  290. .Wind_o (),
  291. .Sin_o (sin_value),
  292. .Cos_o (cos_value),
  293. .Val_o ()
  294. );
  295. S5443Top MasterFpga
  296. (
  297. .Clk_i (Clk50),
  298. .Led_o (),
  299. //------------------------------------------
  300. .Adc1FclkP_i (),
  301. .Adc1FclkN_i (),
  302. .Adc1DataDa0P_i (Adc1DataDa0P),
  303. .Adc1DataDa0N_i (~Adc1DataDa0P),
  304. .Adc1DataDa1P_i (Adc1DataDa1P),
  305. .Adc1DataDa1N_i (~Adc1DataDa1P),
  306. .Adc1DataDb0P_i (Adc1DataDa0P),
  307. .Adc1DataDb0N_i (~Adc1DataDa0P),
  308. .Adc1DataDb1P_i (Adc1DataDa1P),
  309. .Adc1DataDb1N_i (~Adc1DataDa1P),
  310. //------------------------------------------
  311. .Adc2FclkP_i (),
  312. .Adc2FclkN_i (),
  313. .Adc2DataDa0P_i (1'b1),
  314. .Adc2DataDa0N_i (1'b0),
  315. .Adc2DataDa1P_i (1'b1),
  316. .Adc2DataDa1N_i (1'b0),
  317. .Adc2DataDb0P_i (1'b1),
  318. .Adc2DataDb0N_i (1'b0),
  319. .Adc2DataDb1P_i (1'b1),
  320. .Adc2DataDb1N_i (1'b0),
  321. //------------------------------------------
  322. .AdcInitMosi_o (),
  323. .AdcInitClk_o (),
  324. .Adc1InitCs_o (),
  325. .Adc2InitCs_o (),
  326. .AdcInitRst_o (),
  327. //------------------------------------------
  328. .Mosi_i (mosi_i),
  329. .Sck_i (~sck_i),
  330. .Ss_i (ss_i),
  331. .LpOutClk_o (),
  332. .LpOutFs_o (),
  333. .LpOutData_o (),
  334. //fpga-dsp signals
  335. .StartMeas_i (startCalcCmdReg),
  336. .StartMeas_o (startMeasS),
  337. .EndMeas_o (endMeas),
  338. .TimersClk_o (),
  339. .Trig6to1_io (),
  340. .Trig6to1Dir_o (),
  341. .DspTrigOut_i (dspTrigOut), //Trig from DSP
  342. .DspTrigIn_o (), //Trig To DSP
  343. .OverloadS_i (1'b0),
  344. .Overload_o (),
  345. .PortSel_o (),
  346. .PortSelDir_o (),
  347. //mod out line
  348. .Mod_o (),
  349. //gain lines
  350. .SensEnM_io (sensEn),
  351. .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  352. .AdcData_i (sin_value[17-:14])
  353. );
  354. parameter IDLE = 2'h0;
  355. parameter CMD = 2'h1;
  356. parameter TX = 2'h2;
  357. parameter PAUSE = 2'h3;
  358. reg [1:0] txCurrState;
  359. reg [1:0] txNextState;
  360. wire txWork = tb_cnt >= 23;
  361. wire txStop = cmdCnt >= 69;
  362. reg [6:0] txCnt;
  363. reg [3:0] pauseCnt;
  364. always @(posedge Clk41) begin
  365. if (!rst) begin
  366. if (txCurrState == CMD) begin
  367. if (!txStop) begin
  368. cmdCnt <= cmdCnt+1;
  369. end
  370. end
  371. end else begin
  372. cmdCnt <= 0;
  373. end
  374. end
  375. always @(posedge Clk41) begin
  376. if (!rst) begin
  377. if (txCurrState == TX) begin
  378. txCnt <= txCnt+1;
  379. end else begin
  380. txCnt <= 0;
  381. end
  382. end else begin
  383. txCnt <= 0;
  384. end
  385. end
  386. always @(posedge Clk41) begin
  387. if (!rst) begin
  388. if (txCurrState == PAUSE) begin
  389. pauseCnt <= pauseCnt+1;
  390. end else begin
  391. pauseCnt <= 0;
  392. end
  393. end else begin
  394. pauseCnt <= 0;
  395. end
  396. end
  397. always @(posedge Clk41) begin
  398. if (txCurrState == CMD) begin
  399. if (cmdCnt == 0) begin
  400. DspSpiData <= MeasCmd;
  401. end else if (cmdCnt == 1) begin
  402. DspSpiData <= IfFtwH;
  403. end else if (cmdCnt == 2) begin
  404. DspSpiData <= IfFtwL;
  405. end else if (cmdCnt == 3) begin
  406. DspSpiData <= FilterCorrCmdH;
  407. end else if (cmdCnt == 4) begin
  408. DspSpiData <= FilterCorrCmdL;
  409. end else if (cmdCnt == 5) begin
  410. DspSpiData <= PG1P1DelayRegCmd;
  411. end else if (cmdCnt == 6) begin
  412. DspSpiData <= PG1P2DelayRegCmd;
  413. end else if (cmdCnt == 7) begin
  414. DspSpiData <= PG1P3DelayRegCmd;
  415. end else if (cmdCnt == 8) begin
  416. DspSpiData <= PG1P123DelayRegCmd;
  417. end else if (cmdCnt == 9) begin
  418. DspSpiData <= PG1P1WidthRegCmd;
  419. end else if (cmdCnt == 10) begin
  420. DspSpiData <= PG1P2WidthRegCmd;
  421. end else if (cmdCnt == 11) begin
  422. DspSpiData <= PG1P3WidthRegCmd;
  423. end else if (cmdCnt == 12) begin
  424. DspSpiData <= PG1P123WidthRegCmd;
  425. end else if (cmdCnt == 13) begin
  426. DspSpiData <= PG2P1DelayRegCmd;
  427. end else if (cmdCnt == 14) begin
  428. DspSpiData <= PG2P2DelayRegCmd;
  429. end else if (cmdCnt == 15) begin
  430. DspSpiData <= PG2P3DelayRegCmd;
  431. end else if (cmdCnt == 16) begin
  432. DspSpiData <= PG2P123DelayRegCmd;
  433. end else if (cmdCnt == 17) begin
  434. DspSpiData <= PG2P1WidthRegCmd;
  435. end else if (cmdCnt == 18) begin
  436. DspSpiData <= PG2P2WidthRegCmd;
  437. end else if (cmdCnt == 19) begin
  438. DspSpiData <= PG2P3WidthRegCmd;
  439. end else if (cmdCnt == 20) begin
  440. DspSpiData <= PG2P123WidthRegCmd;
  441. end else if (cmdCnt == 21) begin
  442. DspSpiData <= PG3P1DelayRegCmd;
  443. end else if (cmdCnt == 22) begin
  444. DspSpiData <= PG3P2DelayRegCmd;
  445. end else if (cmdCnt == 23) begin
  446. DspSpiData <= PG3P3DelayRegCmd;
  447. end else if (cmdCnt == 24) begin
  448. DspSpiData <= PG3P123DelayRegCmd;
  449. end else if (cmdCnt == 25) begin
  450. DspSpiData <= PG3P1WidthRegCmd;
  451. end else if (cmdCnt == 26) begin
  452. DspSpiData <= PG3P2WidthRegCmd;
  453. end else if (cmdCnt == 27) begin
  454. DspSpiData <= PG3P3WidthRegCmd;
  455. end else if (cmdCnt == 28) begin
  456. DspSpiData <= PG3P123WidthRegCmd;
  457. end else if (cmdCnt == 29) begin
  458. DspSpiData <= PG4P1DelayRegCmd;
  459. end else if (cmdCnt == 30) begin
  460. DspSpiData <= PG4P2DelayRegCmd;
  461. end else if (cmdCnt == 31) begin
  462. DspSpiData <= PG4P3DelayRegCmd;
  463. end else if (cmdCnt == 32) begin
  464. DspSpiData <= PG4P123DelayRegCmd;
  465. end else if (cmdCnt == 33) begin
  466. DspSpiData <= PG4P1WidthRegCmd;
  467. end else if (cmdCnt == 34) begin
  468. DspSpiData <= PG4P2WidthRegCmd;
  469. end else if (cmdCnt == 35) begin
  470. DspSpiData <= PG4P3WidthRegCmd;
  471. end else if (cmdCnt == 36) begin
  472. DspSpiData <= PG4P123WidthRegCmd;
  473. end else if (cmdCnt == 37) begin
  474. DspSpiData <= PG5P1DelayRegCmd;
  475. end else if (cmdCnt == 38) begin
  476. DspSpiData <= PG5P2DelayRegCmd;
  477. end else if (cmdCnt == 39) begin
  478. DspSpiData <= PG5P3DelayRegCmd;
  479. end else if (cmdCnt == 40) begin
  480. DspSpiData <= PG5P123DelayRegCmd;
  481. end else if (cmdCnt == 41) begin
  482. DspSpiData <= PG5P1WidthRegCmd;
  483. end else if (cmdCnt == 42) begin
  484. DspSpiData <= PG5P2WidthRegCmd;
  485. end else if (cmdCnt == 43) begin
  486. DspSpiData <= PG5P3WidthRegCmd;
  487. end else if (cmdCnt == 44) begin
  488. DspSpiData <= PG5P123WidthRegCmd;
  489. end else if (cmdCnt == 45) begin
  490. DspSpiData <= PG6P1DelayRegCmd;
  491. end else if (cmdCnt == 46) begin
  492. DspSpiData <= PG6P2DelayRegCmd;
  493. end else if (cmdCnt == 47) begin
  494. DspSpiData <= PG6P3DelayRegCmd;
  495. end else if (cmdCnt == 48) begin
  496. DspSpiData <= PG6P123DelayRegCmd;
  497. end else if (cmdCnt == 49) begin
  498. DspSpiData <= PG6P1WidthRegCmd;
  499. end else if (cmdCnt == 50) begin
  500. DspSpiData <= PG6P2WidthRegCmd;
  501. end else if (cmdCnt == 51) begin
  502. DspSpiData <= PG6P3WidthRegCmd;
  503. end else if (cmdCnt == 52) begin
  504. DspSpiData <= PG6P123WidthRegCmd;
  505. end else if (cmdCnt == 53) begin
  506. DspSpiData <= PG7P1DelayRegCmd;
  507. end else if (cmdCnt == 54) begin
  508. DspSpiData <= PG7P2DelayRegCmd;
  509. end else if (cmdCnt == 55) begin
  510. DspSpiData <= PG7P3DelayRegCmd;
  511. end else if (cmdCnt == 56) begin
  512. DspSpiData <= PG7P123DelayRegCmd;
  513. end else if (cmdCnt == 57) begin
  514. DspSpiData <= PG7P1WidthRegCmd;
  515. end else if (cmdCnt == 58) begin
  516. DspSpiData <= PG7P2WidthRegCmd;
  517. end else if (cmdCnt == 59) begin
  518. DspSpiData <= PG7P3WidthRegCmd;
  519. end else if (cmdCnt == 60) begin
  520. DspSpiData <= PG7P123WidthRegCmd;
  521. end else if (cmdCnt == 61) begin
  522. DspSpiData <= MeasNum0RegCmd;
  523. end else if (cmdCnt == 62) begin
  524. DspSpiData <= MeasNum1RegCmd;
  525. end else if (cmdCnt == 63) begin
  526. DspSpiData <= PGMode0RegCmd;
  527. end else if (cmdCnt == 64) begin
  528. DspSpiData <= PGMode1RegCmd;
  529. end else if (cmdCnt == 65) begin
  530. DspSpiData <= MuxCtrl1RegCmd;
  531. end else if (cmdCnt == 66) begin
  532. DspSpiData <= MuxCtrl2RegCmd;
  533. end else if (cmdCnt == 67) begin
  534. DspSpiData <= MuxCtrl3RegCmd;
  535. end else if (cmdCnt == 68) begin
  536. DspSpiData <= SensCtrlCmd;
  537. end
  538. end else if (txCurrState == TX) begin
  539. DspSpiData <= DspSpiData<<1;
  540. end
  541. end
  542. always @(posedge Clk41) begin
  543. if (txCurrState == TX) begin
  544. if (txCnt >= 7'd0) begin
  545. mosi_i <= DspSpiData[31];
  546. end else begin
  547. mosi_i <= 1'b1;
  548. end
  549. end else begin
  550. mosi_i <= 1'b1;
  551. end
  552. end
  553. always @(posedge Clk41) begin
  554. if (txCurrState == TX) begin
  555. ss_i <= 1'b0;
  556. end else begin
  557. ss_i <= 1'b1;
  558. end
  559. end
  560. assign sck_i = Clk41;
  561. always @(posedge Clk41) begin
  562. if (rst) begin
  563. txCurrState <= IDLE;
  564. end else begin
  565. txCurrState <= txNextState;
  566. end
  567. end
  568. always @(*) begin
  569. txNextState = IDLE;
  570. case(txCurrState)
  571. IDLE : begin
  572. if (txWork) begin
  573. txNextState = CMD;
  574. end else begin
  575. txNextState = IDLE;
  576. end
  577. end
  578. CMD : begin
  579. if (!txStop) begin
  580. txNextState = TX;
  581. end else begin
  582. txNextState = IDLE;
  583. end
  584. end
  585. TX : begin
  586. if (txCnt==6'd31) begin
  587. txNextState = PAUSE;
  588. end else begin
  589. txNextState = TX;
  590. end
  591. end
  592. PAUSE : begin
  593. if (pauseCnt==4'd10) begin
  594. txNextState = CMD;
  595. end else begin
  596. txNextState = PAUSE;
  597. end
  598. end
  599. endcase
  600. end
  601. endmodule