S5443/S5443_S/S5443.srcs/sources_1/new/Math/Mult_calc.v

`timescale 1ns / 1ps
	
module Mult_calc	(
	input			clk_i, 
	input			reset_i,
	input			[13:0]	adc_i,	
	input	[17:0]	sin_i, 
	input	[17:0]	cos_i,
	input			[17:0]	win_i,
	input			sum_en_i,	
	output	[39:0]	sum_re_o,
	output	[39:0]	sum_im_o
);
//================================================================================
//  REG/WIRE
//================================================================================

	wire	[47:0]	sum_cos;
	wire	[47:0]	sum_sin;		
	wire 			ovfl_sum_cos;	// Check For Overflow
	wire 			ovfl_sum_sin;
	reg[9:0] 		null_corr	= 10'b0;	// Êîððåêòèðîâêà íóëÿ
	
//================================================================================
//  ASSIGNMENTS
//================================================================================
	
	assign ovfl_sum_cos	= (sum_cos[41]^sum_cos[42])|(sum_cos[42]^sum_cos[43]);	// Check For Overflow
	assign ovfl_sum_sin	= (sum_sin[41]^sum_sin[42])|(sum_sin[42]^sum_sin[43]);	// Check For Overflow

	
	assign sum_re_o 	= (ovfl_sum_cos) ? { sum_cos[41],{39{~sum_cos[41]}}} : {sum_cos[40:1]};
	assign sum_im_o 	= (ovfl_sum_sin) ? { sum_sin[41],{39{~sum_sin[41]}}} : {sum_sin[40:1]};	
	//works for now 
	//======================================
	wire [35:0]	adc_wind;
//================================================================================
//  CODING
//================================================================================		
	
//Null correction * Window	
Dsp48Mult	NullCorrWind
(
  .CLK	(clk_i),
  .A	({{8{null_corr[9]}},null_corr[9:0]}),
  .B	(win_i),
  .C	(40'd0),
  .D	({adc_i[13:0],4'b0}),
  .P	(adc_wind)
);

	DSP48A1 #(
       .A0REG(0),              // First stage A input pipeline register (0/1)
       .A1REG(0),              // Second stage A input pipeline register (0/1)
       .B0REG(0),              // First stage B input pipeline register (0/1)
       .B1REG(0),              // Second stage B input pipeline register (0/1)
       .CARRYINREG(0),         // CARRYIN input pipeline register (0/1)
       .CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5" 
       .CARRYOUTREG(0),        // CARRYOUT output pipeline register (0/1)
       .CREG(1),               // C input pipeline register (0/1)
       .DREG(0),               // D pre-adder input pipeline register (0/1)
       .MREG(0),               // M pipeline register (0/1)
       .OPMODEREG(1),          // Enable=1/disable=0 OPMODE input pipeline registers
       .PREG(1),               // P output pipeline register (0/1)
       .RSTTYPE("SYNC")        // Specify reset type, "SYNC" or "ASYNC" 
    )
    DSP48A1_wind_cos (
	//  Cascade Ports: No Cascade
		.BCOUT(),   	   	   // 18-bit output: B port cascade output
		.PCOUT(), 	   	      // 48-bit output: P cascade output
	//   Data Ports: 1-bit (each) output: Data input and output ports
		.CARRYOUT(),			// 1-bit output: carry output                               
		.CARRYOUTF(),  			// 1-bit output: fabric carry output
		.M(), 			        // 36-bit output: fabric multiplier data output
		.P(sum_cos),      		// 48-bit output: data output
	//  Cascade Ports: 48-bit (each) input: No Cascade
		.PCIN(48'b0),           // 48-bit input: P cascade input
	// Control Input Ports: 1-bit (each) input: Clocking and operation mode
		.CLK(clk_i),           
		.OPMODE({4'b0000,sum_en_i,3'b001}),// 8-bit input: operation mode input
		 // .OPMODE({4'b0000,sum_en_i,sum_en_i,2'b01}),// 8-bit input: operation mode input
	// Data Ports: 18-bit (each) input: Data input and output ports
		.A(adc_wind[34:17]),    // 18-bit input: A data input
		.B(cos_i), 				// 18-bit input: B data input
		.C(sum_cos),			// 48-bit input: C data input
		.CARRYIN(1'b0),			// 1-bit input: carry input signal
		.D(18'b0),				// 18-bit input: B pre-adder data input
	//  Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports
		.CEA(1'b1),				// 1-bit input: clock enable input for A registers
		.CEB(1'b1),				// 1-bit input: clock enable input for B registers
		.CEC(1'b1),    			// 1-bit input: clock enable input for C registers
		.CECARRYIN(1'b1),   	// 1-bit input: clock enable input for CARRYIN registers
		.CED(1'b1),             // 1-bit input: clock enable input for D registers
		.CEM(1'b1),             // 1-bit input: clock enable input for multiplier registers
		.CEOPMODE(1'b1),		// 1-bit input: clock enable input for OPMODE registers
		.CEP(1'b1),    			// 1-bit input: clock enable input for P registers
		.RSTA(1'b0),            // 1-bit input: reset input for A pipeline registers
		.RSTB(1'b0),            // 1-bit input: reset input for B pipeline registers
		.RSTC(1'b0),            // 1-bit input: reset input for C pipeline registers
		.RSTCARRYIN(1'b0), 		// 1-bit input: reset input for CARRYIN pipeline registers
		.RSTD(1'b0),            // 1-bit input: reset input for D pipeline registers
		.RSTM(1'b0),            // 1-bit input: reset input for M pipeline registers
		.RSTOPMODE(1'b0),		// 1-bit input: reset input for OPMODE pipeline registers
		.RSTP(1'b0)   	        // 1-bit input: reset input for P pipeline registers
    );
	
endmodule