S5443/S5443_S/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:12:30 06/03/2020 
// Design Name: 
// Module Name:    WinParameters 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: kek
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
//////////////////////////////////////////////////////////////////////////////////
	
module FifoController	
#(
	parameter	TxInPack		=	200,		
	parameter	WorkTimeCycles	=	404000
	// parameter	WorkTimeCycles	=	20000
)
(
	input	Clk_i, 
	input	Rst_i,	
	input	PpiBusy_i,	
	input	DspReadyForRx_i,
	input	MeasDataVal_i,
	input	[32-1:0]	MeasNum_i,
	input	FullFlag_i,
	input	EmptyFlag_i,
	
	output	MeasDataVal_o,
	
	output	reg	WrEn_o,
	output	RdEn_o
);
//================================================================================
//  REG/WIRE
//================================================================================
	reg	rdEn;
	reg	[13:0]	wrCnt;
//================================================================================
//  ASSIGNMENTS
//================================================================================
	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
	
//================================================================================
//  CODING
//================================================================================		

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(WrEn_o)	begin
			wrCnt	<=	wrCnt+14'd1;
		end	
	end	else	begin
		wrCnt	<=	14'd0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(!FullFlag_i)	begin
			if	(MeasDataVal_i)	begin
				if	(wrCnt!=MeasNum_i)	begin
					WrEn_o	<=	1'b1;
				end	else	begin
					WrEn_o	<=	1'b0;
				end
			end	else	begin
				WrEn_o	<=	1'b0;
			end
		end	else	begin
			WrEn_o	<=	1'b0;
		end
	end	else	begin
		WrEn_o	<=	1'b0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(!DspReadyForRx_i)	begin
			if	(!PpiBusy_i)	begin
				if	(!EmptyFlag_i)	begin
					rdEn	<=	1'b1;
				end	else	begin
					rdEn	<=	1'b0;
				end
			end	else	begin
				rdEn	<=	1'b0;
			end
		end	else	begin
			rdEn	<=	1'b0;
		end
	end	else	begin
		rdEn	<=	1'b0;
	end
end

endmodule