S5443TopSpectrumTb.v 18 KB

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  1. `timescale 1ns / 1ps
  2. //=============================================================================================================
  3. // Тестовая конфигурация:
  4. //
  5. // Режим измерения "Точка в импульсе".
  6. // Количество измерений = 1.
  7. // Выбраный фильтр = 2МГц.
  8. //
  9. // PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
  10. // PG2 -> модулятор. | Шаблон 1 имп.
  11. // PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
  12. // PG4 -> Gating Generator. | Шаблон 1 имп.
  13. //
  14. // Настройки мультиплексоров генераторов:
  15. // PG1MUX_OUT -> INT_TRIG.
  16. // PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
  17. // PG3MUX_OUT -> PG1.
  18. // PG4MUX_OUT -> PG1.
  19. // PG5MUX_OUT -> PG1.
  20. // PG6MUX_OUT -> PG1.
  21. // PG7MUX_OUT -> PG1.
  22. //
  23. // Настройки остальных мультиплексоров:
  24. // MODMUX_OUT -> PG2.
  25. // GATINGMUX_OUT -> PG4.
  26. // SAMPLSTROBEMUX_OUT -> PG3.
  27. // EXTSTARTMUX -> DSPSTART.
  28. //=============================================================================================================
  29. module S5443TopSpectrumTb;
  30. localparam [4:0] EP1MUXCMD = 5'd14;
  31. localparam [4:0] EP2MUXCMD = 5'd1;
  32. localparam [4:0] EP3MUXCMD = 5'd1;
  33. localparam [4:0] EP4MUXCMD = 5'd1;
  34. localparam [4:0] EP5MUXCMD = 5'd1;
  35. localparam [4:0] EP6MUXCMD = 5'd1;
  36. localparam [4:0] PG1MUXCMD = 5'd13;
  37. localparam [4:0] PG2MUXCMD = 5'd0;
  38. localparam [4:0] PG3MUXCMD = 5'd18;
  39. localparam [4:0] PG4MUXCMD = 5'd18;
  40. localparam [4:0] PG5MUXCMD = 5'd0;
  41. localparam [4:0] PG6MUXCMD = 5'd0;
  42. localparam [4:0] PG7MUXCMD = 5'd0;
  43. localparam [2:0] PG1MODE = 3'd5;
  44. localparam [2:0] PG2MODE = 3'd1;
  45. localparam [2:0] PG3MODE = 3'd3;
  46. localparam [2:0] PG4MODE = 3'd4;
  47. localparam [2:0] PG5MODE = 3'd0;
  48. localparam [2:0] PG6MODE = 3'd0;
  49. localparam [2:0] PG7MODE = 3'd3;
  50. localparam PG1POL = 1'b0;
  51. localparam PG2POL = 1'b0;
  52. localparam PG3POL = 1'b0;
  53. localparam PG4POL = 1'b0;
  54. localparam PG5POL = 1'b0;
  55. localparam PG6POL = 1'b0;
  56. localparam PG7POL = 1'b0;
  57. localparam [4:0] EXTTRIGMUXCMD = 5'd15;
  58. localparam [4:0] DSPTRIGINCMD = 5'h8;
  59. localparam [4:0] MUXSLOWMODCMD = 5'd1;
  60. localparam [4:0] MUXFASTMODCMD = 5'd1;
  61. localparam [4:0] GATINGMUXCMD = 5'd2;
  62. localparam [4:0] SMPLSTRBMUXCMD = 5'd3;
  63. localparam [1:0] CURRADCCHANNEL = 2'b0;
  64. //COMMANDS FOR REG_MAP
  65. parameter [31:0] MeasCmdBypass = {8'h11,8'h0,8'h63,8'h1};
  66. parameter [31:0] MeasCmdFft = {8'h11,8'h0,8'h63,7'h2,1'b1};
  67. parameter [31:0] MeasCmd = {8'h11,8'h0,8'h53,8'h0};
  68. // parameter [31:0] MeasCmd = {8'h11,8'h3e,8'h63,8'h0};
  69. parameter [31:0] AdcCtrl = {8'h12,24'h2};
  70. parameter [31:0] SensCtrlCmd = {1'b0,21'h0,CURRADCCHANNEL,4'h0,4'b1};
  71. // parameter [31:0] DitherCmd = {8'h0E,24'h100192};
  72. parameter [31:0] DitherCmd = {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
  73. parameter [31:0] IfFtwH = {8'h15,16'h0,8'h40};
  74. parameter [31:0] IfFtwL = {8'h16,24'h000000};
  75. parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
  76. parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
  77. //PG7 Cmd
  78. parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
  79. parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd1};
  80. parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd5};
  81. parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd15};
  82. parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
  83. parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd3};
  84. parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd5};
  85. parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
  86. //PG1 Cmd
  87. parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
  88. parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd400};
  89. parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
  90. parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
  91. parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd1};
  92. parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
  93. parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
  94. parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
  95. //PG2 Cmd
  96. parameter [31:0] PG2P1DelayRegCmd = {8'h20,24'd0};
  97. parameter [31:0] PG2P2DelayRegCmd = {8'h21,24'd1};
  98. parameter [31:0] PG2P3DelayRegCmd = {8'h22,24'd5};
  99. parameter [31:0] PG2P123DelayRegCmd = {8'h23,24'd15};
  100. parameter [31:0] PG2P1WidthRegCmd = {8'h24,24'd1};
  101. parameter [31:0] PG2P2WidthRegCmd = {8'h25,24'd3};
  102. parameter [31:0] PG2P3WidthRegCmd = {8'h26,24'd5};
  103. parameter [31:0] PG2P123WidthRegCmd = {8'h27,24'd0};
  104. //PG3 Cmd
  105. parameter [31:0] PG3P1DelayRegCmd = {8'h20,24'd0};
  106. parameter [31:0] PG3P2DelayRegCmd = {8'h21,24'd1};
  107. parameter [31:0] PG3P3DelayRegCmd = {8'h22,24'd5};
  108. parameter [31:0] PG3P123DelayRegCmd = {8'h23,24'd15};
  109. parameter [31:0] PG3P1WidthRegCmd = {8'h24,24'd1};
  110. parameter [31:0] PG3P2WidthRegCmd = {8'h25,24'd3};
  111. parameter [31:0] PG3P3WidthRegCmd = {8'h26,24'd5};
  112. parameter [31:0] PG3P123WidthRegCmd = {8'h27,24'd0};
  113. //PG4 Cmd
  114. parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
  115. parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd18};
  116. parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
  117. parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
  118. parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd1};
  119. parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd10};
  120. parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd7};
  121. parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
  122. //PG5 Cmd
  123. parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
  124. parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
  125. parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
  126. parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
  127. parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd0};
  128. parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
  129. parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
  130. parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
  131. //PG6 Cmd
  132. parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd0};
  133. parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd5};
  134. parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd15};
  135. parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
  136. parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd1};
  137. parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd3};
  138. parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd5};
  139. parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
  140. parameter [31:0] MeasNum0RegCmd = {8'h58,24'd10};
  141. parameter [31:0] MeasNum1RegCmd = {8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
  142. parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
  143. parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
  144. parameter [31:0] MuxCtrl1RegCmd = {8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
  145. parameter [31:0] MuxCtrl2RegCmd = {8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
  146. parameter [31:0] MuxCtrl3RegCmd = {8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
  147. parameter [31:0] MuxCtrl4RegCmd = {8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
  148. //=================================================================================================================================================================================================================
  149. reg Clk41;
  150. reg Clk50;
  151. reg Clk70;
  152. reg [31:0] tb_cnt=4'd0;
  153. reg rst;
  154. reg mosi_i = 1'b0;
  155. reg Miso_i = 1'b0;
  156. reg ss_i;
  157. reg clk_i = 1'b0;
  158. reg [31:0] DspSpiData;
  159. reg startCalcCmdReg;
  160. wire [17:0] cos_value;
  161. wire [17:0] sin_value;
  162. wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
  163. wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
  164. wire ExtTrigger0 = ExtDspTrigNeg0;
  165. wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
  166. wire endMeas;
  167. reg [31:0] cmdCnt;
  168. reg trig0;
  169. reg trig1;
  170. wire trig0R;
  171. wire trig1R;
  172. assign trig0R = trig0;
  173. assign trig1R = trig1;
  174. //==========================================================================================
  175. //clocks gen
  176. always #10 Clk50 = ~Clk50;
  177. always #(14.285714285714/2) Clk70 = ~Clk70;
  178. always #10 clk_i = ~clk_i;
  179. always #(24.390243902439/2) Clk41 = ~Clk41;
  180. wire sck_i;
  181. //==========================================================================================
  182. initial begin
  183. Clk50 = 1'b1;
  184. Clk70 = 1'b1;
  185. rst = 1'b1;
  186. Clk41 = 1'b0;
  187. trig0 = 1'b0;
  188. trig1 = 1'b0;
  189. #100;
  190. rst = 1'b0;
  191. #400;
  192. Clk41 = 1'b0;
  193. end
  194. reg endMeasReg;
  195. always @(posedge Clk41) begin
  196. endMeasReg <= endMeas;
  197. end
  198. wire endMeasNeg = !endMeas&endMeasReg;
  199. always @(posedge Clk70) begin
  200. if (!rst) begin
  201. if (!endMeas) begin
  202. if (tb_cnt == 4505) begin
  203. startCalcCmdReg <= 1'b1;
  204. end
  205. end else begin
  206. startCalcCmdReg <= 1'b0;
  207. end
  208. end else begin
  209. startCalcCmdReg <= 1'b0;
  210. end
  211. end
  212. always @(negedge Clk41) begin
  213. if (!rst) begin
  214. tb_cnt <= tb_cnt+1;
  215. end else begin
  216. tb_cnt <= 0;
  217. end
  218. end
  219. wire Adc1DataDa0P;
  220. wire Adc1DataDa1P;
  221. wire [31:0] test = 32'h2351eb85;
  222. // wire [31:0] test = 32'h40000000;
  223. CordicNco
  224. #( .ODatWidth (18),
  225. .PhIncWidth (32),
  226. .IterNum (10),
  227. .EnSinN (0))
  228. ncoInst
  229. (
  230. .Clk_i (Clk50),
  231. .Rst_i (rst),
  232. .Val_i (1'b1),
  233. .PhaseInc_i (test),
  234. .WindVal_i (1'b1),
  235. .WinType_i (),
  236. .Wind_o (),
  237. .Sin_o (sin_value),
  238. .Cos_o (cos_value),
  239. .Val_o ()
  240. );
  241. S5443Top MasterFpga
  242. (
  243. .Clk_i (Clk50),
  244. .Led_o (),
  245. //------------------------------------------
  246. .Adc1FclkP_i (),
  247. .Adc1FclkN_i (),
  248. .Adc1DataDa0P_i (Adc1DataDa0P),
  249. .Adc1DataDa0N_i (~Adc1DataDa0P),
  250. .Adc1DataDa1P_i (Adc1DataDa1P),
  251. .Adc1DataDa1N_i (~Adc1DataDa1P),
  252. .Adc1DataDb0P_i (Adc1DataDa0P),
  253. .Adc1DataDb0N_i (~Adc1DataDa0P),
  254. .Adc1DataDb1P_i (Adc1DataDa1P),
  255. .Adc1DataDb1N_i (~Adc1DataDa1P),
  256. //------------------------------------------
  257. .Adc2FclkP_i (),
  258. .Adc2FclkN_i (),
  259. .Adc2DataDa0P_i (1'b1),
  260. .Adc2DataDa0N_i (1'b0),
  261. .Adc2DataDa1P_i (1'b1),
  262. .Adc2DataDa1N_i (1'b0),
  263. .Adc2DataDb0P_i (1'b1),
  264. .Adc2DataDb0N_i (1'b0),
  265. .Adc2DataDb1P_i (1'b1),
  266. .Adc2DataDb1N_i (1'b0),
  267. //------------------------------------------
  268. .AdcInitMosi_o (),
  269. .AdcInitClk_o (),
  270. .Adc1InitCs_o (),
  271. .Adc2InitCs_o (),
  272. .AdcInitRst_o (),
  273. //------------------------------------------
  274. .Mosi_i (mosi_i),
  275. .Sck_i (~sck_i),
  276. .Ss_i (ss_i),
  277. .LpOutClk_o (),
  278. .LpOutFs_o (),
  279. .LpOutData_o (),
  280. //fpga-dsp signals
  281. .StartMeas_i (startCalcCmdReg),
  282. .StartMeasEvent_o (startMeasS),
  283. .EndMeas_o (endMeas),
  284. .TimersClk_o (),
  285. .Trig6to1_io (),
  286. .Trig6to1Dir_o (),
  287. .DspTrigOut_i (Clk41), //Trig from DSP
  288. .DspTrigIn_o (), //Trig To DSP
  289. .OverloadS_i (1'b0),
  290. .Overload_o (),
  291. .PortSel_o (),
  292. .PortSelDir_o (),
  293. //mod out line
  294. .Mod_o (),
  295. //gain lines
  296. .DspReadyForRx_i (1'b0),
  297. .DspReadyForRxToFpgaS_o (),
  298. .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  299. .AdcData_i (sin_value[17-:14])
  300. // .AdcData_i (Data_i)
  301. );
  302. parameter IDLE = 2'h0;
  303. parameter CMD = 2'h1;
  304. parameter TX = 2'h2;
  305. parameter PAUSE = 2'h3;
  306. reg [1:0] txCurrState;
  307. reg [1:0] txNextState;
  308. wire txWork = tb_cnt >= 23;
  309. // wire txStop = (cmdCnt >= 90) & (cmdCnt >= 70) & (cmdCnt >= 71);
  310. wire txStop = (cmdCnt >= 251);
  311. reg [6:0] txCnt;
  312. reg [3:0] pauseCnt;
  313. always @(posedge Clk41) begin
  314. if (!rst) begin
  315. if (txCurrState == CMD) begin
  316. if (!txStop) begin
  317. cmdCnt <= cmdCnt+1;
  318. end
  319. end
  320. end else begin
  321. cmdCnt <= 0;
  322. end
  323. end
  324. always @(posedge Clk41) begin
  325. if (!rst) begin
  326. if (txCurrState == TX) begin
  327. txCnt <= txCnt+1;
  328. end else begin
  329. txCnt <= 0;
  330. end
  331. end else begin
  332. txCnt <= 0;
  333. end
  334. end
  335. always @(posedge Clk41) begin
  336. if (!rst) begin
  337. if (txCurrState == PAUSE) begin
  338. pauseCnt <= pauseCnt+1;
  339. end else begin
  340. pauseCnt <= 0;
  341. end
  342. end else begin
  343. pauseCnt <= 0;
  344. end
  345. end
  346. always @(posedge Clk41) begin
  347. if (txCurrState == CMD) begin
  348. if (cmdCnt == 0) begin
  349. // DspSpiData <= MeasCmd;
  350. DspSpiData <= SensCtrlCmd;
  351. end else if (cmdCnt == 1) begin
  352. DspSpiData <= IfFtwH;
  353. end else if (cmdCnt == 2) begin
  354. DspSpiData <= IfFtwL;
  355. end else if (cmdCnt == 3) begin
  356. DspSpiData <= FilterCorrCmdH;
  357. end else if (cmdCnt == 4) begin
  358. DspSpiData <= FilterCorrCmdL;
  359. end else if (cmdCnt == 5) begin
  360. DspSpiData <= PG1P1DelayRegCmd;
  361. end else if (cmdCnt == 6) begin
  362. DspSpiData <= PG1P2DelayRegCmd;
  363. end else if (cmdCnt == 7) begin
  364. DspSpiData <= PG1P3DelayRegCmd;
  365. end else if (cmdCnt == 8) begin
  366. DspSpiData <= PG1P123DelayRegCmd;
  367. end else if (cmdCnt == 9) begin
  368. DspSpiData <= PG1P1WidthRegCmd;
  369. end else if (cmdCnt == 10) begin
  370. DspSpiData <= PG1P2WidthRegCmd;
  371. end else if (cmdCnt == 11) begin
  372. DspSpiData <= PG1P3WidthRegCmd;
  373. end else if (cmdCnt == 12) begin
  374. DspSpiData <= PG1P123WidthRegCmd;
  375. end else if (cmdCnt == 13) begin
  376. DspSpiData <= PG2P1DelayRegCmd;
  377. end else if (cmdCnt == 14) begin
  378. DspSpiData <= PG2P2DelayRegCmd;
  379. end else if (cmdCnt == 15) begin
  380. DspSpiData <= PG2P3DelayRegCmd;
  381. end else if (cmdCnt == 16) begin
  382. DspSpiData <= PG2P123DelayRegCmd;
  383. end else if (cmdCnt == 17) begin
  384. DspSpiData <= PG2P1WidthRegCmd;
  385. end else if (cmdCnt == 18) begin
  386. DspSpiData <= PG2P2WidthRegCmd;
  387. end else if (cmdCnt == 19) begin
  388. DspSpiData <= PG2P3WidthRegCmd;
  389. end else if (cmdCnt == 20) begin
  390. DspSpiData <= PG2P123WidthRegCmd;
  391. end else if (cmdCnt == 21) begin
  392. DspSpiData <= PG3P1DelayRegCmd;
  393. end else if (cmdCnt == 22) begin
  394. DspSpiData <= PG3P2DelayRegCmd;
  395. end else if (cmdCnt == 23) begin
  396. DspSpiData <= PG3P3DelayRegCmd;
  397. end else if (cmdCnt == 24) begin
  398. DspSpiData <= PG3P123DelayRegCmd;
  399. end else if (cmdCnt == 25) begin
  400. DspSpiData <= PG3P1WidthRegCmd;
  401. end else if (cmdCnt == 26) begin
  402. DspSpiData <= PG3P2WidthRegCmd;
  403. end else if (cmdCnt == 27) begin
  404. DspSpiData <= PG3P3WidthRegCmd;
  405. end else if (cmdCnt == 28) begin
  406. DspSpiData <= PG3P123WidthRegCmd;
  407. end else if (cmdCnt == 29) begin
  408. DspSpiData <= PG4P1DelayRegCmd;
  409. end else if (cmdCnt == 30) begin
  410. DspSpiData <= PG4P2DelayRegCmd;
  411. end else if (cmdCnt == 31) begin
  412. DspSpiData <= PG4P3DelayRegCmd;
  413. end else if (cmdCnt == 32) begin
  414. DspSpiData <= PG4P123DelayRegCmd;
  415. end else if (cmdCnt == 33) begin
  416. DspSpiData <= PG4P1WidthRegCmd;
  417. end else if (cmdCnt == 34) begin
  418. DspSpiData <= PG4P2WidthRegCmd;
  419. end else if (cmdCnt == 35) begin
  420. DspSpiData <= PG4P3WidthRegCmd;
  421. end else if (cmdCnt == 36) begin
  422. DspSpiData <= PG4P123WidthRegCmd;
  423. end else if (cmdCnt == 37) begin
  424. DspSpiData <= PG5P1DelayRegCmd;
  425. end else if (cmdCnt == 38) begin
  426. DspSpiData <= PG5P2DelayRegCmd;
  427. end else if (cmdCnt == 39) begin
  428. DspSpiData <= PG5P3DelayRegCmd;
  429. end else if (cmdCnt == 40) begin
  430. DspSpiData <= PG5P123DelayRegCmd;
  431. end else if (cmdCnt == 41) begin
  432. DspSpiData <= PG5P1WidthRegCmd;
  433. end else if (cmdCnt == 42) begin
  434. DspSpiData <= PG5P2WidthRegCmd;
  435. end else if (cmdCnt == 43) begin
  436. DspSpiData <= PG5P3WidthRegCmd;
  437. end else if (cmdCnt == 44) begin
  438. DspSpiData <= PG5P123WidthRegCmd;
  439. end else if (cmdCnt == 45) begin
  440. DspSpiData <= PG6P1DelayRegCmd;
  441. end else if (cmdCnt == 46) begin
  442. DspSpiData <= PG6P2DelayRegCmd;
  443. end else if (cmdCnt == 47) begin
  444. DspSpiData <= PG6P3DelayRegCmd;
  445. end else if (cmdCnt == 48) begin
  446. DspSpiData <= PG6P123DelayRegCmd;
  447. end else if (cmdCnt == 49) begin
  448. DspSpiData <= PG6P1WidthRegCmd;
  449. end else if (cmdCnt == 50) begin
  450. DspSpiData <= PG6P2WidthRegCmd;
  451. end else if (cmdCnt == 51) begin
  452. DspSpiData <= PG6P3WidthRegCmd;
  453. end else if (cmdCnt == 52) begin
  454. DspSpiData <= PG6P123WidthRegCmd;
  455. end else if (cmdCnt == 53) begin
  456. DspSpiData <= PG7P1DelayRegCmd;
  457. end else if (cmdCnt == 54) begin
  458. DspSpiData <= PG7P2DelayRegCmd;
  459. end else if (cmdCnt == 55) begin
  460. DspSpiData <= PG7P3DelayRegCmd;
  461. end else if (cmdCnt == 56) begin
  462. DspSpiData <= PG7P123DelayRegCmd;
  463. end else if (cmdCnt == 57) begin
  464. DspSpiData <= PG7P1WidthRegCmd;
  465. end else if (cmdCnt == 58) begin
  466. DspSpiData <= PG7P2WidthRegCmd;
  467. end else if (cmdCnt == 59) begin
  468. DspSpiData <= PG7P3WidthRegCmd;
  469. end else if (cmdCnt == 60) begin
  470. DspSpiData <= DitherCmd;
  471. end else if (cmdCnt == 61) begin
  472. DspSpiData <= MeasNum0RegCmd;
  473. end else if (cmdCnt == 62) begin
  474. DspSpiData <= MeasNum1RegCmd;
  475. end else if (cmdCnt == 63) begin
  476. DspSpiData <= PGMode0RegCmd;
  477. end else if (cmdCnt == 64) begin
  478. DspSpiData <= PGMode1RegCmd;
  479. end else if (cmdCnt == 65) begin
  480. DspSpiData <= MuxCtrl1RegCmd;
  481. end else if (cmdCnt == 66) begin
  482. DspSpiData <= MuxCtrl2RegCmd;
  483. end else if (cmdCnt == 67) begin
  484. DspSpiData <= MuxCtrl3RegCmd;
  485. end else if (cmdCnt == 68) begin
  486. DspSpiData <= AdcCtrl;
  487. end else if (cmdCnt == 99) begin
  488. DspSpiData <= {8'h58,24'd100};
  489. end else if (cmdCnt == 100) begin
  490. DspSpiData <= MeasCmdFft;
  491. end else begin
  492. DspSpiData <= 32'hfffffff;
  493. end
  494. end else if (txCurrState == TX) begin
  495. DspSpiData <= DspSpiData<<1;
  496. end
  497. end
  498. always @(posedge Clk41) begin
  499. if (txCurrState == TX) begin
  500. if (txCnt >= 7'd0) begin
  501. mosi_i <= DspSpiData[31];
  502. end else begin
  503. mosi_i <= 1'b1;
  504. end
  505. end else begin
  506. mosi_i <= 1'b1;
  507. end
  508. end
  509. always @(posedge Clk41) begin
  510. if (txCurrState == TX) begin
  511. ss_i <= 1'b0;
  512. end else begin
  513. ss_i <= 1'b1;
  514. end
  515. end
  516. assign sck_i = Clk41;
  517. always @(posedge Clk41) begin
  518. if (rst) begin
  519. txCurrState <= IDLE;
  520. end else begin
  521. txCurrState <= txNextState;
  522. end
  523. end
  524. always @(*) begin
  525. txNextState = IDLE;
  526. case(txCurrState)
  527. IDLE : begin
  528. if (txWork) begin
  529. txNextState = CMD;
  530. end else begin
  531. txNextState = IDLE;
  532. end
  533. end
  534. CMD : begin
  535. if (!txStop) begin
  536. txNextState = TX;
  537. end else begin
  538. txNextState = IDLE;
  539. end
  540. end
  541. TX : begin
  542. if (txCnt==6'd31) begin
  543. txNextState = PAUSE;
  544. end else begin
  545. txNextState = TX;
  546. end
  547. end
  548. PAUSE : begin
  549. if (pauseCnt==4'd10) begin
  550. txNextState = CMD;
  551. end else begin
  552. txNextState = PAUSE;
  553. end
  554. end
  555. endcase
  556. end
  557. reg [13:0] Data_i;
  558. real pi = 3.14159265358;
  559. real phase = 0;
  560. real phaseInc = 0.001;
  561. real signal;
  562. always @ (posedge Clk50)
  563. begin
  564. if (tb_cnt >= 4505)
  565. begin
  566. phase = phase + phaseInc;
  567. phaseInc <= phaseInc + 0.0005;
  568. signal = $sin(2*pi*phase);
  569. Data_i = 2**12 * signal;
  570. end
  571. else
  572. Data_i = 0;
  573. end
  574. endmodule