S5443TopPulseProfileTb.v 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710
  1. `timescale 1ns / 1ps
  2. //=============================================================================================================
  3. // Тестовая конфигурация:
  4. //
  5. // Режим измерения "Точка в импульсе".
  6. // Количество измерений = 1.
  7. // Выбраный фильтр = 2МГц.
  8. //
  9. // PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
  10. // PG2 -> модулятор. | Шаблон 1 имп.
  11. // PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
  12. // PG4 -> Gating Generator. | Шаблон 1 имп.
  13. //
  14. // Настройки мультиплексоров генераторов:
  15. // PG1MUX_OUT -> INT_TRIG.
  16. // PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
  17. // PG3MUX_OUT -> PG1.
  18. // PG4MUX_OUT -> PG1.
  19. // PG5MUX_OUT -> PG1.
  20. // PG6MUX_OUT -> PG1.
  21. // PG7MUX_OUT -> PG1.
  22. //
  23. // Настройки остальных мультиплексоров:
  24. // MODMUX_OUT -> PG2.
  25. // GATINGMUX_OUT -> PG4.
  26. // SAMPLSTROBEMUX_OUT -> PG3.
  27. // EXTSTARTMUX -> DSPSTART.
  28. //=============================================================================================================
  29. module S5443TopPulseProfileTb;
  30. localparam [4:0] EP1MUXCMD = 5'd14;
  31. localparam [4:0] EP2MUXCMD = 5'd1;
  32. localparam [4:0] EP3MUXCMD = 5'd1;
  33. localparam [4:0] EP4MUXCMD = 5'd1;
  34. localparam [4:0] EP5MUXCMD = 5'd1;
  35. localparam [4:0] EP6MUXCMD = 5'd1;
  36. localparam [4:0] PG1MUXCMD = 5'd13;
  37. localparam [4:0] PG2MUXCMD = 5'd0;
  38. localparam [4:0] PG3MUXCMD = 5'd18;
  39. localparam [4:0] PG4MUXCMD = 5'd18;
  40. localparam [4:0] PG5MUXCMD = 5'd0;
  41. localparam [4:0] PG6MUXCMD = 5'd0;
  42. localparam [4:0] PG7MUXCMD = 5'd0;
  43. localparam [2:0] PG1MODE = 3'd5;
  44. localparam [2:0] PG2MODE = 3'd1;
  45. localparam [2:0] PG3MODE = 3'd3;
  46. localparam [2:0] PG4MODE = 3'd4;
  47. localparam [2:0] PG5MODE = 3'd0;
  48. localparam [2:0] PG6MODE = 3'd0;
  49. localparam [2:0] PG7MODE = 3'd3;
  50. localparam PG1POL = 1'b0;
  51. localparam PG2POL = 1'b0;
  52. localparam PG3POL = 1'b0;
  53. localparam PG4POL = 1'b0;
  54. localparam PG5POL = 1'b0;
  55. localparam PG6POL = 1'b0;
  56. localparam PG7POL = 1'b0;
  57. localparam [4:0] EXTTRIGMUXCMD = 5'd7;
  58. localparam [4:0] DSPTRIGINCMD = 5'h8;
  59. localparam [4:0] MUXSLOWMODCMD = 5'd1;
  60. localparam [4:0] MUXFASTMODCMD = 5'd1;
  61. localparam [4:0] GATINGMUXCMD = 5'd2;
  62. localparam [4:0] SMPLSTRBMUXCMD = 5'd8;
  63. //COMMANDS FOR REG_MAP
  64. parameter [31:0] MeasCmdBypass = {8'h11,8'h0,8'h63,8'h1};
  65. parameter [31:0] MeasCmdFft = {8'h11,8'h0,8'h63,7'h5,1'b1};
  66. parameter [31:0] MeasCmd = {8'h11,8'hff,8'h53,8'h0};
  67. // parameter [31:0] MeasCmd = {8'h11,8'h3e,8'h63,8'h0};
  68. parameter [31:0] AdcCtrl = {8'h12,24'h2};
  69. parameter [31:0] SensCtrlCmd = {1'b0,27'h0,4'b1};
  70. // parameter [31:0] DitherCmd = {8'h0E,24'h100192};
  71. parameter [31:0] DitherCmd = {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
  72. parameter [31:0] IfFtwH = {8'h15,16'h0,8'h40};
  73. parameter [31:0] IfFtwL = {8'h16,24'h000000};
  74. parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
  75. parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
  76. //PG7 Cmd
  77. parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
  78. parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd1};
  79. parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd5};
  80. parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd15};
  81. parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
  82. parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd3};
  83. parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd5};
  84. parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
  85. //PG1 Cmd
  86. parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
  87. parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd400};
  88. parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
  89. parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
  90. parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd1};
  91. parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
  92. parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
  93. parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
  94. //PG2 Cmd
  95. parameter [31:0] PG2P1DelayRegCmd = {8'h20,24'd0};
  96. parameter [31:0] PG2P2DelayRegCmd = {8'h21,24'd1};
  97. parameter [31:0] PG2P3DelayRegCmd = {8'h22,24'd5};
  98. parameter [31:0] PG2P123DelayRegCmd = {8'h23,24'd15};
  99. parameter [31:0] PG2P1WidthRegCmd = {8'h24,24'd1};
  100. parameter [31:0] PG2P2WidthRegCmd = {8'h25,24'd3};
  101. parameter [31:0] PG2P3WidthRegCmd = {8'h26,24'd5};
  102. parameter [31:0] PG2P123WidthRegCmd = {8'h27,24'd0};
  103. //PG3 Cmd
  104. parameter [31:0] PG3P1DelayRegCmd = {8'h20,24'd0};
  105. parameter [31:0] PG3P2DelayRegCmd = {8'h21,24'd1};
  106. parameter [31:0] PG3P3DelayRegCmd = {8'h22,24'd5};
  107. parameter [31:0] PG3P123DelayRegCmd = {8'h23,24'd15};
  108. parameter [31:0] PG3P1WidthRegCmd = {8'h24,24'd1};
  109. parameter [31:0] PG3P2WidthRegCmd = {8'h25,24'd3};
  110. parameter [31:0] PG3P3WidthRegCmd = {8'h26,24'd5};
  111. parameter [31:0] PG3P123WidthRegCmd = {8'h27,24'd0};
  112. //PG4 Cmd
  113. parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
  114. parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd18};
  115. parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
  116. parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
  117. parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd1};
  118. parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd10};
  119. parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd7};
  120. parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
  121. //PG5 Cmd
  122. parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
  123. parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
  124. parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
  125. parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
  126. parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd0};
  127. parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
  128. parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
  129. parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
  130. //PG6 Cmd
  131. parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd0};
  132. parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd5};
  133. parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd15};
  134. parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
  135. parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd1};
  136. parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd3};
  137. parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd5};
  138. parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
  139. parameter [31:0] MeasNum0RegCmd = {8'h58,24'd10};
  140. parameter [31:0] MeasNum1RegCmd = {8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
  141. parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
  142. parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
  143. parameter [31:0] MuxCtrl1RegCmd = {8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
  144. parameter [31:0] MuxCtrl2RegCmd = {8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
  145. parameter [31:0] MuxCtrl3RegCmd = {8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
  146. parameter [31:0] MuxCtrl4RegCmd = {8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
  147. //=================================================================================================================================================================================================================
  148. reg Clk41;
  149. reg Clk50;
  150. reg Clk70;
  151. reg [31:0] tb_cnt=4'd0;
  152. reg rst;
  153. reg mosi_i = 1'b0;
  154. reg Miso_i = 1'b0;
  155. reg ss_i;
  156. reg clk_i = 1'b0;
  157. reg [31:0] DspSpiData;
  158. reg startCalcCmdReg;
  159. wire [17:0] cos_value;
  160. wire [17:0] sin_value;
  161. wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
  162. wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
  163. wire ExtTrigger0 = ExtDspTrigNeg0;
  164. wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
  165. wire endMeas;
  166. reg [31:0] cmdCnt;
  167. reg trig0;
  168. reg trig1;
  169. wire trig0R;
  170. wire trig1R;
  171. assign trig0R = trig0;
  172. assign trig1R = trig1;
  173. reg [32:0] extPulseTrigCnt;
  174. wire extPulseTrig = extPulseTrigCnt==32'd500;
  175. wire [5:0] extTrigBus;
  176. wire [5:0] extTrigDir;
  177. //==========================================================================================
  178. //clocks gen
  179. always #10 Clk50 = ~Clk50;
  180. always #(14.285714285714/2) Clk70 = ~Clk70;
  181. always #10 clk_i = ~clk_i;
  182. always #(24.390243902439/2) Clk41 = ~Clk41;
  183. wire sck_i;
  184. assign extTrigDir [0] = !MeasCmd[16];
  185. assign extTrigDir [1] = !MeasCmd[17];
  186. assign extTrigDir [2] = !MeasCmd[18];
  187. assign extTrigDir [3] = !MeasCmd[19];
  188. assign extTrigDir [4] = !MeasCmd[20];
  189. assign extTrigDir [5] = !MeasCmd[21];
  190. assign extTrigBus [0] = (MeasCmd[16]) ? extPulseTrig:1'bz; //1 - in, 0 - out
  191. assign extTrigBus [1] = (MeasCmd[17]) ? 0:1'bz; //1 - in, 0 - out
  192. assign extTrigBus [2] = (MeasCmd[18]) ? extPulseTrig:1'bz; //1 - in, 0 - out
  193. assign extTrigBus [3] = (MeasCmd[19]) ? 0:1'bz; //1 - in, 0 - out
  194. assign extTrigBus [4] = (MeasCmd[20]) ? 0:1'bz; //1 - in, 0 - out
  195. assign extTrigBus [5] = (MeasCmd[21]) ? 0:1'bz; //1 - in, 0 - out
  196. //==========================================================================================
  197. initial begin
  198. Clk50 = 1'b1;
  199. Clk70 = 1'b1;
  200. rst = 1'b1;
  201. Clk41 = 1'b0;
  202. trig0 = 1'b0;
  203. trig1 = 1'b0;
  204. #100;
  205. rst = 1'b0;
  206. #400;
  207. Clk41 = 1'b0;
  208. end
  209. always @(posedge Clk50) begin
  210. if (!rst) begin
  211. if (extPulseTrigCnt!=32'd500) begin
  212. extPulseTrigCnt <= extPulseTrigCnt+32'd1;
  213. end else begin
  214. extPulseTrigCnt <= 32'd0;
  215. end
  216. end else begin
  217. extPulseTrigCnt <= 32'd0;
  218. end
  219. end
  220. reg endMeasReg;
  221. always @(posedge Clk41) begin
  222. endMeasReg <= endMeas;
  223. end
  224. wire endMeasNeg = !endMeas&endMeasReg;
  225. always @(posedge Clk70) begin
  226. if (!rst) begin
  227. if (!endMeas) begin
  228. if (tb_cnt == 3550 | tb_cnt == 3950 |tb_cnt == 4505) begin
  229. startCalcCmdReg <= 1'b1;
  230. end
  231. end else begin
  232. startCalcCmdReg <= 1'b0;
  233. end
  234. end else begin
  235. startCalcCmdReg <= 1'b0;
  236. end
  237. end
  238. always @(negedge Clk41) begin
  239. if (!rst) begin
  240. tb_cnt <= tb_cnt+1;
  241. end else begin
  242. tb_cnt <= 0;
  243. end
  244. end
  245. wire Adc1DataDa0P;
  246. wire Adc1DataDa1P;
  247. // wire [31:0] test = 32'h2351eb85;
  248. wire [31:0] test = 32'h40000000;
  249. CordicNco
  250. #( .ODatWidth (18),
  251. .PhIncWidth (32),
  252. .IterNum (10),
  253. .EnSinN (0))
  254. ncoInst
  255. (
  256. .Clk_i (Clk50),
  257. .Rst_i (rst),
  258. .Val_i (1'b1),
  259. .PhaseInc_i (test),
  260. .WindVal_i (1'b1),
  261. .WinType_i (),
  262. .Wind_o (),
  263. .Sin_o (sin_value),
  264. .Cos_o (cos_value),
  265. .Val_o ()
  266. );
  267. S5243Top MasterFpga
  268. (
  269. .ClkP_i (Clk50),
  270. .ClkN_i (~Clk50),
  271. .Led_o (),
  272. //------------------------------------------
  273. .Adc1FclkP_i (),
  274. .Adc1FclkN_i (),
  275. .Adc1DataDa0P_i (Adc1DataDa0P),
  276. .Adc1DataDa0N_i (~Adc1DataDa0P),
  277. .Adc1DataDa1P_i (Adc1DataDa1P),
  278. .Adc1DataDa1N_i (~Adc1DataDa1P),
  279. .Adc1DataDb0P_i (Adc1DataDa0P),
  280. .Adc1DataDb0N_i (~Adc1DataDa0P),
  281. .Adc1DataDb1P_i (Adc1DataDa1P),
  282. .Adc1DataDb1N_i (~Adc1DataDa1P),
  283. //------------------------------------------
  284. .Adc2FclkP_i (),
  285. .Adc2FclkN_i (),
  286. .Adc2DataDa0P_i (1'b1),
  287. .Adc2DataDa0N_i (1'b0),
  288. .Adc2DataDa1P_i (1'b1),
  289. .Adc2DataDa1N_i (1'b0),
  290. .Adc2DataDb0P_i (1'b1),
  291. .Adc2DataDb0N_i (1'b0),
  292. .Adc2DataDb1P_i (1'b1),
  293. .Adc2DataDb1N_i (1'b0),
  294. //------------------------------------------
  295. // .AdcInitMosi_o (),
  296. // .AdcInitClk_o (),
  297. .Adc1InitCs_o (),
  298. .Adc2InitCs_o (),
  299. // .AdcInitRst_o (),
  300. //------------------------------------------
  301. .Mosi_i (mosi_i),
  302. .Sck_i (~sck_i),
  303. .Ss_i (ss_i),
  304. .LpOutClk_o (),
  305. .LpOutFs_o (),
  306. .LpOutData_o (),
  307. //fpga-dsp signals
  308. .StartMeas_i (startCalcCmdReg),
  309. // .StartMeasEvent_o (startMeasS),
  310. .EndMeas_o (endMeas),
  311. .TimersClk_o (),
  312. .Trig6to1_io (extTrigBus),
  313. .Trig6to1Dir_o (extTrigDir),
  314. .DspTrigOut_i (Clk41), //Trig from DSP
  315. .DspTrigIn_o (), //Trig To DSP
  316. // .OverloadS_i (1'b0),
  317. .Overload_o (),
  318. .PortSel_o (),
  319. // .PortSelDir_o (),
  320. //mod out line
  321. .Mod_o (),
  322. //gain lines
  323. .DspReadyForRx_i (1'b0),
  324. // .DspReadyForRxToFpgaS_o (),
  325. .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  326. .AdcData_i (sin_value[17-:14])
  327. // .AdcData_i (Data_i)
  328. );
  329. parameter IDLE = 2'h0;
  330. parameter CMD = 2'h1;
  331. parameter TX = 2'h2;
  332. parameter PAUSE = 2'h3;
  333. reg [1:0] txCurrState;
  334. reg [1:0] txNextState;
  335. wire txWork = tb_cnt >= 23;
  336. // wire txStop = (cmdCnt >= 90) & (cmdCnt >= 70) & (cmdCnt >= 71);
  337. wire txStop = (cmdCnt >= 251);
  338. reg [6:0] txCnt;
  339. reg [3:0] pauseCnt;
  340. always @(posedge Clk41) begin
  341. if (!rst) begin
  342. if (txCurrState == CMD) begin
  343. if (!txStop) begin
  344. cmdCnt <= cmdCnt+1;
  345. end
  346. end
  347. end else begin
  348. cmdCnt <= 0;
  349. end
  350. end
  351. always @(posedge Clk41) begin
  352. if (!rst) begin
  353. if (txCurrState == TX) begin
  354. txCnt <= txCnt+1;
  355. end else begin
  356. txCnt <= 0;
  357. end
  358. end else begin
  359. txCnt <= 0;
  360. end
  361. end
  362. always @(posedge Clk41) begin
  363. if (!rst) begin
  364. if (txCurrState == PAUSE) begin
  365. pauseCnt <= pauseCnt+1;
  366. end else begin
  367. pauseCnt <= 0;
  368. end
  369. end else begin
  370. pauseCnt <= 0;
  371. end
  372. end
  373. always @(posedge Clk41) begin
  374. if (txCurrState == CMD) begin
  375. if (cmdCnt == 0) begin
  376. DspSpiData <= MeasCmd;
  377. end else if (cmdCnt == 1) begin
  378. DspSpiData <= IfFtwH;
  379. end else if (cmdCnt == 2) begin
  380. DspSpiData <= IfFtwL;
  381. end else if (cmdCnt == 3) begin
  382. DspSpiData <= FilterCorrCmdH;
  383. end else if (cmdCnt == 4) begin
  384. DspSpiData <= FilterCorrCmdL;
  385. end else if (cmdCnt == 5) begin
  386. DspSpiData <= PG1P1DelayRegCmd;
  387. end else if (cmdCnt == 6) begin
  388. DspSpiData <= PG1P2DelayRegCmd;
  389. end else if (cmdCnt == 7) begin
  390. DspSpiData <= PG1P3DelayRegCmd;
  391. end else if (cmdCnt == 8) begin
  392. DspSpiData <= PG1P123DelayRegCmd;
  393. end else if (cmdCnt == 9) begin
  394. DspSpiData <= PG1P1WidthRegCmd;
  395. end else if (cmdCnt == 10) begin
  396. DspSpiData <= PG1P2WidthRegCmd;
  397. end else if (cmdCnt == 11) begin
  398. DspSpiData <= PG1P3WidthRegCmd;
  399. end else if (cmdCnt == 12) begin
  400. DspSpiData <= PG1P123WidthRegCmd;
  401. end else if (cmdCnt == 13) begin
  402. DspSpiData <= PG2P1DelayRegCmd;
  403. end else if (cmdCnt == 14) begin
  404. DspSpiData <= PG2P2DelayRegCmd;
  405. end else if (cmdCnt == 15) begin
  406. DspSpiData <= PG2P3DelayRegCmd;
  407. end else if (cmdCnt == 16) begin
  408. DspSpiData <= PG2P123DelayRegCmd;
  409. end else if (cmdCnt == 17) begin
  410. DspSpiData <= PG2P1WidthRegCmd;
  411. end else if (cmdCnt == 18) begin
  412. DspSpiData <= PG2P2WidthRegCmd;
  413. end else if (cmdCnt == 19) begin
  414. DspSpiData <= PG2P3WidthRegCmd;
  415. end else if (cmdCnt == 20) begin
  416. DspSpiData <= PG2P123WidthRegCmd;
  417. end else if (cmdCnt == 21) begin
  418. DspSpiData <= PG3P1DelayRegCmd;
  419. end else if (cmdCnt == 22) begin
  420. DspSpiData <= PG3P2DelayRegCmd;
  421. end else if (cmdCnt == 23) begin
  422. DspSpiData <= PG3P3DelayRegCmd;
  423. end else if (cmdCnt == 24) begin
  424. DspSpiData <= PG3P123DelayRegCmd;
  425. end else if (cmdCnt == 25) begin
  426. DspSpiData <= PG3P1WidthRegCmd;
  427. end else if (cmdCnt == 26) begin
  428. DspSpiData <= PG3P2WidthRegCmd;
  429. end else if (cmdCnt == 27) begin
  430. DspSpiData <= PG3P3WidthRegCmd;
  431. end else if (cmdCnt == 28) begin
  432. DspSpiData <= PG3P123WidthRegCmd;
  433. end else if (cmdCnt == 29) begin
  434. DspSpiData <= PG4P1DelayRegCmd;
  435. end else if (cmdCnt == 30) begin
  436. DspSpiData <= PG4P2DelayRegCmd;
  437. end else if (cmdCnt == 31) begin
  438. DspSpiData <= PG4P3DelayRegCmd;
  439. end else if (cmdCnt == 32) begin
  440. DspSpiData <= PG4P123DelayRegCmd;
  441. end else if (cmdCnt == 33) begin
  442. DspSpiData <= PG4P1WidthRegCmd;
  443. end else if (cmdCnt == 34) begin
  444. DspSpiData <= PG4P2WidthRegCmd;
  445. end else if (cmdCnt == 35) begin
  446. DspSpiData <= PG4P3WidthRegCmd;
  447. end else if (cmdCnt == 36) begin
  448. DspSpiData <= PG4P123WidthRegCmd;
  449. end else if (cmdCnt == 37) begin
  450. DspSpiData <= PG5P1DelayRegCmd;
  451. end else if (cmdCnt == 38) begin
  452. DspSpiData <= PG5P2DelayRegCmd;
  453. end else if (cmdCnt == 39) begin
  454. DspSpiData <= PG5P3DelayRegCmd;
  455. end else if (cmdCnt == 40) begin
  456. DspSpiData <= PG5P123DelayRegCmd;
  457. end else if (cmdCnt == 41) begin
  458. DspSpiData <= PG5P1WidthRegCmd;
  459. end else if (cmdCnt == 42) begin
  460. DspSpiData <= PG5P2WidthRegCmd;
  461. end else if (cmdCnt == 43) begin
  462. DspSpiData <= PG5P3WidthRegCmd;
  463. end else if (cmdCnt == 44) begin
  464. DspSpiData <= PG5P123WidthRegCmd;
  465. end else if (cmdCnt == 45) begin
  466. DspSpiData <= PG6P1DelayRegCmd;
  467. end else if (cmdCnt == 46) begin
  468. DspSpiData <= PG6P2DelayRegCmd;
  469. end else if (cmdCnt == 47) begin
  470. DspSpiData <= PG6P3DelayRegCmd;
  471. end else if (cmdCnt == 48) begin
  472. DspSpiData <= PG6P123DelayRegCmd;
  473. end else if (cmdCnt == 49) begin
  474. DspSpiData <= PG6P1WidthRegCmd;
  475. end else if (cmdCnt == 50) begin
  476. DspSpiData <= PG6P2WidthRegCmd;
  477. end else if (cmdCnt == 51) begin
  478. DspSpiData <= PG6P3WidthRegCmd;
  479. end else if (cmdCnt == 52) begin
  480. DspSpiData <= PG6P123WidthRegCmd;
  481. end else if (cmdCnt == 53) begin
  482. DspSpiData <= PG7P1DelayRegCmd;
  483. end else if (cmdCnt == 54) begin
  484. DspSpiData <= PG7P2DelayRegCmd;
  485. end else if (cmdCnt == 55) begin
  486. DspSpiData <= PG7P3DelayRegCmd;
  487. end else if (cmdCnt == 56) begin
  488. DspSpiData <= PG7P123DelayRegCmd;
  489. end else if (cmdCnt == 57) begin
  490. DspSpiData <= PG7P1WidthRegCmd;
  491. end else if (cmdCnt == 58) begin
  492. DspSpiData <= PG7P2WidthRegCmd;
  493. end else if (cmdCnt == 59) begin
  494. DspSpiData <= PG7P3WidthRegCmd;
  495. end else if (cmdCnt == 60) begin
  496. DspSpiData <= DitherCmd;
  497. end else if (cmdCnt == 61) begin
  498. DspSpiData <= MeasNum0RegCmd;
  499. end else if (cmdCnt == 62) begin
  500. DspSpiData <= MeasNum1RegCmd;
  501. end else if (cmdCnt == 63) begin
  502. DspSpiData <= PGMode0RegCmd;
  503. end else if (cmdCnt == 64) begin
  504. DspSpiData <= PGMode1RegCmd;
  505. end else if (cmdCnt == 65) begin
  506. DspSpiData <= MuxCtrl1RegCmd;
  507. end else if (cmdCnt == 66) begin
  508. DspSpiData <= MuxCtrl2RegCmd;
  509. end else if (cmdCnt == 67) begin
  510. DspSpiData <= MuxCtrl3RegCmd;
  511. end else if (cmdCnt == 68) begin
  512. DspSpiData <= AdcCtrl;
  513. end else if (cmdCnt == 99) begin
  514. DspSpiData <= {8'h58,24'd100};
  515. end else if (cmdCnt == 100) begin
  516. DspSpiData <= MeasCmdFft;
  517. end else begin
  518. DspSpiData <= 32'hfffffff;
  519. end
  520. end else if (txCurrState == TX) begin
  521. DspSpiData <= DspSpiData<<1;
  522. end
  523. end
  524. always @(posedge Clk41) begin
  525. if (txCurrState == TX) begin
  526. if (txCnt >= 7'd0) begin
  527. mosi_i <= DspSpiData[31];
  528. end else begin
  529. mosi_i <= 1'b1;
  530. end
  531. end else begin
  532. mosi_i <= 1'b1;
  533. end
  534. end
  535. always @(posedge Clk41) begin
  536. if (txCurrState == TX) begin
  537. ss_i <= 1'b0;
  538. end else begin
  539. ss_i <= 1'b1;
  540. end
  541. end
  542. assign sck_i = Clk41;
  543. always @(posedge Clk41) begin
  544. if (rst) begin
  545. txCurrState <= IDLE;
  546. end else begin
  547. txCurrState <= txNextState;
  548. end
  549. end
  550. always @(*) begin
  551. txNextState = IDLE;
  552. case(txCurrState)
  553. IDLE : begin
  554. if (txWork) begin
  555. txNextState = CMD;
  556. end else begin
  557. txNextState = IDLE;
  558. end
  559. end
  560. CMD : begin
  561. if (!txStop) begin
  562. txNextState = TX;
  563. end else begin
  564. txNextState = IDLE;
  565. end
  566. end
  567. TX : begin
  568. if (txCnt==6'd31) begin
  569. txNextState = PAUSE;
  570. end else begin
  571. txNextState = TX;
  572. end
  573. end
  574. PAUSE : begin
  575. if (pauseCnt==4'd10) begin
  576. txNextState = CMD;
  577. end else begin
  578. txNextState = PAUSE;
  579. end
  580. end
  581. endcase
  582. end
  583. reg [13:0] Data_i;
  584. real pi = 3.14159265358;
  585. real phase = 0;
  586. real phaseInc = 0.001;
  587. real signal;
  588. always @ (posedge Clk50)
  589. begin
  590. if (tb_cnt >= 4505)
  591. begin
  592. phase = phase + phaseInc;
  593. phaseInc <= phaseInc + 0.0005;
  594. signal = $sin(2*pi*phase);
  595. Data_i = 2**12 * signal;
  596. end
  597. else
  598. Data_i = 0;
  599. end
  600. endmodule