S5243TopPulseProfileTb.v 18 KB

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  1. `timescale 1ns / 1ps
  2. //=============================================================================================================
  3. // Тестовая конфигурация:
  4. //
  5. // Режим измерения "Точка в импульсе".
  6. // Количество измерений = 1.
  7. // Выбраный фильтр = 2МГц.
  8. //
  9. // PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
  10. // PG2 -> модулятор. | Шаблон 1 имп.
  11. // PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
  12. // PG4 -> Gating Generator. | Шаблон 1 имп.
  13. //
  14. // Настройки мультиплексоров генераторов:
  15. // PG1MUX_OUT -> INT_TRIG.
  16. // PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
  17. // PG3MUX_OUT -> PG1.
  18. // PG4MUX_OUT -> PG1.
  19. // PG5MUX_OUT -> PG1.
  20. // PG6MUX_OUT -> PG1.
  21. // PG7MUX_OUT -> PG1.
  22. //
  23. // Настройки остальных мультиплексоров:
  24. // MODMUX_OUT -> PG2.
  25. // GATINGMUX_OUT -> PG4.
  26. // SAMPLSTROBEMUX_OUT -> PG3.
  27. // EXTSTARTMUX -> DSPSTART.
  28. //=============================================================================================================
  29. module S5243TopPulseProfileTb;
  30. localparam [4:0] EP1MUXCMD = 5'd14;
  31. localparam [4:0] EP2MUXCMD = 5'd1;
  32. localparam [4:0] EP3MUXCMD = 5'd1;
  33. localparam [4:0] EP4MUXCMD = 5'd1;
  34. localparam [4:0] EP5MUXCMD = 5'd1;
  35. localparam [4:0] EP6MUXCMD = 5'd1;
  36. localparam [4:0] PG1MUXCMD = 5'd13;
  37. localparam [4:0] PG2MUXCMD = 5'd0;
  38. localparam [4:0] PG3MUXCMD = 5'd18;
  39. localparam [4:0] PG4MUXCMD = 5'd18;
  40. localparam [4:0] PG5MUXCMD = 5'd0;
  41. localparam [4:0] PG6MUXCMD = 5'd0;
  42. localparam [4:0] PG7MUXCMD = 5'd0;
  43. localparam [2:0] PG1MODE = 3'd5;
  44. localparam [2:0] PG2MODE = 3'd1;
  45. localparam [2:0] PG3MODE = 3'd3;
  46. localparam [2:0] PG4MODE = 3'd4;
  47. localparam [2:0] PG5MODE = 3'd0;
  48. localparam [2:0] PG6MODE = 3'd0;
  49. localparam [2:0] PG7MODE = 3'd3;
  50. localparam PG1POL = 1'b0;
  51. localparam PG2POL = 1'b0;
  52. localparam PG3POL = 1'b0;
  53. localparam PG4POL = 1'b0;
  54. localparam PG5POL = 1'b0;
  55. localparam PG6POL = 1'b0;
  56. localparam PG7POL = 1'b0;
  57. localparam [4:0] EXTTRIGMUXCMD = 5'd15;
  58. localparam [4:0] DSPTRIGINCMD = 5'h8;
  59. localparam [4:0] MUXSLOWMODCMD = 5'd1;
  60. localparam [4:0] MUXFASTMODCMD = 5'd1;
  61. localparam [4:0] GATINGMUXCMD = 5'd2;
  62. localparam [4:0] SMPLSTRBMUXCMD = 5'd3;
  63. //COMMANDS FOR REG_MAP
  64. parameter [31:0] MeasCmdBypass = {8'h11,8'h0,8'h63,8'h1};
  65. // parameter [31:0] MeasCmdFft = {8'h11,8'h0,8'h63,7'h5,1'b1};
  66. // parameter [31:0] MeasCmd = {8'h11,8'h0,8'h53,8'h0};
  67. // parameter [31:0] MeasCmd = {8'h11,8'h3e,8'h63,8'h0};
  68. parameter [31:0] AdcCtrl = {8'h12,24'h2};
  69. parameter [31:0] SensCtrlCmd = {1'b0,27'h0,4'b1};
  70. // parameter [31:0] DitherCmd = {8'h0E,24'h100192};
  71. parameter [31:0] DitherCmd = {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
  72. parameter [31:0] IfFtwH = {8'h15,16'h0,8'h40};
  73. parameter [31:0] IfFtwL = {8'h16,24'h000000};
  74. parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
  75. parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
  76. //PG7 Cmd
  77. parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
  78. parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd1};
  79. parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd5};
  80. parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd15};
  81. parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
  82. parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd3};
  83. parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd5};
  84. parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
  85. //PG1 Cmd
  86. parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
  87. parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd400};
  88. parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
  89. parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
  90. parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd1};
  91. parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
  92. parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
  93. parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
  94. //PG2 Cmd
  95. parameter [31:0] PG2P1DelayRegCmd = {8'h20,24'd0};
  96. parameter [31:0] PG2P2DelayRegCmd = {8'h21,24'd1};
  97. parameter [31:0] PG2P3DelayRegCmd = {8'h22,24'd5};
  98. parameter [31:0] PG2P123DelayRegCmd = {8'h23,24'd15};
  99. parameter [31:0] PG2P1WidthRegCmd = {8'h24,24'd1};
  100. parameter [31:0] PG2P2WidthRegCmd = {8'h25,24'd3};
  101. parameter [31:0] PG2P3WidthRegCmd = {8'h26,24'd5};
  102. parameter [31:0] PG2P123WidthRegCmd = {8'h27,24'd0};
  103. //PG3 Cmd
  104. parameter [31:0] PG3P1DelayRegCmd = {8'h20,24'd0};
  105. parameter [31:0] PG3P2DelayRegCmd = {8'h21,24'd1};
  106. parameter [31:0] PG3P3DelayRegCmd = {8'h22,24'd5};
  107. parameter [31:0] PG3P123DelayRegCmd = {8'h23,24'd15};
  108. parameter [31:0] PG3P1WidthRegCmd = {8'h24,24'd1};
  109. parameter [31:0] PG3P2WidthRegCmd = {8'h25,24'd3};
  110. parameter [31:0] PG3P3WidthRegCmd = {8'h26,24'd5};
  111. parameter [31:0] PG3P123WidthRegCmd = {8'h27,24'd0};
  112. //PG4 Cmd
  113. parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
  114. parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd18};
  115. parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
  116. parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
  117. parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd1};
  118. parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd10};
  119. parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd7};
  120. parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
  121. //PG5 Cmd
  122. parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
  123. parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
  124. parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
  125. parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
  126. parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd0};
  127. parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
  128. parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
  129. parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
  130. //PG6 Cmd
  131. parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd0};
  132. parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd5};
  133. parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd15};
  134. parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
  135. parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd1};
  136. parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd3};
  137. parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd5};
  138. parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
  139. parameter [31:0] MeasNum0RegCmd = {8'h58,24'd10};
  140. parameter [31:0] MeasNum1RegCmd = {8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
  141. parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
  142. parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
  143. parameter [31:0] MuxCtrl1RegCmd = {8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
  144. parameter [31:0] MuxCtrl2RegCmd = {8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
  145. parameter [31:0] MuxCtrl3RegCmd = {8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
  146. parameter [31:0] MuxCtrl4RegCmd = {8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
  147. //=================================================================================================================================================================================================================
  148. reg Clk41;
  149. reg Clk50;
  150. reg Clk70;
  151. reg [31:0] tb_cnt=4'd0;
  152. reg rst;
  153. reg mosi_i = 1'b0;
  154. reg Miso_i = 1'b0;
  155. reg ss_i;
  156. reg clk_i = 1'b0;
  157. reg [31:0] DspSpiData;
  158. reg startCalcCmdReg;
  159. wire [17:0] cos_value;
  160. wire [17:0] sin_value;
  161. wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
  162. wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
  163. wire ExtTrigger0 = ExtDspTrigNeg0;
  164. wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
  165. wire endMeas;
  166. reg [31:0] cmdCnt;
  167. reg trig0;
  168. reg trig1;
  169. wire trig0R;
  170. wire trig1R;
  171. assign trig0R = trig0;
  172. assign trig1R = trig1;
  173. //==========================================================================================
  174. //clocks gen
  175. always #10 Clk50 = ~Clk50;
  176. always #(14.285714285714/2) Clk70 = ~Clk70;
  177. always #10 clk_i = ~clk_i;
  178. always #(24.390243902439/2) Clk41 = ~Clk41;
  179. wire sck_i;
  180. //==========================================================================================
  181. initial begin
  182. Clk50 = 1'b1;
  183. Clk70 = 1'b1;
  184. rst = 1'b1;
  185. Clk41 = 1'b0;
  186. trig0 = 1'b0;
  187. trig1 = 1'b0;
  188. #100;
  189. rst = 1'b0;
  190. #400;
  191. Clk41 = 1'b0;
  192. end
  193. reg endMeasReg;
  194. always @(posedge Clk41) begin
  195. endMeasReg <= endMeas;
  196. end
  197. wire endMeasNeg = !endMeas&endMeasReg;
  198. always @(posedge Clk70) begin
  199. if (!rst) begin
  200. if (!endMeas) begin
  201. // if (tb_cnt == 3550 | tb_cnt == 3950 |tb_cnt == 4505) begin
  202. if (tb_cnt == 3550) begin
  203. startCalcCmdReg <= 1'b1;
  204. end
  205. end else begin
  206. startCalcCmdReg <= 1'b0;
  207. end
  208. end else begin
  209. startCalcCmdReg <= 1'b0;
  210. end
  211. end
  212. always @(negedge Clk41) begin
  213. if (!rst) begin
  214. tb_cnt <= tb_cnt+1;
  215. end else begin
  216. tb_cnt <= 0;
  217. end
  218. end
  219. wire Adc1DataDa0P;
  220. wire Adc1DataDa1P;
  221. // wire [31:0] test = 32'h2351eb85;
  222. wire [31:0] test = 32'h40000000;
  223. CordicNco
  224. #( .ODatWidth (18),
  225. .PhIncWidth (32),
  226. .IterNum (10),
  227. .EnSinN (0))
  228. ncoInst
  229. (
  230. .Clk_i (Clk50),
  231. .Rst_i (rst),
  232. .Val_i (1'b1),
  233. .PhaseInc_i (test),
  234. .WindVal_i (1'b1),
  235. .WinType_i (),
  236. .Wind_o (),
  237. .Sin_o (sin_value),
  238. .Cos_o (cos_value),
  239. .Val_o ()
  240. );
  241. S5243Top MasterFpga
  242. (
  243. .ClkP_i (Clk50),
  244. .ClkN_i (~Clk50),
  245. .Led_o (),
  246. //------------------------------------------
  247. .Adc1FclkP_i (),
  248. .Adc1FclkN_i (),
  249. .Adc1DataDa0P_i (Adc1DataDa0P),
  250. .Adc1DataDa0N_i (~Adc1DataDa0P),
  251. .Adc1DataDa1P_i (Adc1DataDa1P),
  252. .Adc1DataDa1N_i (~Adc1DataDa1P),
  253. .Adc1DataDb0P_i (Adc1DataDa0P),
  254. .Adc1DataDb0N_i (~Adc1DataDa0P),
  255. .Adc1DataDb1P_i (Adc1DataDa1P),
  256. .Adc1DataDb1N_i (~Adc1DataDa1P),
  257. //------------------------------------------
  258. .Adc2FclkP_i (),
  259. .Adc2FclkN_i (),
  260. .Adc2DataDa0P_i (1'b1),
  261. .Adc2DataDa0N_i (1'b0),
  262. .Adc2DataDa1P_i (1'b1),
  263. .Adc2DataDa1N_i (1'b0),
  264. .Adc2DataDb0P_i (1'b1),
  265. .Adc2DataDb0N_i (1'b0),
  266. .Adc2DataDb1P_i (1'b1),
  267. .Adc2DataDb1N_i (1'b0),
  268. //------------------------------------------
  269. .Adc1InitMosi_o (),
  270. .Adc2InitMosi_o (),
  271. .Adc1InitClk_o (),
  272. .Adc2InitClk_o (),
  273. .Adc1InitCs_o (),
  274. .Adc2InitCs_o (),
  275. .Adc1InitRst_o (),
  276. .Adc2InitRst_o (),
  277. .DitherCtrlCh1_o (),
  278. .DitherCtrlCh2_o (),
  279. //------------------------------------------
  280. .Mosi_i (mosi_i),
  281. .Sck_i (~sck_i),
  282. .Ss_i (ss_i),
  283. .Miso_i (),
  284. .Miso_o (),
  285. .LpOutClk_o (),
  286. .LpOutFs_o (),
  287. .LpOutData_o (),
  288. //fpga-dsp signals
  289. .StartMeas_i (startCalcCmdReg),
  290. .EndMeas_o (endMeas),
  291. .TimersClk_o (),
  292. .Trig6to1_io (),
  293. .Trig6to1Dir_o (),
  294. .DspTrigOut_i (), //Trig from DSP
  295. .DspTrigIn_o (), //Trig To DSP
  296. .Overload_o (),
  297. .PortSel_o (),
  298. //mod out line
  299. .Mod_o (),
  300. //gain lines
  301. .DspReadyForRx_i (1'b0),
  302. .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
  303. .AdcData_i (sin_value[17-:14])
  304. // .AdcData_i (Data_i)
  305. );
  306. parameter IDLE = 2'h0;
  307. parameter CMD = 2'h1;
  308. parameter TX = 2'h2;
  309. parameter PAUSE = 2'h3;
  310. reg [1:0] txCurrState;
  311. reg [1:0] txNextState;
  312. wire txWork = tb_cnt >= 23;
  313. // wire txStop = (cmdCnt >= 90) & (cmdCnt >= 70) & (cmdCnt >= 71);
  314. wire txStop = (cmdCnt >= 251);
  315. reg [6:0] txCnt;
  316. reg [3:0] pauseCnt;
  317. always @(posedge Clk41) begin
  318. if (!rst) begin
  319. if (txCurrState == CMD) begin
  320. if (!txStop) begin
  321. cmdCnt <= cmdCnt+1;
  322. end
  323. end
  324. end else begin
  325. cmdCnt <= 0;
  326. end
  327. end
  328. always @(posedge Clk41) begin
  329. if (!rst) begin
  330. if (txCurrState == TX) begin
  331. txCnt <= txCnt+1;
  332. end else begin
  333. txCnt <= 0;
  334. end
  335. end else begin
  336. txCnt <= 0;
  337. end
  338. end
  339. always @(posedge Clk41) begin
  340. if (!rst) begin
  341. if (txCurrState == PAUSE) begin
  342. pauseCnt <= pauseCnt+1;
  343. end else begin
  344. pauseCnt <= 0;
  345. end
  346. end else begin
  347. pauseCnt <= 0;
  348. end
  349. end
  350. always @(posedge Clk41) begin
  351. if (txCurrState == CMD) begin
  352. if (cmdCnt == 0) begin
  353. DspSpiData <= MeasCmdBypass;
  354. end else if (cmdCnt == 1) begin
  355. DspSpiData <= IfFtwH;
  356. end else if (cmdCnt == 2) begin
  357. DspSpiData <= IfFtwL;
  358. end else if (cmdCnt == 3) begin
  359. DspSpiData <= FilterCorrCmdH;
  360. end else if (cmdCnt == 4) begin
  361. DspSpiData <= FilterCorrCmdL;
  362. end else if (cmdCnt == 5) begin
  363. DspSpiData <= PG1P1DelayRegCmd;
  364. end else if (cmdCnt == 6) begin
  365. DspSpiData <= PG1P2DelayRegCmd;
  366. end else if (cmdCnt == 7) begin
  367. DspSpiData <= PG1P3DelayRegCmd;
  368. end else if (cmdCnt == 8) begin
  369. DspSpiData <= PG1P123DelayRegCmd;
  370. end else if (cmdCnt == 9) begin
  371. DspSpiData <= PG1P1WidthRegCmd;
  372. end else if (cmdCnt == 10) begin
  373. DspSpiData <= PG1P2WidthRegCmd;
  374. end else if (cmdCnt == 11) begin
  375. DspSpiData <= PG1P3WidthRegCmd;
  376. end else if (cmdCnt == 12) begin
  377. DspSpiData <= PG1P123WidthRegCmd;
  378. end else if (cmdCnt == 13) begin
  379. DspSpiData <= PG2P1DelayRegCmd;
  380. end else if (cmdCnt == 14) begin
  381. DspSpiData <= PG2P2DelayRegCmd;
  382. end else if (cmdCnt == 15) begin
  383. DspSpiData <= PG2P3DelayRegCmd;
  384. end else if (cmdCnt == 16) begin
  385. DspSpiData <= PG2P123DelayRegCmd;
  386. end else if (cmdCnt == 17) begin
  387. DspSpiData <= PG2P1WidthRegCmd;
  388. end else if (cmdCnt == 18) begin
  389. DspSpiData <= PG2P2WidthRegCmd;
  390. end else if (cmdCnt == 19) begin
  391. DspSpiData <= PG2P3WidthRegCmd;
  392. end else if (cmdCnt == 20) begin
  393. DspSpiData <= PG2P123WidthRegCmd;
  394. end else if (cmdCnt == 21) begin
  395. DspSpiData <= PG3P1DelayRegCmd;
  396. end else if (cmdCnt == 22) begin
  397. DspSpiData <= PG3P2DelayRegCmd;
  398. end else if (cmdCnt == 23) begin
  399. DspSpiData <= PG3P3DelayRegCmd;
  400. end else if (cmdCnt == 24) begin
  401. DspSpiData <= PG3P123DelayRegCmd;
  402. end else if (cmdCnt == 25) begin
  403. DspSpiData <= PG3P1WidthRegCmd;
  404. end else if (cmdCnt == 26) begin
  405. DspSpiData <= PG3P2WidthRegCmd;
  406. end else if (cmdCnt == 27) begin
  407. DspSpiData <= PG3P3WidthRegCmd;
  408. end else if (cmdCnt == 28) begin
  409. DspSpiData <= PG3P123WidthRegCmd;
  410. end else if (cmdCnt == 29) begin
  411. DspSpiData <= PG4P1DelayRegCmd;
  412. end else if (cmdCnt == 30) begin
  413. DspSpiData <= PG4P2DelayRegCmd;
  414. end else if (cmdCnt == 31) begin
  415. DspSpiData <= PG4P3DelayRegCmd;
  416. end else if (cmdCnt == 32) begin
  417. DspSpiData <= PG4P123DelayRegCmd;
  418. end else if (cmdCnt == 33) begin
  419. DspSpiData <= PG4P1WidthRegCmd;
  420. end else if (cmdCnt == 34) begin
  421. DspSpiData <= PG4P2WidthRegCmd;
  422. end else if (cmdCnt == 35) begin
  423. DspSpiData <= PG4P3WidthRegCmd;
  424. end else if (cmdCnt == 36) begin
  425. DspSpiData <= PG4P123WidthRegCmd;
  426. end else if (cmdCnt == 37) begin
  427. DspSpiData <= PG5P1DelayRegCmd;
  428. end else if (cmdCnt == 38) begin
  429. DspSpiData <= PG5P2DelayRegCmd;
  430. end else if (cmdCnt == 39) begin
  431. DspSpiData <= PG5P3DelayRegCmd;
  432. end else if (cmdCnt == 40) begin
  433. DspSpiData <= PG5P123DelayRegCmd;
  434. end else if (cmdCnt == 41) begin
  435. DspSpiData <= PG5P1WidthRegCmd;
  436. end else if (cmdCnt == 42) begin
  437. DspSpiData <= PG5P2WidthRegCmd;
  438. end else if (cmdCnt == 43) begin
  439. DspSpiData <= PG5P3WidthRegCmd;
  440. end else if (cmdCnt == 44) begin
  441. DspSpiData <= PG5P123WidthRegCmd;
  442. end else if (cmdCnt == 45) begin
  443. DspSpiData <= PG6P1DelayRegCmd;
  444. end else if (cmdCnt == 46) begin
  445. DspSpiData <= PG6P2DelayRegCmd;
  446. end else if (cmdCnt == 47) begin
  447. DspSpiData <= PG6P3DelayRegCmd;
  448. end else if (cmdCnt == 48) begin
  449. DspSpiData <= PG6P123DelayRegCmd;
  450. end else if (cmdCnt == 49) begin
  451. DspSpiData <= PG6P1WidthRegCmd;
  452. end else if (cmdCnt == 50) begin
  453. DspSpiData <= PG6P2WidthRegCmd;
  454. end else if (cmdCnt == 51) begin
  455. DspSpiData <= PG6P3WidthRegCmd;
  456. end else if (cmdCnt == 52) begin
  457. DspSpiData <= PG6P123WidthRegCmd;
  458. end else if (cmdCnt == 53) begin
  459. DspSpiData <= PG7P1DelayRegCmd;
  460. end else if (cmdCnt == 54) begin
  461. DspSpiData <= PG7P2DelayRegCmd;
  462. end else if (cmdCnt == 55) begin
  463. DspSpiData <= PG7P3DelayRegCmd;
  464. end else if (cmdCnt == 56) begin
  465. DspSpiData <= PG7P123DelayRegCmd;
  466. end else if (cmdCnt == 57) begin
  467. DspSpiData <= PG7P1WidthRegCmd;
  468. end else if (cmdCnt == 58) begin
  469. DspSpiData <= PG7P2WidthRegCmd;
  470. end else if (cmdCnt == 59) begin
  471. DspSpiData <= PG7P3WidthRegCmd;
  472. end else if (cmdCnt == 60) begin
  473. DspSpiData <= DitherCmd;
  474. end else if (cmdCnt == 61) begin
  475. DspSpiData <= MeasNum0RegCmd;
  476. end else if (cmdCnt == 62) begin
  477. DspSpiData <= MeasNum1RegCmd;
  478. end else if (cmdCnt == 63) begin
  479. DspSpiData <= PGMode0RegCmd;
  480. end else if (cmdCnt == 64) begin
  481. DspSpiData <= PGMode1RegCmd;
  482. end else if (cmdCnt == 65) begin
  483. DspSpiData <= MuxCtrl1RegCmd;
  484. end else if (cmdCnt == 66) begin
  485. DspSpiData <= MuxCtrl2RegCmd;
  486. end else if (cmdCnt == 67) begin
  487. DspSpiData <= MuxCtrl3RegCmd;
  488. end else if (cmdCnt == 68) begin
  489. DspSpiData <= AdcCtrl;
  490. end else if (cmdCnt == 99) begin
  491. DspSpiData <= {8'h58,24'd100};
  492. end else begin
  493. DspSpiData <= 32'hfffffff;
  494. end
  495. end else if (txCurrState == TX) begin
  496. DspSpiData <= DspSpiData<<1;
  497. end
  498. end
  499. always @(posedge Clk41) begin
  500. if (txCurrState == TX) begin
  501. if (txCnt >= 7'd0) begin
  502. mosi_i <= DspSpiData[31];
  503. end else begin
  504. mosi_i <= 1'b1;
  505. end
  506. end else begin
  507. mosi_i <= 1'b1;
  508. end
  509. end
  510. always @(posedge Clk41) begin
  511. if (txCurrState == TX) begin
  512. ss_i <= 1'b0;
  513. end else begin
  514. ss_i <= 1'b1;
  515. end
  516. end
  517. assign sck_i = Clk41;
  518. always @(posedge Clk41) begin
  519. if (rst) begin
  520. txCurrState <= IDLE;
  521. end else begin
  522. txCurrState <= txNextState;
  523. end
  524. end
  525. always @(*) begin
  526. txNextState = IDLE;
  527. case(txCurrState)
  528. IDLE : begin
  529. if (txWork) begin
  530. txNextState = CMD;
  531. end else begin
  532. txNextState = IDLE;
  533. end
  534. end
  535. CMD : begin
  536. if (!txStop) begin
  537. txNextState = TX;
  538. end else begin
  539. txNextState = IDLE;
  540. end
  541. end
  542. TX : begin
  543. if (txCnt==6'd31) begin
  544. txNextState = PAUSE;
  545. end else begin
  546. txNextState = TX;
  547. end
  548. end
  549. PAUSE : begin
  550. if (pauseCnt==4'd10) begin
  551. txNextState = CMD;
  552. end else begin
  553. txNextState = PAUSE;
  554. end
  555. end
  556. endcase
  557. end
  558. reg [13:0] Data_i;
  559. real pi = 3.14159265358;
  560. real phase = 0;
  561. real phaseInc = 0.001;
  562. real signal;
  563. always @ (posedge Clk50)
  564. begin
  565. if (tb_cnt >= 4505)
  566. begin
  567. phase = phase + phaseInc;
  568. phaseInc <= phaseInc + 0.0005;
  569. signal = $sin(2*pi*phase);
  570. Data_i = 2**12 * signal;
  571. end
  572. else
  573. Data_i = 0;
  574. end
  575. endmodule