S5443/S5443_M/S5443.srcs/sources_1/new/S5443Top.v

`timescale 1ns / 1ps
(* keep_hierarchy = "yes" *)
//////////////////////////////////////////////////////////////////////////////////
// company: 
// engineer: 
// 
// create date:    12:23:20 05/20/2019 
// design name: 
// module name:    S5443Top
// project name: 
// target devices: 
// tool versions: 
// description: 
//
// dependencies: 
//
// revision: 
// revision 0.01 - file created
// additional comments: 
//
//================================================================================
//
//Spi clock for ADC initialization is 15Mhz.
//Spi clock for RegMap work is 41Mhz.
//Нужно сделать процедуру сброса для импульсных измерений, такую же как для обычных, тоесть по детектированию спадающего фронта StartMeas.
//Забрать из команды настройки измерения, биты управления ключем и замкнуть на выходы.
//////////////////////////////////////////////////////////////////////////////////

//  xc7s25-2csga225
// new feature added

module	S5443Top
#(	
	parameter	LpDataWidth			=	16,
	parameter	CtrlWidth			=	4,
	parameter	AdcDataWidth		=	14,
	parameter	ThresholdWidth		=	24,
	parameter	ResultWidth			=	32,
	parameter	ChNum				=	4,
	parameter	PGenNum				=	7,
	parameter	TrigPortsNum		=	6,
	parameter	Ratio				=	8,
	parameter	DelayValue			=	24000,
	parameter	LengthWidth			=	2000,
	parameter	DataWidth			=	24,
	parameter	DataNum				=	26,
	parameter	CmdRegWidth			=	32,
	parameter	HeaderWidth			=	7,
	parameter	CmdDataRegWith		=	24,
	parameter	DataCntWidth		=	5,
	parameter	Divparam			=	4,
	parameter	MeasPeriod			=	44,
	parameter	PhIncWidth			=	32,
	parameter	NcoWidth			=	18
)
(
	//common ports
	input	Clk_i,
	output	Led_o,
	
	//fpga-adc1 data interface
    input	Adc1FclkP_i,
    input	Adc1FclkN_i,
		
    input	Adc1DataDa0P_i,
	input	Adc1DataDa0N_i,
    input	Adc1DataDa1P_i,
    input	Adc1DataDa1N_i,
    	
	input	Adc1DataDb0P_i,
    input	Adc1DataDb0N_i,
    input	Adc1DataDb1P_i,
    input	Adc1DataDb1N_i,
	
	//fpga-adc2 data interface
    input	Adc2FclkP_i,
    input	Adc2FclkN_i,
			
    input	Adc2DataDa0P_i,
    input	Adc2DataDa0N_i,
    input	Adc2DataDa1P_i,
    input	Adc2DataDa1N_i,
	
	input	Adc2DataDb0P_i,
    input	Adc2DataDb0N_i,
    input	Adc2DataDb1P_i,
    input	Adc2DataDb1N_i,
	
	//fpga-adc's initialization interface
	output	AdcInitMosi_o,
	output	AdcInitClk_o,
	output	Adc1InitCs_o,
	output	Adc2InitCs_o,
	output	AdcInitRst_o,
		
	//ditherCtrl
	
	output	DitherCtrlCh1_o,
	output	DitherCtrlCh2_o,
	
	//fpga-dsp cmd interface
	input	Mosi_i,
	input	Sck_i,
	input	Ss_i,
	input	Miso_i,
	output	Miso_o,
	
	//fpga-dsp data interface
	output	LpOutClk_o,
	output	LpOutFs_o,
	output	[LpDataWidth-1:0]	LpOutData_o,
	
	//fpga-dsp signals
	input	StartMeas_i,		//"high"- start meas, "low"-stop meas
	output	StartMeasEvent_o,
	output	EndMeas_o,
	
	output	TimersClk_o,
	
	//trigger's 
	inout	[TrigPortsNum-1:0]	Trig6to1_io,			//Trigger0 from/to external device
	output	[TrigPortsNum-1:0]	Trig6to1Dir_o,		//Trigger0 direction 
	
	input	DspTrigOut_i,		//Trig from DSP
	output	DspTrigIn_o,		//Trig To DSP
	
	//overload lines
	input	OverloadS_i,
	output	Overload_o,
	
	//modulation & active port selection
	
	output	[3:0]	PortSel_o,		//управление модулятором через ключ 
	output	[3:0]	PortSelDir_o,	//управление направлением двунаправленного буффера
	
	//mod out line
	output	Mod_o,
	
	//gain lines
	input	DspReadyForRx_i,
	output	DspReadyForRxToFpgaS_o,
	
	output	StartMeasDsp_o,
	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
	
	///test port for testbench
	input	[AdcDataWidth-1:0]	AdcData_i
);
//================================================================================
//  reg/wire
//================================================================================	
	//captured data
	wire	[AdcDataWidth-1:0]	adc1ChT1Data;
	wire	[AdcDataWidth-1:0]	adc1ChR1Data;
	wire	[AdcDataWidth-1:0]	adc2ChR2Data;
	wire	[AdcDataWidth-1:0]	adc2ChT2Data;
	
	reg		startMeasSync;
	reg		startMeasSyncR;
	reg		startMeasSyncRR;
	wire	startMeasEvent;
	wire	intTrig1;
	reg		startMeasEventReg;
	
	wire	gatingPulse;
	wire	sampleStrobe;
	wire	[ChNum-1:0]	measStartBus;
	wire	measStart;
	
	//spi signals for adc init
	wire	adcInitRst;
	wire	adcInitMosi;
	wire	adcInitSck;
	wire	adc0InitCs;
	wire	adc1InitCs;

	wire	[ResultWidth-1:0]	adc1ImT1;
	wire	[ResultWidth-1:0]	adc1ReT1;
	wire	[ResultWidth-1:0]	adc1ImR1;
	wire	[ResultWidth-1:0]	adc1ReR1;
	
	wire	[ResultWidth-1:0]	adc2ImT2;
	wire	[ResultWidth-1:0]	adc2ReT2;
	wire	[ResultWidth-1:0]	adc2ImR2;
	wire	[ResultWidth-1:0]	adc2ReR2;
	
	wire	measDataRdy;
	
	wire	timersClk;
	
	wire	[ThresholdWidth-1:0]	lowThreshold;
	wire	[ThresholdWidth-1:0]	highThreshold;
	wire	initRst;
	
	wire	gclk;
	
	reg		ledReg;
	
	wire	[CmdRegWidth-1:0]	cmdDataReg;
	wire	cmdDataVal;
	
	wire	[CmdDataRegWith-1:0]	ansReg;	
	wire	[HeaderWidth-1:0]		ansAddr;
	
	wire	[CmdDataRegWith-1:0]	gainCtrl;
	wire	[CmdDataRegWith-1:0]	gainLowThreshT1;
	wire	[CmdDataRegWith-1:0]	gainHighThreshT1;
	wire	[CmdDataRegWith-1:0]	gainLowThreshR1;
	wire	[CmdDataRegWith-1:0]	gainHighThreshR1;
	wire	[CmdDataRegWith-1:0]	gainLowThreshT2;
	wire	[CmdDataRegWith-1:0]	gainHighThreshT2;
	wire	[CmdDataRegWith-1:0]	gainLowThreshR2;
	wire	[CmdDataRegWith-1:0]	gainHighThreshR2;
	
	wire	[ChNum-1:0]				overCtrlChannels;
	wire	[CmdDataRegWith-1:0]	overCtrl	=	{{CmdDataRegWith-ChNum{1'b0}},overCtrlChannels};
	wire	[CmdDataRegWith-1:0]	overThresh;
	wire	[CmdDataRegWith-1:0]	ditherCtrl;
	wire	[CmdDataRegWith-1:0]	windowGenPhase1;
	wire	[CmdDataRegWith-1:0]	windowGenPhase2;
	wire	[CmdDataRegWith-1:0]	adcCtrl;
	wire	[CmdDataRegWith-1:0]	adcDirectRd0;
	wire	[CmdDataRegWith-1:0]	adcDirectRd1;
	wire	[CmdDataRegWith-1:0]	ifFtwL;
	wire	[CmdDataRegWith-1:0]	ifFtwH;
	wire	[CmdDataRegWith-1:0]	measCtrl;
	wire	[CmdDataRegWith-1:0]	amplitudeMod;
	wire	[CmdDataRegWith-1:0]	dspTrigIn;
	wire	[CmdDataRegWith-1:0]	dspTrigOut;
	wire	[CmdDataRegWith-1:0]	dspTrigIn1;
	wire	[CmdDataRegWith-1:0]	dspTrigIn2;
	wire	[CmdDataRegWith-1:0]	dspTrigOut1;
	wire	[CmdDataRegWith-1:0]	dspTrigOut2;
	wire	[CmdDataRegWith-1:0]	filterCorrCoefL;
	wire	[CmdDataRegWith-1:0]	filterCorrCoefH;
	
	wire	trigToDsp0;
	wire	trigToDsp1;
	
	wire	intTrigToExtDev0;
	wire	intTrigToExtDev1;
	
	wire	delayDoneFlag0;
	wire	delayDoneFlag1;
	
	wire	trigEn0;
	wire	trigEn1;
	
	wire	stopMeas;
	reg		stopMeasR;
	
	wire	[NcoWidth-1:0]	ncoCos;
	wire	[NcoWidth-1:0]	ncoSin;
	
	wire	[CmdDataRegWith-1:0]	gainLowThresholdBus		[ChNum-1:0];
	wire	[CmdDataRegWith-1:0]	gainHighThresholdBus	[ChNum-1:0];
	
	wire	[ChNum-1:0]	ampEnNewStates;
	wire	[ChNum-1:0]	sensEn;
	
	wire	[ChNum-1:0]	gainManual;
	wire	[ChNum-1:0]	gainAutoEn;
	
	wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
	wire	overCtrlR	=	|overCtrlChannels[ChNum-1:0];
	
	localparam TESTCNTPARAM	=	32'd100000000;
	reg	[31:0]	testCnt;

	wire	refClk;
	wire	Clk100_o;
	
	wire	measWind;
	
	wire	measTrig;
	wire	trigForIntTrig2;
	wire	intTrig2;
	
	wire	measTrigVal;
	
	wire	refSeqPulse;
	wire	refSeq;
	
	//Pmeas wires
	
	//PG1 Regs
	wire	[CmdDataRegWith-1:0]	pG1P1Del;
	wire	[CmdDataRegWith-1:0]	pG1P2Del;
	wire	[CmdDataRegWith-1:0]	pG1P3Del;
	wire	[CmdDataRegWith-1:0]	pG1P123Del;
	wire	[CmdDataRegWith-1:0]	pG1P1Width;
	wire	[CmdDataRegWith-1:0]	pG1P2Width;
	wire	[CmdDataRegWith-1:0]	pG1P3Width;
	wire	[CmdDataRegWith-1:0]	pG1P123Width;
	
	//PG2 Regs	
	wire	[CmdDataRegWith-1:0]	pG2P1Del;
	wire	[CmdDataRegWith-1:0]	pG2P2Del;
	wire	[CmdDataRegWith-1:0]	pG2P3Del;
	wire	[CmdDataRegWith-1:0]	pG2P123Del;
	wire	[CmdDataRegWith-1:0]	pG2P1Width;
	wire	[CmdDataRegWith-1:0]	pG2P2Width;
	wire	[CmdDataRegWith-1:0]	pG2P3Width;
	wire	[CmdDataRegWith-1:0]	pG2P123Width;	
	
	//PG3 Regs	
	wire	[CmdDataRegWith-1:0]	pG3P1Del;
	wire	[CmdDataRegWith-1:0]	pG3P2Del;
	wire	[CmdDataRegWith-1:0]	pG3P3Del;
	wire	[CmdDataRegWith-1:0]	pG3P123Del;
	wire	[CmdDataRegWith-1:0]	pG3P1Width;
	wire	[CmdDataRegWith-1:0]	pG3P2Width;
	wire	[CmdDataRegWith-1:0]	pG3P3Width;
	wire	[CmdDataRegWith-1:0]	pG3P123Width;
	
	//PG4 Regs	
	wire	[CmdDataRegWith-1:0]	pG4P1Del;
	wire	[CmdDataRegWith-1:0]	pG4P2Del;
	wire	[CmdDataRegWith-1:0]	pG4P3Del;
	wire	[CmdDataRegWith-1:0]	pG4P123Del;
	wire	[CmdDataRegWith-1:0]	pG4P1Width;
	wire	[CmdDataRegWith-1:0]	pG4P2Width;
	wire	[CmdDataRegWith-1:0]	pG4P3Width;
	wire	[CmdDataRegWith-1:0]	pG4P123Width;
	
	//PG5 Regs	
	wire	[CmdDataRegWith-1:0]	pG5P1Del;
	wire	[CmdDataRegWith-1:0]	pG5P2Del;
	wire	[CmdDataRegWith-1:0]	pG5P3Del;
	wire	[CmdDataRegWith-1:0]	pG5P123Del;
	wire	[CmdDataRegWith-1:0]	pG5P1Width;
	wire	[CmdDataRegWith-1:0]	pG5P2Width;
	wire	[CmdDataRegWith-1:0]	pG5P3Width;
	wire	[CmdDataRegWith-1:0]	pG5P123Width;
	
	//PG6 Regs	
	wire	[CmdDataRegWith-1:0]	pG6P1Del;
	wire	[CmdDataRegWith-1:0]	pG6P2Del;
	wire	[CmdDataRegWith-1:0]	pG6P3Del;
	wire	[CmdDataRegWith-1:0]	pG6P123Del;
	wire	[CmdDataRegWith-1:0]	pG6P1Width;
	wire	[CmdDataRegWith-1:0]	pG6P2Width;
	wire	[CmdDataRegWith-1:0]	pG6P3Width;
	wire	[CmdDataRegWith-1:0]	pG6P123Width;
	
	//PG7 Regs	
	wire	[CmdDataRegWith-1:0]	pG7P1Del;
	wire	[CmdDataRegWith-1:0]	pG7P2Del;
	wire	[CmdDataRegWith-1:0]	pG7P3Del;
	wire	[CmdDataRegWith-1:0]	pG7P123Del;
	wire	[CmdDataRegWith-1:0]	pG7P1Width;
	wire	[CmdDataRegWith-1:0]	pG7P2Width;
	wire	[CmdDataRegWith-1:0]	pG7P3Width;
	wire	[CmdDataRegWith-1:0]	pG7P123Width;
	
	wire	[CmdDataRegWith-1:0]	measNum1;
	wire	[CmdDataRegWith-1:0]	measNum2;
	
	wire	[CmdDataRegWith-1:0]	pgMode0;
	wire	[CmdDataRegWith-1:0]	pgMode1;
	
	wire	[CmdDataRegWith-1:0]	muxCtrl1;
	wire	[CmdDataRegWith-1:0]	muxCtrl2;
	wire	[CmdDataRegWith-1:0]	muxCtrl3;
	wire	[CmdDataRegWith-1:0]	muxCtrl4;

	wire	[CmdRegWidth-29:0]	pgModeArray		[PGenNum-1:0];
	wire	pgPulsePolArray		[PGenNum-1:0];
	wire	pgEnEdgeArray		[PGenNum-1:0];
	wire	[PGenNum-1:0]	pgRstArray;
	wire	[6:0]	pGenRst;
	wire	[6:0]	pGenMeasRst;
	wire	pGenRstDone;
	wire	[CmdRegWidth-28:0]	pgMuxCtrlArray	[PGenNum-1:0];
	wire	[CmdRegWidth-28:0]	extTrigMuxCtrlArray	[TrigPortsNum-1:0];
	wire	[TrigPortsNum-1:0]	extTrigDirCmd	=	measCtrl[21:16];
	
	wire	[CmdRegWidth-1:0]	pgP1DelArray	[PGenNum-1:0];
	wire	[CmdRegWidth-1:0]	pgP2DelArray	[PGenNum-1:0];
	wire	[CmdRegWidth-1:0]	pgP3DelArray	[PGenNum-1:0];
	
	wire	[CmdRegWidth-1:0]	pgP1WidthArray	[PGenNum-1:0];
	wire	[CmdRegWidth-1:0]	pgP2WidthArray	[PGenNum-1:0];
	wire	[CmdRegWidth-1:0]	pgP3WidthArray	[PGenNum-1:0];
	
	wire	[PGenNum-1:0]		pulseBus;
	wire	[PGenNum-1:0]		pgMuxedOut;
	wire	[TrigPortsNum-1:0]	extPortsMuxedOut;
	
	wire	measEnd;
	wire	slowMod;
	wire	fastMod;
	wire	[3:0]	modKeyCtrl;
	wire	tirgToDspEvent;
	wire	trigFromDspEvent;
	wire	oscWind;
	wire	oscDataRdFlag;
	
	reg		dspReadyForRxReg;
	reg		dspReadyForRxRegR;
	reg		dspReadyForRxRegRR;
	
	wire	sampleStrobeGenRst;
//================================================================================
//  assignments
//================================================================================	
	
	assign	pgModeArray	[PGenNum-1]	=	pgMode0[21:18];	
	assign	pgModeArray	[PGenNum-2]	=	pgMode0[17:15];	
	assign	pgModeArray	[PGenNum-3]	=	pgMode0[14:12];	
	assign	pgModeArray	[PGenNum-4]	=	pgMode0[11:9];	
	assign	pgModeArray	[PGenNum-5]	=	pgMode0[8:6];	
	assign	pgModeArray	[PGenNum-6]	=	pgMode0[5:3];	
	assign	pgModeArray	[PGenNum-7]	=	pgMode0[2:0];	

	assign	pgPulsePolArray	[PGenNum-1]	=	pgMode1[16];	
	assign	pgPulsePolArray	[PGenNum-2]	=	pgMode1[15];	
	assign	pgPulsePolArray	[PGenNum-3]	=	pgMode1[14];	
	assign	pgPulsePolArray	[PGenNum-4]	=	pgMode1[13];	
	assign	pgPulsePolArray	[PGenNum-5]	=	pgMode1[12];	
	assign	pgPulsePolArray	[PGenNum-6]	=	pgMode1[11];	
	assign	pgPulsePolArray	[PGenNum-7]	=	pgMode1[10];

	assign	pgEnEdgeArray	[PGenNum-1]	=	pgMode1[23];
	assign	pgEnEdgeArray	[PGenNum-2]	=	pgMode1[22];
	assign	pgEnEdgeArray	[PGenNum-3]	=	pgMode1[21];
	assign	pgEnEdgeArray	[PGenNum-4]	=	pgMode1[20];
	assign	pgEnEdgeArray	[PGenNum-5]	=	pgMode1[19];
	assign	pgEnEdgeArray	[PGenNum-6]	=	pgMode1[18];
	assign	pgEnEdgeArray	[PGenNum-7]	=	pgMode1[17];

	assign	pgRstArray	[PGenNum-1]	=	pgMode1[6];
	assign	pgRstArray	[PGenNum-2]	=	pgMode1[5];
	assign	pgRstArray	[PGenNum-3]	=	pgMode1[4];
	assign	pgRstArray	[PGenNum-4]	=	pgMode1[3];
	assign	pgRstArray	[PGenNum-5]	=	pgMode1[2];
	assign	pgRstArray	[PGenNum-6]	=	pgMode1[1];
	assign	pgRstArray	[PGenNum-7]	=	pgMode1[0];
	
	assign	pgMuxCtrlArray	[PGenNum-1]	=	muxCtrl1[19:15];		
	assign	pgMuxCtrlArray	[PGenNum-2]	=	muxCtrl1[14:10];	
	assign	pgMuxCtrlArray	[PGenNum-3]	=	muxCtrl1[9:5];	
	assign	pgMuxCtrlArray	[PGenNum-4]	=	muxCtrl1[4:0];	
	assign	pgMuxCtrlArray	[PGenNum-5]	=	muxCtrl2[19:15];		
	assign	pgMuxCtrlArray	[PGenNum-6]	=	muxCtrl2[14:10];		
	assign	pgMuxCtrlArray	[PGenNum-7]	=	muxCtrl2[9:5];
	
	assign	extTrigMuxCtrlArray	[TrigPortsNum-1]	=	muxCtrl4[19:15];		
	assign	extTrigMuxCtrlArray	[TrigPortsNum-2]	=	muxCtrl4[14:10];	
	assign	extTrigMuxCtrlArray	[TrigPortsNum-3]	=	muxCtrl4[9:5];	
	assign	extTrigMuxCtrlArray	[TrigPortsNum-4]	=	muxCtrl4[4:0];	
	assign	extTrigMuxCtrlArray	[TrigPortsNum-5]	=	muxCtrl3[9:5];		
	assign	extTrigMuxCtrlArray	[TrigPortsNum-6]	=	muxCtrl3[4:0];		
	
	assign	pgP1DelArray[PGenNum-1]	=	{pG7P123Del[7:0],pG7P1Del};
	assign	pgP1DelArray[PGenNum-2]	=	{pG6P123Del[7:0],pG6P1Del};
	assign	pgP1DelArray[PGenNum-3]	=	{pG5P123Del[7:0],pG5P1Del};
	assign	pgP1DelArray[PGenNum-4]	=	{pG4P123Del[7:0],pG4P1Del};
	assign	pgP1DelArray[PGenNum-5]	=	{pG3P123Del[7:0],pG3P1Del};
	assign	pgP1DelArray[PGenNum-6]	=	{pG2P123Del[7:0],pG2P1Del};
	assign	pgP1DelArray[PGenNum-7]	=	{pG1P123Del[7:0],pG1P1Del};
	
	assign	pgP2DelArray[PGenNum-1]	=	{pG7P123Del[15:8],pG7P2Del};
	assign	pgP2DelArray[PGenNum-2]	=	{pG6P123Del[15:8],pG6P2Del};
	assign	pgP2DelArray[PGenNum-3]	=	{pG5P123Del[15:8],pG5P2Del};
	assign	pgP2DelArray[PGenNum-4]	=	{pG4P123Del[15:8],pG4P2Del};
	assign	pgP2DelArray[PGenNum-5]	=	{pG3P123Del[15:8],pG3P2Del};
	assign	pgP2DelArray[PGenNum-6]	=	{pG2P123Del[15:8],pG2P2Del};
	assign	pgP2DelArray[PGenNum-7]	=	{pG1P123Del[15:8],pG1P2Del};
	
	assign	pgP3DelArray[PGenNum-1]	=	{pG7P123Del[23:16],pG7P3Del};
	assign	pgP3DelArray[PGenNum-2]	=	{pG6P123Del[23:16],pG6P3Del};
	assign	pgP3DelArray[PGenNum-3]	=	{pG5P123Del[23:16],pG5P3Del};
	assign	pgP3DelArray[PGenNum-4]	=	{pG4P123Del[23:16],pG4P3Del};
	assign	pgP3DelArray[PGenNum-5]	=	{pG3P123Del[23:16],pG3P3Del};
	assign	pgP3DelArray[PGenNum-6]	=	{pG2P123Del[23:16],pG2P3Del};
	assign	pgP3DelArray[PGenNum-7]	=	{pG1P123Del[23:16],pG1P3Del};

	assign	pgP1WidthArray[PGenNum-1]	=	{pG7P123Width[7:0],pG7P1Width};
	assign	pgP1WidthArray[PGenNum-2]	=	{pG6P123Width[7:0],pG6P1Width};
	assign	pgP1WidthArray[PGenNum-3]	=	{pG5P123Width[7:0],pG5P1Width};
	assign	pgP1WidthArray[PGenNum-4]	=	{pG4P123Width[7:0],pG4P1Width};
	assign	pgP1WidthArray[PGenNum-5]	=	{pG3P123Width[7:0],pG3P1Width};
	assign	pgP1WidthArray[PGenNum-6]	=	{pG2P123Width[7:0],pG2P1Width};
	assign	pgP1WidthArray[PGenNum-7]	=	{pG1P123Width[7:0],pG1P1Width};
	
	assign	pgP2WidthArray[PGenNum-1]	=	{pG7P123Width[15:8],pG7P2Width};
	assign	pgP2WidthArray[PGenNum-2]	=	{pG6P123Width[15:8],pG6P2Width};
	assign	pgP2WidthArray[PGenNum-3]	=	{pG5P123Width[15:8],pG5P2Width};
	assign	pgP2WidthArray[PGenNum-4]	=	{pG4P123Width[15:8],pG4P2Width};
	assign	pgP2WidthArray[PGenNum-5]	=	{pG3P123Width[15:8],pG3P2Width};
	assign	pgP2WidthArray[PGenNum-6]	=	{pG2P123Width[15:8],pG2P2Width};
	assign	pgP2WidthArray[PGenNum-7]	=	{pG1P123Width[15:8],pG1P2Width};
	
	assign	pgP3WidthArray[PGenNum-1]	=	{pG7P123Width[23:16],pG7P3Width};
	assign	pgP3WidthArray[PGenNum-2]	=	{pG6P123Width[23:16],pG6P3Width};
	assign	pgP3WidthArray[PGenNum-3]	=	{pG5P123Width[23:16],pG5P3Width};
	assign	pgP3WidthArray[PGenNum-4]	=	{pG4P123Width[23:16],pG4P3Width};
	assign	pgP3WidthArray[PGenNum-5]	=	{pG3P123Width[23:16],pG3P3Width};
	assign	pgP3WidthArray[PGenNum-6]	=	{pG2P123Width[23:16],pG2P3Width};
	assign	pgP3WidthArray[PGenNum-7]	=	{pG1P123Width[23:16],pG1P3Width};

	assign	adcDataBus	[ChNum-4]	=	adc1ChT1Data;
	assign	adcDataBus	[ChNum-3]	=	adc1ChR1Data;
	assign	adcDataBus	[ChNum-2]	=	adc2ChR2Data;
	assign	adcDataBus	[ChNum-1]	=	adc2ChT2Data;
	
	assign	gainManual	[ChNum-4]	=	gainCtrl[5];
	assign	gainManual	[ChNum-3]	=	gainCtrl[4];
	assign	gainManual	[ChNum-2]	=	gainCtrl[6];
	assign	gainManual	[ChNum-1]	=	gainCtrl[7];
	
	assign	gainAutoEn	[ChNum-4]	=	gainCtrl[1];
	assign	gainAutoEn	[ChNum-3]	=	gainCtrl[0];
	assign	gainAutoEn	[ChNum-2]	=	gainCtrl[2];
	assign	gainAutoEn	[ChNum-1]	=	gainCtrl[3];
	
	assign	AdcInitMosi_o	=	adcInitMosi;
	assign	AdcInitClk_o	=	adcInitSck;			
	assign	Adc1InitCs_o	=	adc0InitCs;
	assign	Adc2InitCs_o	=	adc1InitCs;
	assign	AdcInitRst_o	=	adcCtrl[0];

	assign	Led_o	=	ledReg	|(|ampEnNewStates);
	
	assign	StartMeasEvent_o	=	startMeasEvent;
	
	assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
	
	assign	gainLowThresholdBus		[ChNum-4]	=	gainLowThreshT1;
	assign	gainLowThresholdBus		[ChNum-3]	=	gainLowThreshR1;
	assign	gainLowThresholdBus		[ChNum-2]	=	gainLowThreshR2;
	assign	gainLowThresholdBus		[ChNum-1]	=	gainLowThreshT2;
	
	assign	gainHighThresholdBus	[ChNum-4]	=	gainHighThreshT1;
	assign	gainHighThresholdBus	[ChNum-3]	=	gainHighThreshR1;
	assign	gainHighThresholdBus	[ChNum-2]	=	gainHighThreshR2;
	assign	gainHighThresholdBus	[ChNum-1]	=	gainHighThreshT2;
	
	assign	AmpEn_o	[3]	=	~ampEnNewStates[3];	
	assign	AmpEn_o	[2]	=	~ampEnNewStates[2];	
	assign	AmpEn_o	[1]	=	~ampEnNewStates[0];	
	assign	AmpEn_o	[0]	=	~ampEnNewStates[1];			
	
	assign	Overload_o	=	overCtrlR||OverloadS_i;

	assign	Mod_o	=	fastMod;
	
	assign	PortSel_o		=	~modKeyCtrl;
	assign	PortSelDir_o	=	4'd15;
	
	assign	Trig6to1Dir_o	[0]	=	!measCtrl[16];
	assign	Trig6to1Dir_o	[1]	=	!measCtrl[17];
	assign	Trig6to1Dir_o	[2]	=	!measCtrl[18];
	assign	Trig6to1Dir_o	[3]	=	!measCtrl[19];
	assign	Trig6to1Dir_o	[4]	=	!measCtrl[20];
	assign	Trig6to1Dir_o	[5]	=	!measCtrl[21];
	
	assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:extPortsMuxedOut[0];	//1 - in, 0 - out
	// assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
	assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:extPortsMuxedOut[1];	//1 - in, 0 - out
	// assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
	assign	Trig6to1_io	[2]	=	(measCtrl[18])	?	1'bz:extPortsMuxedOut[2];	//1 - in, 0 - out
	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
	assign	Trig6to1_io	[5]	=	(measCtrl[21])	?	1'bz:extPortsMuxedOut[5];	//1 - in, 0 - out
	
	assign	DspReadyForRxToFpgaS_o	=	dspReadyForRxRegR;
	assign	StartMeasDsp_o	=	startMeasSyncR;
//================================================================================
//  CODING
//================================================================================
integer m;

always	@(posedge	gclk)	begin	//stretching pulse
	stopMeasR	<=	stopMeas;
end

always	@(posedge	gclk)	begin
	if	(!initRst)	begin
		dspReadyForRxReg	<=	DspReadyForRx_i;
		dspReadyForRxRegR	<=	dspReadyForRxReg;
		dspReadyForRxRegRR	<=	dspReadyForRxRegR;
		
		startMeasSync	<=	StartMeas_i;
		startMeasSyncR	<=	startMeasSync;
		startMeasSyncRR	<=	startMeasSyncR;
	end	else	begin
		dspReadyForRxReg	<=	1'b0;
		dspReadyForRxRegR	<=	1'b0;
		dspReadyForRxRegRR	<=	1'b0;
		
		startMeasSync	<=	1'b0;
		startMeasSyncR	<=	1'b0;
		startMeasSyncRR	<=	1'b0;
	end
end

//--------------------------------------------------------------------------------
//	Data Receiving Interface
//--------------------------------------------------------------------------------

IBUF iob_50m_in
(
	.I    			(Clk_i),
	.O         		(gclk)
);
	
Clk200Gen	Clk200Gen 
(
    .Clk_i			(gclk),
    .Rst_i			(initRst),
	.Clk200_o		(refClk),
	.Clk10Timers_o	(TimersClk_o),
	.Clk100_o		(Clk100_o),
	
	.Locked_o		(Locked200)
);

AdcDataInterface	
#(
	.AdcDataWidth	(AdcDataWidth),
	.ChNum			(ChNum),
	.Ratio			(Ratio)
)
AdcDataInterface	
(
	.Clk_i			(gclk),
	.RefClk_i		(refClk),
	.Locked_i		(Locked200),
	.Rst_i			(initRst),
	
	.Adc1FclkP_i	(Adc1FclkP_i),		
	.Adc1FclkN_i	(Adc1FclkN_i),
	
	.testAdc		(AdcData_i),		
	
	.Adc1DataDa0P_i	(Adc1DataDa0P_i),
	.Adc1DataDa0N_i	(Adc1DataDa0N_i),
	.Adc1DataDa1P_i	(Adc1DataDa1P_i),
	.Adc1DataDa1N_i	(Adc1DataDa1N_i),
	
	.Adc1DataDb0P_i	(Adc1DataDb0P_i),
	.Adc1DataDb0N_i	(Adc1DataDb0N_i),
	.Adc1DataDb1P_i	(Adc1DataDb1P_i),
	.Adc1DataDb1N_i	(Adc1DataDb1N_i),
	
	.Adc2FclkP_i	(Adc2FclkP_i),		
	.Adc2FclkN_i	(Adc2FclkN_i),	
	
	.Adc2DataDa0P_i	(Adc2DataDa0P_i),
	.Adc2DataDa0N_i	(Adc2DataDa0N_i),
	.Adc2DataDa1P_i	(Adc2DataDa1P_i),
	.Adc2DataDa1N_i	(Adc2DataDa1N_i),
	
	.Adc2DataDb0P_i	(Adc2DataDb0P_i),	
	.Adc2DataDb0N_i	(Adc2DataDb0N_i),
	.Adc2DataDb1P_i	(Adc2DataDb1P_i),
	.Adc2DataDb1N_i	(Adc2DataDb1N_i),
	
	.Adc1ChT1Data_o	(adc1ChT1Data),
	.Adc1ChR1Data_o	(adc1ChR1Data),
	
	.Adc2ChR2Data_o	(adc2ChR2Data),
	.Adc2ChT2Data_o	(adc2ChT2Data)
);  
 
//--------------------------------------------------------------------------------
//	External DSP Interface
//--------------------------------------------------------------------------------

DspInterface 
#(	
	.ODataWidth			(LpDataWidth),	
	.ResultWidth		(ResultWidth),
	.ChNum				(ChNum),
	.CmdRegWidth		(CmdRegWidth),
	.CmdDataRegWith		(CmdDataRegWith),
	.HeaderWidth		(HeaderWidth),
	.DataCntWidth		(DataCntWidth)
)
ExternalDspInterface
(
	.Clk_i				(gclk),
	.Rst_i				(initRst),
	.OscWind_i			(oscWind),
	.StartMeasDsp_i		(startMeasSyncRR),
	.DspReadyForRx_i	(dspReadyForRxRegRR),
	.MeasNum_i			({measNum2[7:0],measNum1}),
	
	.Mosi_i				(Mosi_i),
	.Sck_i				(Sck_i),
	.Ss_i				(Ss_i),

	.Mode_i				(measCtrl[0]),
	.PortSel_i			(measCtrl[23:22]),
	.DecimFactor_i		(measCtrl[3:1]),
	.IfFtwL_i			(ifFtwL),
	.IfFtwH_i			(ifFtwH),
	
	.OscDataRdFlag_o	(oscDataRdFlag),
	
	.Adc1ChT1Data_i		(adc1ChT1Data),	
	.Adc1ChR1Data_i		(adc1ChR1Data),	
	.Adc2ChR2Data_i		(adc2ChR2Data),	
	.Adc2ChT2Data_i		(adc2ChT2Data),	

	// .Adc1ChT1Data_i		(AdcData_i),	
	// .Adc1ChR1Data_i		(AdcData_i),	
	// .Adc2ChR2Data_i		(AdcData_i),	
	// .Adc2ChT2Data_i		(AdcData_i),	
	
	// .Adc1ChT1Data_i		(14'h1fff),	
	// .Adc1ChR1Data_i		(14'h257f),	
	// .Adc2ChR2Data_i		(14'h1001),	
	// .Adc2ChT2Data_i		(14'h25f8),	
	
	.Mosi_o				(adcInitMosi),
	.Sck_o				(adcInitSck),
	.Ss0_o				(adc0InitCs),
	.Ss1_o				(adc1InitCs),
	.Miso_i				(Miso_i),
	.Miso_o				(Miso_o),
	
	.CmdDataReg_o		(cmdDataReg),
	.CmdDataVal_o		(cmdDataVal),
	
	.AnsReg_i			(ansReg),
	.AnsAddr_o			(ansAddr),
	
	.LpOutFs_o			(LpOutFs_o),
	.LpOutClk_o			(LpOutClk_o),
	.LpOutData_o		(LpOutData_o),
	
	.Adc1T1ImResult_i	(adc1ImT1),
	.Adc1T1ReResult_i	(adc1ReT1),
	.Adc1R1ImResult_i	(adc1ImR1),
	.Adc1R1ReResult_i	(adc1ReR1),
	
	.Adc2R2ImResult_i	(adc2ImR2),
	.Adc2R2ReResult_i	(adc2ReR2),
	.Adc2T2ImResult_i	(adc2ImT2),
	.Adc2T2ReResult_i	(adc2ReT2),
	.ServiseRegData_i	(ampEnNewStates),
	
	.LpOutStart_i		(measDataRdy)
);

//--------------------------------------------------------------------------------
//	Internal DSP calculation module
//--------------------------------------------------------------------------------
NcoRstGen	NcoRstGenInst
(
	.Clk_i				(gclk),
	.Rst_i				(initRst),
	.NcoPhInc_i			({ifFtwH[0+:PhIncWidth-CmdDataRegWith],ifFtwL}),
	.StartMeasEvent_i	(startMeasEvent),
	
	.NcoRst_o			(ncoRst),
	.StartMeasEvent_o	(intTrig1)	
);

InternalDsp	
#(	
	.AdcDataWidth		(AdcDataWidth),
	.ChNum				(ChNum),
	.ResultWidth		(ResultWidth),
	.CmdDataRegWith		(CmdDataRegWith)
)
InternalDsp
(
	.Clk_i					(gclk),
	.WindCalcClk_i			(Clk100_o),
	.Rst_i					(initRst),
	.NcoRst_i				(ncoRst),
	.OscWind_o				(oscWind),

	.Adc1ChT1Data_i			(adc1ChT1Data),	//T1
	.Adc1ChR1Data_i			(adc1ChR1Data),	//R1
	.Adc2ChR2Data_i			(adc2ChR2Data),	//R2
	.Adc2ChT2Data_i			(adc2ChT2Data),	//T2

	// .Adc1ChT1Data_i			(AdcData_i),	//T1
	// .Adc1ChR1Data_i			(AdcData_i),	//R1
	// .Adc2ChR2Data_i			(AdcData_i),	//R2
	// .Adc2ChT2Data_i			(AdcData_i),	//T2

	.GatingPulse_i			(gatingPulse),

	.StartMeas_i			(measStart),
	.StartMeasDsp_i			(startMeasSyncRR),
	.OscDataRdFlag_i		(oscDataRdFlag),

	.MeasNum_i				({measNum2[7:0],measNum1}),

	.MeasCtrl_i				(measCtrl),
	.FilterCorrCoefH_i		(filterCorrCoefH),
	.FilterCorrCoefL_i		(filterCorrCoefL),

	.CalModeEn_i			(adcCtrl[1]),
	.CalModeDone_o			(calDone),

	.IfFtwL_i				(ifFtwL),
	.IfFtwH_i				(ifFtwH),
	
	.NcoSin_o				(ncoSin),
	.NcoCos_o				(ncoCos),
	
	.Adc1ImT1Data_o			(adc1ImT1),
	.Adc1ReT1Data_o			(adc1ReT1),
	.Adc1ImR1Data_o			(adc1ImR1),
	.Adc1ReR1Data_o			(adc1ReR1),
	
	.Adc2ImR2Data_o			(adc2ImR2),
	.Adc2ReR2Data_o			(adc2ReR2),
	.Adc2ImT2Data_o			(adc2ImT2),
	.Adc2ReT2Data_o			(adc2ReT2),
	
	.MeasDataRdy_o			(measDataRdy),
	.EndMeas_o				(stopMeas),
	.MeasWind_o				(measWind),
	.MeasEnd_o				(measEnd),
	.SampleStrobeGenRst_o	(sampleStrobeGenRst)
); 

//--------------------------------------------------------------------------------
//	Reg Map With Config Registers
//--------------------------------------------------------------------------------
RegMap	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.HeaderWidth	(HeaderWidth),
	.CmdDataRegWith	(CmdDataRegWith)
)
RegMapInst
(
	.Clk_i					(gclk),
	.Rst_i					(initRst),
	.PGenRstDone_i			(pGenRstDone),
	
	.Val_i					(cmdDataVal),
	.CalDone_i				(calDone),
	.Data_i					(cmdDataReg),
	.AnsAddr_i				(ansAddr),
	.AnsDataReg_o			(ansReg),
	
	.OverCtrlReg_i			(overCtrl),
	
	.GainCtrlReg_o			(gainCtrl),
	.GainLowThreshT1Reg_o	(gainLowThreshT1),
	.GainHighThreshT1Reg_o	(gainHighThreshT1),		
	.GainLowThreshR1Reg_o	(gainLowThreshR1),
	.GainHighThreshR1Reg_o	(gainHighThreshR1),
	.GainLowThreshT2Reg_o	(gainLowThreshT2),
	.GainHighThreshT2Reg_o	(gainHighThreshT2),
	.GainLowThreshR2Reg_o	(gainLowThreshR2),
	.GainHighThreshR2Reg_o	(gainHighThreshR2),
	.OverThreshReg_o		(overThresh),
	.DitherCtrlReg_o		(ditherCtrl),
	.MeasCtrlReg_o			(measCtrl),
	.AdcCtrlReg_o			(adcCtrl),
	.AdcDirectRd0Reg_o		(adcDirectRd0),
	.AdcDirectRd1Reg_o		(adcDirectRd1),
	.IfFtwRegL_o			(ifFtwL),
	.IfFtwRegH_o			(ifFtwH),
	.FilterCorrCoefRegL_o	(filterCorrCoefL),
	.FilterCorrCoefRegH_o	(filterCorrCoefH),
	.DspTrigInReg_o			(dspTrigIn),		
	.DspTrigOutReg_o		(dspTrigOut),
	.DspTrigIn1Reg_o		(dspTrigIn1),
	.DspTrigIn2Reg_o		(dspTrigIn2),
	.DspTrigOut1Reg_o		(dspTrigOut1),	
	.DspTrigOut2Reg_o		(dspTrigOut2),	
	
	.PG1P1DelayReg_o		(pG1P1Del),
	.PG1P2DelayReg_o		(pG1P2Del),
	.PG1P3DelayReg_o		(pG1P3Del),
	.PG1P123DelayReg_o		(pG1P123Del),
	.PG1P1WidthReg_o		(pG1P1Width),
	.PG1P2WidthReg_o		(pG1P2Width),
	.PG1P3WidthReg_o		(pG1P3Width),
	.PG1P123WidthReg_o		(pG1P123Width),
	
	//PG2 Regs	
	.PG2P1DelayReg_o		(pG2P1Del),
	.PG2P2DelayReg_o		(pG2P2Del),
	.PG2P3DelayReg_o		(pG2P3Del),
	.PG2P123DelayReg_o		(pG2P123Del),
	.PG2P1WidthReg_o		(pG2P1Width),
	.PG2P2WidthReg_o		(pG2P2Width),
	.PG2P3WidthReg_o		(pG2P3Width),
	.PG2P123WidthReg_o		(pG2P123Width),	
	
	//PG3 Regs	
	.PG3P1DelayReg_o		(pG3P1Del),
	.PG3P2DelayReg_o		(pG3P2Del),
	.PG3P3DelayReg_o		(pG3P3Del),
	.PG3P123DelayReg_o		(pG3P123Del),
	.PG3P1WidthReg_o		(pG3P1Width),
	.PG3P2WidthReg_o		(pG3P2Width),
	.PG3P3WidthReg_o		(pG3P3Width),
	.PG3P123WidthReg_o		(pG3P123Width),
	
	//PG4 Regs	
	.PG4P1DelayReg_o		(pG4P1Del),
	.PG4P2DelayReg_o		(pG4P2Del),
	.PG4P3DelayReg_o		(pG4P3Del),
	.PG4P123DelayReg_o		(pG4P123Del),
	.PG4P1WidthReg_o		(pG4P1Width),
	.PG4P2WidthReg_o		(pG4P2Width),
	.PG4P3WidthReg_o		(pG4P3Width),
	.PG4P123WidthReg_o		(pG4P123Width),
	
	//PG5 Regs	
	.PG5P1DelayReg_o		(pG5P1Del),
	.PG5P2DelayReg_o		(pG5P2Del),
	.PG5P3DelayReg_o		(pG5P3Del),
	.PG5P123DelayReg_o		(pG5P123Del),
	.PG5P1WidthReg_o		(pG5P1Width),
	.PG5P2WidthReg_o		(pG5P2Width),
	.PG5P3WidthReg_o		(pG5P3Width),
	.PG5P123WidthReg_o		(pG5P123Width),
	
	//PG6 Regs	
	.PG6P1DelayReg_o		(pG6P1Del),
	.PG6P2DelayReg_o		(pG6P2Del),
	.PG6P3DelayReg_o		(pG6P3Del),
	.PG6P123DelayReg_o		(pG6P123Del),
	.PG6P1WidthReg_o		(pG6P1Width),
	.PG6P2WidthReg_o		(pG6P2Width),
	.PG6P3WidthReg_o		(pG6P3Width),
	.PG6P123WidthReg_o		(pG6P123Width),
	
	//PG7 Regs	
	.PG7P1DelayReg_o		(pG7P1Del),
	.PG7P2DelayReg_o		(pG7P2Del),
	.PG7P3DelayReg_o		(pG7P3Del),
	.PG7P123DelayReg_o		(pG7P123Del),
	.PG7P1WidthReg_o		(pG7P1Width),
	.PG7P2WidthReg_o		(pG7P2Width),
	.PG7P3WidthReg_o		(pG7P3Width),
	.PG7P123WidthReg_o		(pG7P123Width),
	
	.MeasNum1Reg_o			(measNum1),
	.MeasNum2Reg_o			(measNum2),
	
	.PgMode0Reg_o			(pgMode0),
	.PgMode1Reg_o			(pgMode1),
	
	.MuxCtrl1Reg_o			(muxCtrl1),
	.MuxCtrl2Reg_o			(muxCtrl2),
	.MuxCtrl3Reg_o			(muxCtrl3),
	.MuxCtrl4Reg_o			(muxCtrl4)
);

//--------------------------------------------------------------------------------
//	Global FPGA reset generator
//--------------------------------------------------------------------------------	
InitRst FpgaInitRst 
(
	.clk_i		(gclk),
	.signal_o	(initRst)
);

//--------------------------------------------------------------------------------
//	ADC overload detection
//--------------------------------------------------------------------------------	
genvar	i;
generate
	for	(i=0;	i<ChNum;	i=i+1)	begin	:OverControl
		OverloadDetect
		#(	
			.ThresholdWidth		(ThresholdWidth),
			.AdcDataWidth		(AdcDataWidth),
			.MeasPeriod			(MeasPeriod)
		)
		OverloadDetect	
		(
			.Rst_i				(initRst),
			.Clk_i				(gclk),		
			.AdcData_i			(adcDataBus[i]),
			.OverThreshold_i	(overThresh),
			.Overload_o			(overCtrlChannels[i])
		);
	end
endgenerate

//--------------------------------------------------------------------------------
//	Gain Control module	
//--------------------------------------------------------------------------------	
genvar g;
generate
	for	(g=0;	g<ChNum;	g=g+1)	begin	:GainControl
	GainControlWrapper
	#(	
		.AdcDataWidth		(AdcDataWidth),
		.ThresholdWidth		(ThresholdWidth),
		.PhIncWidth			(PhIncWidth),
		.IfNcoOutWidth		(NcoWidth),
		.MeasPeriod			(MeasPeriod)
	)	
	GainControlModule
	(
		.Rst_i				(initRst),
		.Clk_i				(gclk),	
		.StartMeas_i		(sampleStrobe),
		
		.NcoSin_i			(ncoSin),
		.NcoCos_i			(ncoCos),
		
		.AdcData_i			(adcDataBus[g]),
		// .AdcData_i			(AdcData_i),
		
		.GainLowThreshold_i	(gainLowThresholdBus[g]),
		.GainHighThreshold_i(gainHighThresholdBus[g]),
		.GainAutoEn_i		(gainAutoEn[g]),
		.GainManualState_i	(gainManual[g]),
		
		.AmpEnNewState_o	(ampEnNewStates[g]),
		.SensEn_o			(sensEn[g]),
		.MeasStart_o		(measStartBus[g])
	);
	end
endgenerate

StartAfterGainSel	
#(	
	.ChNum	(ChNum)
)	
StartAfterGainSelInst
(
	.Rst_i			(initRst),
	.GainCtrl_i		(gainAutoEn),
	.MeasStart_i	(measStartBus),
	
	.MeasStart_o	(measStart)
);
//--------------------------------------------------------------------------------
//	Trig TO/FROM DSP	
//--------------------------------------------------------------------------------	

Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
DspTrigMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(measNum2[13:9]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(1'b0),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(7'd0),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(DspTrigIn_o)
);

//--------------------------------------------------------------------------------
//	Dither Gen 
//--------------------------------------------------------------------------------	
DitherGenv2	DitherGenInst
(
	.Rst_i				(initRst),
	.Clk_i				(gclk),	
	
	.DitherCmd_i		(ditherCtrl),
	.DitherCtrlT2R2_o	(DitherCtrlCh1_o),
	.DitherCtrlT1R1_o	(DitherCtrlCh2_o)
);

//--------------------------------------------------------------------------------
//	MeasTrigMux 
//--------------------------------------------------------------------------------	
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
MeasTrigMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(muxCtrl3[14:10]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(startMeasSyncRR),
	.IntTrig_i		(1'b0),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(7'b0),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(measTrig)
);

//--------------------------------------------------------------------------------
//	MeasStartEventGen
//--------------------------------------------------------------------------------	
MeasStartEventGen	MeasStartEventGenInst
(
	.Rst_i				(initRst),
	.Clk_i				(gclk),
	
	.MeasTrig_i			(measTrig),
	.StartMeasDsp_i		(startMeasSyncRR),
	
	.StartMeasEvent_o	(startMeasEvent),
	.InitTrig_o			()
);
//--------------------------------------------------------------------------------
//	IntTrig2 Mux
//--------------------------------------------------------------------------------	

TrigInt2Mux
#(	
	.PGenNum		(PGenNum)
)
InitTrig2Mux
(
	.Rst_i			(initRst),
	
	.MuxCtrl_i		(muxCtrl3[23:20]),
	.PulseBus_i		(pulseBus),
	
	.MuxOut_o		(trigForIntTrig2)
);	

//--------------------------------------------------------------------------------
//	MeasStartEventGen
//--------------------------------------------------------------------------------	
MeasStartEventGen	IntTrig2GenInst
(
	.Rst_i				(initRst),
	.Clk_i				(gclk),
	
	.MeasTrig_i			(trigForIntTrig2),
	// .StartMeasDsp_i		(startMeasEvent),
	.StartMeasDsp_i		(intTrig1),
	
	.StartMeasEvent_o	(),
	.InitTrig_o			(intTrig2)
);

//--------------------------------------------------------------------------------
//	Pulse Meas modules
//--------------------------------------------------------------------------------	

//--------------------------------------------------------------------------------
//	Pulse Gens 
//--------------------------------------------------------------------------------	

PGenRstGenerator	PGenRstGen	
(
	.Rst_i		(initRst),
	.Clk_i		(gclk),
	
	.PGenRst_i	(pgRstArray),
	
	.PGenRst_o	(pGenRst),
	.RstDone_o	(pGenRstDone)
);	

genvar j;
generate
for	(j=0;	j<PGenNum;	j=j+1)	begin	:PGen
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
PulseGenMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(pgMuxCtrlArray[j]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(intTrig1),
	.IntTrig2_i		(intTrig2),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(pgMuxedOut[j])
);	

PulseGen
#(	
	.CmdRegWidth	(CmdRegWidth)
)
PulseGenerator
(
	// .Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
	.Rst_i			(initRst|pGenMeasRst[j]),
	.Clk_i			(gclk),
	.EnPulse_i		(pgMuxedOut[j]),
	
	.PulsePol_i		(pgPulsePolArray[j]),
	.EnEdge_i		(pgEnEdgeArray[j]),
	.Mode_i			(pgModeArray[j]),
	.P1Del_i		(pgP1DelArray[j]),
	.P2Del_i		(pgP2DelArray[j]),
	.P3Del_i		(pgP3DelArray[j]),
	.P1Width_i		(pgP1WidthArray[j]),
	.P2Width_i		(pgP2WidthArray[j]),
	.P3Width_i		(pgP3WidthArray[j]),
	
	.Pulse_o		(pulseBus[j])
);	

// PulseGenV2
// #(	
	// .CmdRegWidth	(CmdRegWidth)
// )
// TestPgen
// (
	// .Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
	// .Clk_i			(gclk),
	// .EnPulse_i		(pgMuxedOut[j]),
	
	// .PulsePol_i		(pgPulsePolArray[j]),
	// .EnEdge_i		(pgEnEdgeArray[j]),
	// .Mode_i			(pgModeArray[j]),
	// .P1Del_i		(pgP1DelArray[j]),
	// .P2Del_i		(pgP2DelArray[j]),
	// .P3Del_i		(pgP3DelArray[j]),
	// .P1Width_i		(pgP1WidthArray[j]),
	// .P2Width_i		(pgP2WidthArray[j]),
	// .P3Width_i		(pgP3WidthArray[j]),
	
	// .Pulse_o		()
// );

end
endgenerate



//--------------------------------------------------------------------------------
//	External ports mux 
//--------------------------------------------------------------------------------	

genvar l;
generate
for	(l=0;	l<TrigPortsNum;	l=l+1)	begin	:ExtPortsMux
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
ExtPortsMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(extTrigMuxCtrlArray[l]),

	.DspTrigOut_i	(DspTrigOut_i),
	.DspStartCmd_i	(startMeasSyncRR), //tut nichego nebilo 14.02.2023 zamknul suda startMeasSync
	.IntTrig_i		(intTrig1),
	.IntTrig2_i		(intTrig2),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(extPortsMuxedOut[l])
);	
end
endgenerate


//--------------------------------------------------------------------------------
//	SlowMod Out Muxer
//--------------------------------------------------------------------------------	
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
SlowModMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(measNum2[18:14]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(1'b0),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(slowMod)
);

//--------------------------------------------------------------------------------
//	FastMod Out Muxer
//--------------------------------------------------------------------------------	
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
FastModMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(measNum2[23:19]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(1'b0),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(fastMod)
);

//--------------------------------------------------------------------------------
//	Software Gating
//--------------------------------------------------------------------------------	
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
GatingMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(muxCtrl3[19:15]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(1'b0),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(gatingPulse)
);

//--------------------------------------------------------------------------------
//	SampleStrobeMux
//--------------------------------------------------------------------------------	
Mux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
SampleStrobeMux
(
	.Rst_i			(initRst),

	.MuxCtrl_i		(muxCtrl2[4:0]),

	.DspTrigOut_i	(1'b0),
	.DspStartCmd_i	(1'b0),
	.IntTrig_i		(intTrig1),
	.IntTrig2_i		(1'b0),
	.PulseBus_i		(pulseBus),
	.ExtPortsBus_i	(Trig6to1_io),
	
	.MuxOut_o		(sampleStrobe)
);

//--------------------------------------------------------------------------------
//	SampleStrobeGenRstDemux
//--------------------------------------------------------------------------------	
SampleStrobeGenRstDemux	
#(	
	.CmdRegWidth	(CmdRegWidth),
	.PGenNum		(PGenNum),
	.TrigPortsNum	(TrigPortsNum)
)
SampleStrobeGenRstDemux
(
	.Rst_i			(initRst),
	.MuxCtrl_i		(muxCtrl2[4:0]),
	// .GenRst_i		(stopMeas),
	.GenRst_i		(sampleStrobeGenRst),
	
	.RstDemuxOut_o	(pGenMeasRst)
);	

//--------------------------------------------------------------------------------
//	Active Port Selection
//--------------------------------------------------------------------------------	
ActivePortSelector	ActivePortSel
(
	.Rst_i		(initRst),
	
	.Mod_i		(slowMod),
	.Ctrl_i		(measCtrl[7:4]),
	
	.Ctrl_o		(modKeyCtrl)
);

//--------------------------------------------------------------------------------
//	Debug led
//--------------------------------------------------------------------------------	
always	@(posedge	gclk)	begin
	if	(initRst)	begin
		testCnt	<=	32'b0;
	end	else	if	(testCnt !=	TESTCNTPARAM)	begin
		testCnt	<=	testCnt+1;
	end	else	begin
		testCnt	<=	32'd0;
	end
end

always	@(posedge	gclk)	begin
	if	(initRst)	begin
		ledReg	<=	1'b0;
	end	else	if	((testCnt ==	TESTCNTPARAM-1))	begin
		ledReg	<=	~ledReg;
	end	
end


endmodule