module ClkGen (
  input Clk_i,
  input [3:0] ClkDiv_i,
  input Rst_i,
  output Clk_o
);

reg [16:0] cnt;

reg clk;
wire clk_o;


always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        cnt <= 0;
    end
    else begin 
        if (cnt >= ClkDiv_i-1) begin 
            cnt <= 0;
        end
        else begin 
            cnt <= cnt + 1;
        end
    end
end

assign Clk_o = (cnt < ClkDiv_i/2) ? 1 : 0;







endmodule