module ClkCh (
    input Rst_i,
    input clkCh,
    input clkOutMMCM,
    input clkMan,

    output SpiClk_o



);


reg spiClkReg;

wire spiClk;

assign spiClk = spiClkReg;



always @(*) begin 
    if (Rst_i) begin 
        spiClkReg = 0;
    end
    else begin 
        if (clkCh) begin 
            spiClkReg = clkOutMMCM;
        end
        else begin 
            spiClkReg = clkMan;
        end
    end
end



BUFG BUFG_inst (
   .O(SpiClk_o), // 1-bit output: Clock output
   .I(spiClk)  // 1-bit input: Clock input
);








endmodule



