module ClkDivSync #(
    parameter WIDTH = 4,
    parameter STAGES = 3



)
(
    input ClkFast_i,
    input ClkSlow_i,
    input [WIDTH-1:0] ClkDiv_i,

    output [WIDTH-1:0] ClkDiv_o
);


//lauch registers 
reg [WIDTH-1:0] clkDivReg;

// capture registers
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;


assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];



always @(posedge ClkFast_i) begin
    clkDivReg <= ClkDiv_i;
end





always @(posedge ClkSlow_i) begin
    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
end





endmodule