set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}]
set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}]
set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}]
set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}]
set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}]
set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}]
set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}]
set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}]
set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}]
set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}]
set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}]



set_property PACKAGE_PIN B15 [get_ports {SmcData_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[0]}]
set_property PACKAGE_PIN B14 [get_ports {SmcData_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[1]}]
set_property PACKAGE_PIN B11 [get_ports {SmcData_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[2]}]
set_property PACKAGE_PIN B12 [get_ports {SmcData_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[3]}]
set_property PACKAGE_PIN A12 [get_ports {SmcData_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[4]}]
set_property PACKAGE_PIN B9 [get_ports {SmcData_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[5]}]
set_property PACKAGE_PIN K14 [get_ports {SmcData_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[6]}]
set_property PACKAGE_PIN A11 [get_ports {SmcData_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[7]}]
set_property PACKAGE_PIN A6 [get_ports {SmcData_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[8]}]
set_property PACKAGE_PIN A13 [get_ports {SmcData_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[9]}]
set_property PACKAGE_PIN A10 [get_ports {SmcData_io[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[10]}]
set_property PACKAGE_PIN B6 [get_ports {SmcData_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[11]}]
set_property PACKAGE_PIN A5 [get_ports {SmcData_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[12]}]
set_property PACKAGE_PIN B10 [get_ports {SmcData_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[13]}]
set_property PACKAGE_PIN A8 [get_ports {SmcData_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[14]}]
set_property PACKAGE_PIN A14 [get_ports {SmcData_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_io[15]}]

set_property PACKAGE_PIN B13 [get_ports SmcAmsN_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAmsN_i]


set_property PACKAGE_PIN C6 [get_ports Led_o]
set_property IOSTANDARD LVCMOS33 [get_ports Led_o]

set_property PACKAGE_PIN A9 [get_ports SmcAwe_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i]

set_property PACKAGE_PIN C5 [get_ports SmcAre_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i]

set_property PACKAGE_PIN C8 [get_ports SmcAoe_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i]

set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}]
set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}]


set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]

set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]

set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]

set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]

set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]

set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]

set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]

#==========================================================================
#	SPI INTERFACES

#SPI0
set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]

set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]

set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]

set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]

set_property PACKAGE_PIN J3 [get_ports {Mosi1_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[0]}]

set_property PACKAGE_PIN M3 [get_ports {Mosi2_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]

set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]

set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]



set_property PACKAGE_PIN H2 [get_ports {SpiDir_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[0]}]









#SPI1
set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
set_property PACKAGE_PIN R2 [get_ports {Mosi1_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[1]}]
set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]

set_property PACKAGE_PIN M1 [get_ports {SpiDir_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[1]}]



#SPI2
set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
set_property PACKAGE_PIN D2 [get_ports {Mosi1_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[2]}]
set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]


set_property PACKAGE_PIN C1 [get_ports {SpiDir_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[2]}]


#SPI3
set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
set_property PACKAGE_PIN R8 [get_ports {Mosi1_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[3]}]
set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]

set_property PACKAGE_PIN P7 [get_ports {SpiDir_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[3]}]



#SPI4
set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
set_property PACKAGE_PIN P12 [get_ports {Mosi1_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[4]}]
set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]


set_property PACKAGE_PIN R12 [get_ports {SpiDir_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[4]}]



#SPI5
set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
set_property PACKAGE_PIN R5 [get_ports LoCsReg_o]
set_property IOSTANDARD LVCMOS33 [get_ports LoCsReg_o]
set_property PACKAGE_PIN R4 [get_ports {Ss_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
set_property PACKAGE_PIN R7 [get_ports {SsFlash_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
set_property PACKAGE_PIN P3 [get_ports {Mosi0_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
set_property PACKAGE_PIN R6 [get_ports {Mosi1_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[5]}]
set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
# set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]


set_property PACKAGE_PIN R3 [get_ports {SpiDir_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[5]}]



#SPI6
set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
set_property PACKAGE_PIN C4 [get_ports {Mosi1_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_io[6]}]
set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[5]}]
set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]

set_property PACKAGE_PIN B2 [get_ports {SpiDir_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiDir_o[6]}]


set_property PACKAGE_PIN M7 [get_ports LD_o]
set_property IOSTANDARD LVCMOS33 [get_ports LD_o]

#==========================================================================
#	INPUT CLOCKS

set_property PACKAGE_PIN M10 [get_ports Clk123_i]
set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SmcAre_i_IBUF]






set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]

set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]

set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]]


set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]]


set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]]


set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]]


set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]]


set_false_path -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks Clk123_i]
# set_false_path -from [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]]




set_clock_groups -asynchronous -group [get_clocks [list Clk123_i [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]]]

set_clock_groups -logically_exclusive -group [get_clocks [list [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]]]]

set_property PULLUP true [get_ports {SsFlash_o[6]}]
set_property PULLUP true [get_ports {SsFlash_o[5]}]
set_property PULLUP true [get_ports {SsFlash_o[4]}]
set_property PULLUP true [get_ports {SsFlash_o[3]}]
set_property PULLUP true [get_ports {SsFlash_o[2]}]
set_property PULLUP true [get_ports {SsFlash_o[1]}]
set_property PULLUP true [get_ports {SsFlash_o[0]}]

set_property PULLUP true [get_ports {Ss_o[6]}]
set_property PULLUP true [get_ports {Ss_o[5]}]
set_property PULLUP true [get_ports {Ss_o[4]}]
set_property PULLUP true [get_ports {Ss_o[3]}]
set_property PULLUP true [get_ports {Ss_o[2]}]
set_property PULLUP true [get_ports {Ss_o[1]}]
set_property PULLUP true [get_ports {Ss_o[0]}]


# connect_debug_port u_ila_0/probe1 [get_nets [list {toRegMapAddr[1]} {toRegMapAddr[2]} {toRegMapAddr[3]} {toRegMapAddr[4]} {toRegMapAddr[5]} {toRegMapAddr[6]} {toRegMapAddr[7]} {toRegMapAddr[8]} {toRegMapAddr[9]}]]
# connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/Spi0ClkReg_o[0]} {RegMap_inst/Spi0ClkReg_o[1]} {RegMap_inst/Spi0ClkReg_o[2]} {RegMap_inst/Spi0ClkReg_o[3]} {RegMap_inst/Spi0ClkReg_o[4]} {RegMap_inst/Spi0ClkReg_o[5]} {RegMap_inst/Spi0ClkReg_o[6]} {RegMap_inst/Spi0ClkReg_o[7]}]]
# connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/TxFifoCtrlReg0_i[0]} {RegMap_inst/TxFifoCtrlReg0_i[1]} {RegMap_inst/TxFifoCtrlReg0_i[2]} {RegMap_inst/TxFifoCtrlReg0_i[8]} {RegMap_inst/TxFifoCtrlReg0_i[9]} {RegMap_inst/TxFifoCtrlReg0_i[10]} {RegMap_inst/TxFifoCtrlReg0_i[11]} {RegMap_inst/TxFifoCtrlReg0_i[12]} {RegMap_inst/TxFifoCtrlReg0_i[13]} {RegMap_inst/TxFifoCtrlReg0_i[14]} {RegMap_inst/TxFifoCtrlReg0_i[15]}]]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]




# connect_debug_port u_ila_0/probe14 [get_nets [list {ansData[0]} {ansData[1]} {ansData[2]} {ansData[3]} {ansData[4]} {ansData[5]} {ansData[6]} {ansData[7]} {ansData[8]} {ansData[9]} {ansData[10]} {ansData[11]} {ansData[12]} {ansData[13]} {ansData[14]} {ansData[15]}]]




# connect_debug_port u_ila_0/probe4 [get_nets [list {Mosi1_io_OBUF[5]}]]

# create_debug_core u_ila_0 ila
# set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
# set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
# set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
# set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
# set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
# set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
# set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
# set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
# set_property port_width 1 [get_debug_ports u_ila_0/clk]
# connect_debug_port u_ila_0/clk [get_nets [list gclk]]
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
# set_property port_width 32 [get_debug_ports u_ila_0/probe0]
# connect_debug_port u_ila_0/probe0 [get_nets [list {SpiGen[5].SPIm_inst/txLenght[0]} {SpiGen[5].SPIm_inst/txLenght[1]} {SpiGen[5].SPIm_inst/txLenght[2]} {SpiGen[5].SPIm_inst/txLenght[3]} {SpiGen[5].SPIm_inst/txLenght[4]} {SpiGen[5].SPIm_inst/txLenght[5]} {SpiGen[5].SPIm_inst/txLenght[6]} {SpiGen[5].SPIm_inst/txLenght[7]} {SpiGen[5].SPIm_inst/txLenght[8]} {SpiGen[5].SPIm_inst/txLenght[9]} {SpiGen[5].SPIm_inst/txLenght[10]} {SpiGen[5].SPIm_inst/txLenght[11]} {SpiGen[5].SPIm_inst/txLenght[12]} {SpiGen[5].SPIm_inst/txLenght[13]} {SpiGen[5].SPIm_inst/txLenght[14]} {SpiGen[5].SPIm_inst/txLenght[15]} {SpiGen[5].SPIm_inst/txLenght[16]} {SpiGen[5].SPIm_inst/txLenght[17]} {SpiGen[5].SPIm_inst/txLenght[18]} {SpiGen[5].SPIm_inst/txLenght[19]} {SpiGen[5].SPIm_inst/txLenght[20]} {SpiGen[5].SPIm_inst/txLenght[21]} {SpiGen[5].SPIm_inst/txLenght[22]} {SpiGen[5].SPIm_inst/txLenght[23]} {SpiGen[5].SPIm_inst/txLenght[24]} {SpiGen[5].SPIm_inst/txLenght[25]} {SpiGen[5].SPIm_inst/txLenght[26]} {SpiGen[5].SPIm_inst/txLenght[27]} {SpiGen[5].SPIm_inst/txLenght[28]} {SpiGen[5].SPIm_inst/txLenght[29]} {SpiGen[5].SPIm_inst/txLenght[30]} {SpiGen[5].SPIm_inst/txLenght[31]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
# set_property port_width 1 [get_debug_ports u_ila_0/probe1]
# connect_debug_port u_ila_0/probe1 [get_nets [list {Mosi3_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
# set_property port_width 16 [get_debug_ports u_ila_0/probe2]
# connect_debug_port u_ila_0/probe2 [get_nets [list {SmcData_io_IBUF[0]} {SmcData_io_IBUF[1]} {SmcData_io_IBUF[2]} {SmcData_io_IBUF[3]} {SmcData_io_IBUF[4]} {SmcData_io_IBUF[5]} {SmcData_io_IBUF[6]} {SmcData_io_IBUF[7]} {SmcData_io_IBUF[8]} {SmcData_io_IBUF[9]} {SmcData_io_IBUF[10]} {SmcData_io_IBUF[11]} {SmcData_io_IBUF[12]} {SmcData_io_IBUF[13]} {SmcData_io_IBUF[14]} {SmcData_io_IBUF[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
# set_property port_width 1 [get_debug_ports u_ila_0/probe3]
# connect_debug_port u_ila_0/probe3 [get_nets [list {Sck_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
# set_property port_width 1 [get_debug_ports u_ila_0/probe4]
# connect_debug_port u_ila_0/probe4 [get_nets [list {Sck_o_OBUF[5]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
# set_property port_width 1 [get_debug_ports u_ila_0/probe5]
# connect_debug_port u_ila_0/probe5 [get_nets [list {Mosi2_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
# set_property port_width 1 [get_debug_ports u_ila_0/probe6]
# connect_debug_port u_ila_0/probe6 [get_nets [list {Mosi1_io_IBUF[5]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
# set_property port_width 1 [get_debug_ports u_ila_0/probe7]
# connect_debug_port u_ila_0/probe7 [get_nets [list {Mosi0_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
# set_property port_width 1 [get_debug_ports u_ila_0/probe8]
# connect_debug_port u_ila_0/probe8 [get_nets [list {Mosi0_o_OBUF[5]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
# set_property port_width 11 [get_debug_ports u_ila_0/probe9]
# connect_debug_port u_ila_0/probe9 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
# set_property port_width 1 [get_debug_ports u_ila_0/probe10]
# connect_debug_port u_ila_0/probe10 [get_nets [list {Ss_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
# set_property port_width 16 [get_debug_ports u_ila_0/probe11]
# connect_debug_port u_ila_0/probe11 [get_nets [list {spi0TxFifoCtrl[0]} {spi0TxFifoCtrl[1]} {spi0TxFifoCtrl[2]} {spi0TxFifoCtrl[3]} {spi0TxFifoCtrl[4]} {spi0TxFifoCtrl[5]} {spi0TxFifoCtrl[6]} {spi0TxFifoCtrl[7]} {spi0TxFifoCtrl[8]} {spi0TxFifoCtrl[9]} {spi0TxFifoCtrl[10]} {spi0TxFifoCtrl[11]} {spi0TxFifoCtrl[12]} {spi0TxFifoCtrl[13]} {spi0TxFifoCtrl[14]} {spi0TxFifoCtrl[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
# set_property port_width 1 [get_debug_ports u_ila_0/probe12]
# connect_debug_port u_ila_0/probe12 [get_nets [list {SsFlash_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
# set_property port_width 16 [get_debug_ports u_ila_0/probe13]
# connect_debug_port u_ila_0/probe13 [get_nets [list {spi0CsDelay[0]} {spi0CsDelay[1]} {spi0CsDelay[2]} {spi0CsDelay[3]} {spi0CsDelay[4]} {spi0CsDelay[5]} {spi0CsDelay[6]} {spi0CsDelay[7]} {spi0CsDelay[8]} {spi0CsDelay[9]} {spi0CsDelay[10]} {spi0CsDelay[11]} {spi0CsDelay[12]} {spi0CsDelay[13]} {spi0CsDelay[14]} {spi0CsDelay[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
# set_property port_width 16 [get_debug_ports u_ila_0/probe14]
# connect_debug_port u_ila_0/probe14 [get_nets [list {dataFromRxFifo[0][15]} {dataFromRxFifo[0][14]} {dataFromRxFifo[0][13]} {dataFromRxFifo[0][12]} {dataFromRxFifo[0][11]} {dataFromRxFifo[0][10]} {dataFromRxFifo[0][9]} {dataFromRxFifo[0][8]} {dataFromRxFifo[0][7]} {dataFromRxFifo[0][6]} {dataFromRxFifo[0][5]} {dataFromRxFifo[0][4]} {dataFromRxFifo[0][3]} {dataFromRxFifo[0][2]} {dataFromRxFifo[0][1]} {dataFromRxFifo[0][0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
# set_property port_width 16 [get_debug_ports u_ila_0/probe15]
# connect_debug_port u_ila_0/probe15 [get_nets [list {spi0RxFifoCtrl[0]} {spi0RxFifoCtrl[1]} {spi0RxFifoCtrl[2]} {spi0RxFifoCtrl[3]} {spi0RxFifoCtrl[4]} {spi0RxFifoCtrl[5]} {spi0RxFifoCtrl[6]} {spi0RxFifoCtrl[7]} {spi0RxFifoCtrl[8]} {spi0RxFifoCtrl[9]} {spi0RxFifoCtrl[10]} {spi0RxFifoCtrl[11]} {spi0RxFifoCtrl[12]} {spi0RxFifoCtrl[13]} {spi0RxFifoCtrl[14]} {spi0RxFifoCtrl[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
# set_property port_width 1 [get_debug_ports u_ila_0/probe16]
# connect_debug_port u_ila_0/probe16 [get_nets [list {SpiRst_o_OBUF[0]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
# set_property port_width 16 [get_debug_ports u_ila_0/probe17]
# connect_debug_port u_ila_0/probe17 [get_nets [list {spi0CsCtrl[0]} {spi0CsCtrl[1]} {spi0CsCtrl[2]} {spi0CsCtrl[3]} {spi0CsCtrl[4]} {spi0CsCtrl[5]} {spi0CsCtrl[6]} {spi0CsCtrl[7]} {spi0CsCtrl[8]} {spi0CsCtrl[9]} {spi0CsCtrl[10]} {spi0CsCtrl[11]} {spi0CsCtrl[12]} {spi0CsCtrl[13]} {spi0CsCtrl[14]} {spi0CsCtrl[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
# set_property port_width 16 [get_debug_ports u_ila_0/probe18]
# connect_debug_port u_ila_0/probe18 [get_nets [list {spi0Ctrl[0]} {spi0Ctrl[1]} {spi0Ctrl[2]} {spi0Ctrl[3]} {spi0Ctrl[4]} {spi0Ctrl[5]} {spi0Ctrl[6]} {spi0Ctrl[7]} {spi0Ctrl[8]} {spi0Ctrl[9]} {spi0Ctrl[10]} {spi0Ctrl[11]} {spi0Ctrl[12]} {spi0Ctrl[13]} {spi0Ctrl[14]} {spi0Ctrl[15]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe19]
# set_property port_width 32 [get_debug_ports u_ila_0/probe19]
# connect_debug_port u_ila_0/probe19 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[8]} {toFifoData[9]} {toFifoData[10]} {toFifoData[11]} {toFifoData[12]} {toFifoData[13]} {toFifoData[14]} {toFifoData[15]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[24]} {toFifoData[25]} {toFifoData[26]} {toFifoData[27]} {toFifoData[28]} {toFifoData[29]} {toFifoData[30]} {toFifoData[31]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
# set_property port_width 1 [get_debug_ports u_ila_0/probe20]
# connect_debug_port u_ila_0/probe20 [get_nets [list SmcAre_i_IBUF]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
# set_property port_width 1 [get_debug_ports u_ila_0/probe21]
# connect_debug_port u_ila_0/probe21 [get_nets [list SmcAwe_i_IBUF]]
# set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
# set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
# set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
# connect_debug_port dbg_hub/clk [get_nets gclk]
