module Sync1bit #(
    parameter WIDTH = 1,
    parameter STAGES = 3



)
(
    input ClkFast_i,
    input ClkSlow_i,
    input TxEn_i,
    input RstReg_i,

    output [WIDTH-1:0] TxEn_o,
    output [WIDTH-1:0] RstReg_o

);
//lauch registers 
reg spiTxEnReg;
reg rstReg;
// capture registers
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] spiTxEnReg_c;
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rstReg_c;

assign TxEn_o = spiTxEnReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];


always @(posedge ClkFast_i) begin
    spiTxEnReg <= TxEn_i;
    rstReg <= RstReg_i;
end





always @(posedge ClkSlow_i) begin 
    spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
    rstReg_c <= {rstReg_c[(STAGES-1)*WIDTH-1:0], rstReg};
end





endmodule