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Добавил BUFGMUX

Anatoliy Chigirinskiy 11 months ago
parent
commit
05bf61f15b

File diff suppressed because it is too large
+ 95 - 50
constrs_1/new/S5443_3.xdc


+ 5 - 5
sources_1/new/ClkManager/MmcmClkMux.v

@@ -43,7 +43,7 @@ wire clkOutMMCM;
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
-assign clkOutMMCM = clkOutMMCMReg;
+assign ClkOutMMCM_o = clkOutMMCMReg;
 
 //================================================================================
 //	CODING
@@ -66,9 +66,9 @@ always @(*) begin
 	end
 end
 
-BUFG BUFG_inst (
-	.O(ClkOutMMCM_o),	// 1-bit output: Clock output
-	.I(clkOutMMCM)		// 1-bit input: Clock input
-);
+// BUFG BUFG_inst (
+// 	.O(ClkOutMMCM_o),	// 1-bit output: Clock output
+// 	.I(clkOutMMCM)		// 1-bit input: Clock input
+// );
 
 endmodule

+ 26 - 17
sources_1/new/ClkManager/SpiClkMux.v

@@ -42,24 +42,33 @@ assign spiClk = spiClkReg;
 //================================================================================
 //	CODING
 //================================================================================ 
-always @(*) begin 
-	if (Rst_i) begin 
-		spiClkReg = 0;
-	end
-	else begin 
-		if (clkCh) begin 
-			spiClkReg = clkOutMMCM;
-		end
-		else begin 
-			spiClkReg = clkMan;
-		end
-	end
-end
+// always @(*) begin 
+// 	if (Rst_i) begin 
+// 		spiClkReg = 0;
+// 	end
+// 	else begin 
+// 		if (clkCh) begin 
+// 			spiClkReg = clkOutMMCM;
+// 		end
+// 		else begin 
+// 			spiClkReg = clkMan;
+// 		end
+// 	end
+// end
 
-BUFG BUFG_inst (
-	.O(SpiClk_o),	// 1-bit output: Clock output
-	.I(spiClk)		// 1-bit input: Clock input
-);
+// BUFG BUFG_inst (
+// 	.O(SpiClk_o),	// 1-bit output: Clock output
+// 	.I(spiClk)		// 1-bit input: Clock input
+// );
+
+   BUFGMUX #(
+   )
+   BUFGMUX_inst (
+      .O(SpiClk_o),   // 1-bit output: Clock output
+      .I0(clkMan), // 1-bit input: Clock input (S=0)
+      .I1(clkOutMMCM), // 1-bit input: Clock input (S=1)
+      .S(clkCh)    // 1-bit input: Clock select
+   );
 
 endmodule
 

+ 1 - 1
sources_1/new/SpiR/SPIm.v

@@ -59,7 +59,7 @@ module SPIm
     reg [2:0] delayCnt;
     reg stopFlag;
     
-    (* dont_touch = "true" *) wire [31:0] txLenght = ssNum+Lag_i+Lead_i;
+    wire [31:0] txLenght = ssNum+Lag_i+Lead_i;
     //================================================================================
     //  ASSIGNMENTS
     //================================================================================