Добавил регистры Set и Clear

sources_1/new/RegMap/RegMap.v

@@ -112,6 +112,8 @@ module RegMap #(
 	output reg [CMD_REG_WIDTH/2-1:0] Spi6RxFifoReg_o,
 
 	output [CMD_REG_WIDTH/2-1:0] SpiTxRxEnReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] SpiTxRxEnSetReg_o,
+	output reg [CMD_REG_WIDTH/2-1:0] SpiTxRxEnClrReg_o,
 	output [CMD_REG_WIDTH-1:0] GPIOAReg_o,
 
 	output [CMD_REG_WIDTH/2-1:0] AnsDataReg_o,
@@ -221,6 +223,11 @@ module RegMap #(
 	localparam SPI_6_RX_FIFO 				= 12'h24c;
 	
 	localparam SPI_TX_RX_EN 	= 12'hF00;
+	/* Set register */
+	localparam SPI_TX_RX_EN_SET = 12'hF04;
+	/* Clear register */
+	localparam SPI_TX_RX_EN_CLR = 12'hF08;
+
 	localparam GPIO_CTRL_ADDR 	= 12'hFF0;
 	localparam GPIO_CTRL_ADDR_S = 12'hFF2;
 	
@@ -283,6 +290,8 @@ module RegMap #(
 			Spi6TxFifoCtrlReg_o <= 0;
 			Spi6RxFifoCtrlReg_o <= 0;
 			spiTxRxEnReg 		<= 0;
+			SpiTxRxEnSetReg_o 	<= 0;
+			SpiTxRxEnClrReg_o 	<= 0;
 			GPIOAReg 			<= 0;
 			GPIOARegS 			<= 0;
 			ledReg 				<= 0;
@@ -421,6 +430,12 @@ module RegMap #(
 							SPI_TX_RX_EN : begin 
 								spiTxRxEnReg <= Data_i;
 							end
+							SPI_TX_RX_EN_SET : begin 
+								spiTxRxEnReg <= spiTxRxEnReg | Data_i;
+							end
+							SPI_TX_RX_EN_CLR : begin 
+								spiTxRxEnReg <= (spiTxRxEnReg) & (~Data_i);
+							end
 							GPIO_CTRL_ADDR : begin 
 								GPIOAReg <= Data_i;
 							end
@@ -563,6 +578,12 @@ module RegMap #(
 							SPI_TX_RX_EN : begin 
 								spiTxRxEnReg[15:8] <= Data_i[15:8];
 							end
+							SPI_TX_RX_EN_SET : begin 
+								spiTxRxEnReg[15:8] <= spiTxRxEnReg[15:8] | Data_i[15:8];
+							end
+							SPI_TX_RX_EN_CLR : begin 
+								spiTxRxEnReg[15:8] <= (spiTxRxEnReg[15:8]) & (~Data_i[15:8]);
+							end
 							GPIO_CTRL_ADDR : begin 
 								GPIOAReg[15:8] <= Data_i[15:8];
 							end
@@ -705,6 +726,12 @@ module RegMap #(
 							SPI_TX_RX_EN : begin 
 								spiTxRxEnReg[7:0] <= Data_i[7:0];
 							end
+							SPI_TX_RX_EN_SET : begin 
+								spiTxRxEnReg[7:0] <= spiTxRxEnReg[7:0] | Data_i[7:0];
+							end
+							SPI_TX_RX_EN_CLR : begin 
+								spiTxRxEnReg[7:0] <= (spiTxRxEnReg[7:0]) & (~Data_i[7:0]);
+							end
 							GPIO_CTRL_ADDR : begin 
 								GPIOAReg[7:0] <= Data_i[7:0];
 							end
@@ -897,6 +924,12 @@ module RegMap #(
 				SPI_TX_RX_EN : begin 
 					ansReg = spiTxRxEnReg;
 				end
+				SPI_TX_RX_EN_SET : begin 
+					ansReg = SpiTxRxEnSetReg_o;
+				end
+				SPI_TX_RX_EN_CLR : begin 
+					ansReg = SpiTxRxEnClrReg_o;
+				end
 				GPIO_CTRL_ADDR : begin 
 					ansReg = GPIOAReg;
 				end

sources_1/new/S5443_3Top.v

@@ -193,6 +193,8 @@ module S5443_3Top
 	wire [CMD_REG_WIDTH-1:0] spi6RxFifoCtrlRR;
 	
 	wire [CMD_REG_WIDTH-1:0] spiTxRxEn;
+	wire [CMD_REG_WIDTH-1:0] spiTxRxEnSet;
+	wire [CMD_REG_WIDTH-1:0] spiTxRxEnClr;
 	wire [CMD_REG_WIDTH-1:0] Gpio;
 	
 	wire [ADDR_REG_WIDTH-1:0]	toRegMapAddr;
@@ -685,6 +687,8 @@ module S5443_3Top
 		.Spi6RxFifoCtrlReg_o	(spi6RxFifoCtrl),
 		
 		.SpiTxRxEnReg_o			(spiTxRxEn),
+		.SpiTxRxEnSetReg_o		(spiTxRxEnSet),
+		.SpiTxRxEnClrReg_o		(spiTxRxEnClr),
 		.GPIOAReg_o				(Gpio),
 
 		.AnsDataReg_o			(ansData),

sources_1/new/S5443_3_tb.v

@@ -111,6 +111,8 @@ localparam SpiTxRxEn5 = 1'b0;
 localparam SpiTxRxEn6 = 1'b0;
 
 localparam [15:0] SpiTxRxEnRegData = {8'h0, SpiTxRxEn6, SpiTxRxEn5, SpiTxRxEn4, SpiTxRxEn3, SpiTxRxEn2, SpiTxRxEn1, SpiTxRxEn0};
+localparam [15:0] SpiTxRxEnRegDataSet = {8'h0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+localparam [15:0] SpiTxRxEnRegDataClr = {8'h0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1};
 
 
 
@@ -209,6 +211,8 @@ localparam [10:0] Spi6RxFifoAddr = BaseAddr6 + 28;
 //***********************************************
 
 localparam SpiTxRxEnAddr = 11'h780;
+localparam SpiTxRxEnSetAddr = 11'h782;
+localparam SpiTxRxEnClrAddr = 11'h784;
 
 //***********************************************
 //	           GPIO Reg Adress
@@ -219,8 +223,8 @@ localparam GPIOAddr = 11'hFF0;
 //***********************************************
 //	           ASSIGNS
 //***********************************************
-assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
-assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
+assign SmcBe_i = (tb_cnt >0 && tb_cnt <=48) ? 2'b00 : 2'b11;
+assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 48) ? 1'b0 : 1'b1;
 assign smcData = SmcData_i;
 assign mosi1_io = (!Mode0) ? mosi0_o : 1'bz;
 
@@ -259,7 +263,7 @@ always @(posedge Clk_i) begin
         SmcAwe_i <= 1'b1;
     end
     else begin 
-        if (tb_cnt > 0 && tb_cnt <= 44) begin 
+        if (tb_cnt > 0 && tb_cnt <= 48) begin 
             if (tb_cnt % 2 != 0) begin 
                 SmcAwe_i <= 1'b1;
             end
@@ -270,17 +274,12 @@ always @(posedge Clk_i) begin
     end
 end
 
-    
-
-
-
-
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         SmcAddr_i <= 0;
     end
     else begin
-        if (tb_cnt < 27) begin
+        if (tb_cnt < 31) begin
         case (tb_cnt)
         0: begin 
             SmcAddr_i <= BaseAddr0;
@@ -309,6 +308,12 @@ always @(posedge Clk_i) begin
         23 : begin 
             SmcAddr_i <= SpiTxRxEnAddr;
         end
+        25 : begin 
+            SmcAddr_i <= SpiTxRxEnSetAddr;
+        end
+        27 : begin 
+            SmcAddr_i <= SpiTxRxEnClrAddr;
+        end
         endcase
         end
         else begin 
@@ -328,7 +333,7 @@ always @(posedge Clk_i) begin
         SmcData_i <= 16'h0;
     end
     else begin
-        if (tb_cnt < 27 ) begin  
+        if (tb_cnt < 31 ) begin  
             case (tb_cnt)
             0 : begin 
                 SmcData_i <= Spi0CtrlRegData;
@@ -357,6 +362,12 @@ always @(posedge Clk_i) begin
             23 : begin 
                 SmcData_i <= SpiTxRxEnRegData;
             end
+            25 : begin 
+                SmcData_i <= SpiTxRxEnRegDataSet;
+            end
+            27 : begin 
+                SmcData_i <= SpiTxRxEnRegDataClr;
+            end
             endcase
         end
         else begin