Рефакторинг модуля DataMuxer

.gitignore

@@ -35,3 +35,4 @@ packages/
 /sources_1/new/MMCM/ClkGen_tb.v
 /sources_1/new/MMCM/ClkGen_tb.v
 /sources_1/new/S5443_3Top.v.orig
+/Docs/~$$NEW Структурная схема BY5443v новая шина вер_3.~vsd

sources_1/new/Mux/DataMuxer.v

@@ -1,86 +1,95 @@
-
-module DataMuxer 
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SmcInDataMux
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module SmcInDataMux 
 #(
-    parameter	CmdRegWidth	=	16,
-    parameter	AddrRegWidth=	12,
-	
-	parameter	FifoNum	=	7,
+	parameter	CMD_REG_WIDTH	=	16,
+	parameter	ADDR_REG_WIDTH	=	12,
 	
-	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
-	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
-	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
-	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
-	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
-	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
-	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
-	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
+	parameter	FIFO_NUM	=	7,
 	
-	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
-	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
-	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
-	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
-	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
-	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
-	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
-	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
-	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
-	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
-	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
-	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
-	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
-	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26,
-
-	parameter Fifo0ReadLsbAddr		= 12'h0+12'd28,
-	parameter Fifo0ReadMsbAddr		= 12'h0+12'd30,
-	parameter Fifo1ReadLsbAddr		= 12'h50+12'd28,
-	parameter Fifo1ReadMsbAddr		= 12'h50+12'd30,
-	parameter Fifo2ReadLsbAddr		= 12'hf0+12'd28,
-	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd30,
-	parameter Fifo3ReadLsbAddr		= 12'h140+12'd28,
-	parameter Fifo3ReadMsbAddr		= 12'h140+12'd30,
-	parameter Fifo4ReadLsbAddr		= 12'h190+12'd28,
-	parameter Fifo4ReadMsbAddr		= 12'h190+12'd30,
-	parameter Fifo5ReadLsbAddr		= 12'h1e0+12'd28,
-	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd30,
-	parameter Fifo6ReadLsbAddr		= 12'h230+12'd28,
-	parameter Fifo6ReadMsbAddr		= 12'h230+12'd30
-
+	parameter	FIFO_0_WRITE_LSB_ADDR	=	12'h0+12'd24,
+	parameter	FIFO_0_WRITE_MSB_ADDR	=	12'h0+12'd26,
+	parameter	FIFO_1_WRITE_LSB_ADDR	=	12'h50+12'd24,
+	parameter	FIFO_1_WRITE_MSB_ADDR	=	12'h50+12'd26,
+	parameter	FIFO_2_WRITE_LSB_ADDR	=	12'hf0+12'd24,
+	parameter	FIFO_2_WRITE_MSB_ADDR	=	12'hf0+12'd26,
+	parameter	FIFO_3_WRITE_LSB_ADDR	=	12'h140+12'd24,
+	parameter	FIFO_3_WRITE_MSB_ADDR	=	12'h140+12'd26,
+	parameter	FIFO_4_WRITE_LSB_ADDR	=	12'h190+12'd24,
+	parameter	FIFO_4_WRITE_MSB_ADDR	=	12'h190+12'd26,
+	parameter	FIFO_5_WRITE_LSB_ADDR	=	12'h1e0+12'd24,
+	parameter	FIFO_5_WRITE_MSB_ADDR	=	12'h1e0+12'd26,
+	parameter	FIFO_6_WRITE_LSB_ADDR	=	12'h230+12'd24,
+	parameter	FIFO_6_WRITE_MSB_ADDR	=	12'h230+12'd26,
 
+	parameter	FIFO_0_READ_LSB_ADDR	=	12'h0+12'd28,
+	parameter	FIFO_0_READ_MSB_ADDR	=	12'h0+12'd30,
+	parameter	FIFO_1_READ_LSB_ADDR	=	12'h50+12'd28,
+	parameter	FIFO_1_READ_MSB_ADDR	=	12'h50+12'd30,
+	parameter	FIFO_2_READ_LSB_ADDR	=	12'hf0+12'd28,
+	parameter	FIFO_2_READ_MSB_ADDR	=	12'hf0+12'd30,
+	parameter	FIFO_3_READ_LSB_ADDR	=	12'h140+12'd28,
+	parameter	FIFO_3_READ_MSB_ADDR	=	12'h140+12'd30,
+	parameter	FIFO_4_READ_LSB_ADDR	=	12'h190+12'd28,
+	parameter	FIFO_4_READ_MSB_ADDR	=	12'h190+12'd30,
+	parameter	FIFO_5_READ_LSB_ADDR	=	12'h1e0+12'd28,
+	parameter	FIFO_5_READ_MSB_ADDR	=	12'h1e0+12'd30,
+	parameter	FIFO_6_READ_LSB_ADDR	=	12'h230+12'd28,
+	parameter	FIFO_6_READ_MSB_ADDR	=	12'h230+12'd30
 )
 (
-    input	Clk_i,
-    input	Rst_i,
+	input	Clk_i,
+	input	Rst_i,
 
 	input	SmcVal_i,
-	input	[CmdRegWidth-1:0]	SmcData_i,
-    input	[AddrRegWidth-1:0]	SmcAddr_i,
+	input	[CMD_REG_WIDTH-1:0]		SmcData_i,
+	input	[ADDR_REG_WIDTH-1:0]	SmcAddr_i,
 
 	output	RequestToFifo_o,
 
 	output	reg	ToRegMapVal_o,
-	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
-    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
-	
-	output	reg	[FifoNum-1:0]	ToFifoVal_o,
-	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
+	output	reg	[CMD_REG_WIDTH-1:0]		ToRegMapData_o,
+	output	reg	[ADDR_REG_WIDTH-1:0]	ToRegMapAddr_o,
 	
+	output	reg	[FIFO_NUM-1:0]	ToFifoVal_o,
+	output	reg	[CMD_REG_WIDTH*2*FIFO_NUM-1:0]	ToFifoData_o
 );
+
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	wire	requestToFifo0	=((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
-	wire	requestToFifo1	=((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
-	wire	requestToFifo2	=((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
-	wire	requestToFifo3	=((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
-	wire	requestToFifo4	=((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
-	wire	requestToFifo5	=((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
-	wire	requestToFifo6	=((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
+	wire	requestToFifo0	=((SmcAddr_i==FIFO_0_WRITE_LSB_ADDR||SmcAddr_i==FIFO_0_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_0_READ_LSB_ADDR||SmcAddr_i==FIFO_0_READ_MSB_ADDR));
+	wire	requestToFifo1	=((SmcAddr_i==FIFO_1_WRITE_LSB_ADDR||SmcAddr_i==FIFO_1_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_1_READ_LSB_ADDR||SmcAddr_i==FIFO_1_READ_MSB_ADDR));
+	wire	requestToFifo2	=((SmcAddr_i==FIFO_2_WRITE_LSB_ADDR||SmcAddr_i==FIFO_2_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_2_READ_LSB_ADDR||SmcAddr_i==FIFO_2_READ_MSB_ADDR));
+	wire	requestToFifo3	=((SmcAddr_i==FIFO_3_WRITE_LSB_ADDR||SmcAddr_i==FIFO_3_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_3_READ_LSB_ADDR||SmcAddr_i==FIFO_3_READ_MSB_ADDR));
+	wire	requestToFifo4	=((SmcAddr_i==FIFO_4_WRITE_LSB_ADDR||SmcAddr_i==FIFO_4_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_4_READ_LSB_ADDR||SmcAddr_i==FIFO_4_READ_MSB_ADDR));
+	wire	requestToFifo5	=((SmcAddr_i==FIFO_5_WRITE_LSB_ADDR||SmcAddr_i==FIFO_5_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_5_READ_LSB_ADDR||SmcAddr_i==FIFO_5_READ_MSB_ADDR));
+	wire	requestToFifo6	=((SmcAddr_i==FIFO_6_WRITE_LSB_ADDR||SmcAddr_i==FIFO_6_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_6_READ_LSB_ADDR||SmcAddr_i==FIFO_6_READ_MSB_ADDR));
 	
 	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
+
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 	assign	RequestToFifo_o	=	requestToFifo;
+
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -88,7 +97,6 @@ module DataMuxer
 //================================================================================
 //	CODING
 //================================================================================
-
 	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 		if	(Rst_i)	begin
 			ToRegMapVal_o	<=	1'b0;
@@ -100,67 +108,67 @@ module DataMuxer
 		end	else	begin
 			if	(requestToFifo)	begin	
 				case(SmcAddr_i)	
-					Fifo0WriteLsbAddr:	begin
+					FIFO_0_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[0]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*0+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo0WriteMsbAddr:	begin
+					FIFO_0_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[0]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*1+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo1WriteLsbAddr:	begin
+					FIFO_1_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[1]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*2+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo1WriteMsbAddr:	begin
+					FIFO_1_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[1]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*3+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo2WriteLsbAddr:	begin
+					FIFO_2_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[2]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*4+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo2WriteMsbAddr:	begin
+					FIFO_2_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[2]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*5+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo3WriteLsbAddr:	begin
+					FIFO_3_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[3]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*6+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo3WriteMsbAddr:	begin
+					FIFO_3_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[3]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*7+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo4WriteLsbAddr:	begin
+					FIFO_4_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[4]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*8+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo4WriteMsbAddr:	begin
+					FIFO_4_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[4]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*9+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo5WriteLsbAddr:	begin
+					FIFO_5_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[5]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*10+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo5WriteMsbAddr:	begin
+					FIFO_5_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[5]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*11+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 									
-					Fifo6WriteLsbAddr:	begin
+					FIFO_6_WRITE_LSB_ADDR:	begin
 										ToFifoVal_o[6]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*12+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
-					Fifo6WriteMsbAddr:	begin
+					FIFO_6_WRITE_MSB_ADDR:	begin
 										ToFifoVal_o[6]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
+										ToFifoData_o[CMD_REG_WIDTH*13+:CMD_REG_WIDTH]	<=	SmcData_i;
 									end
 				endcase
 				ToRegMapAddr_o	<=	0;
@@ -174,4 +182,4 @@ module DataMuxer
 			end
 		end
 	end
-	endmodule
+endmodule