Исправлены ошибки при обработке сигнала BE. Отлажен обмен по 16 бит, с использованием сигнала BE.

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -77,11 +77,11 @@ FifoCtrl FifoCtrl_inst (
 
 
 
-DataFifoTx	DataFifoTx
+DataFifo	DataFifoTx
 ( 
 	.wr_clk		(WrClk_i), 
 	.rd_clk		(RdClk_i), 
-	.rst		(FifoTxRst_i),
+//	.rst		(FifoTxRst_i),
 	.din		(ToFifoData_i), 
 	.wr_en		(txFifoWrEn), 
 	.rd_en		(txFifoRdEn), 
@@ -90,11 +90,11 @@ DataFifoTx	DataFifoTx
 	.empty		(emptyFlagTx)
 );
 
-DataFifoRx	DataFifoRx
+DataFifo	DataFifoRx
 ( 
 	.wr_clk		(RdClk_i), 
 	.rd_clk		(WrClk_i),
-	.rst		(FifoRxRst_i), 
+	//.rst		(FifoRxRst_i), 
 	.din		(ToFifoRxData_i), 
 	.wr_en		(rxFifoWrEn), 
 	.rd_en		(rxFifoRdEn), 

sources_1/new/DspSmc/SmcRx.v

@@ -39,6 +39,7 @@ module	SmcRx
 	
 	input	[DataInOutWidth-1:0]	AnsData_i,
 	
+	output	[1:0]	Be_o,
 	output	[DataInOutWidth-1:0]	Data_o,
 	output	[AddrWidth-1:0]	Addr_o,
 	output	Val_o
@@ -53,6 +54,7 @@ module	SmcRx
 	reg	valReg;
 	
 	reg	[DataInOutWidth-1:0]	outDataReg;
+	reg	[1:0]	beReg;
 //================================================================================
 //  LOCALPARAM
 
@@ -61,6 +63,7 @@ module	SmcRx
 	assign	Data_o	=	inDataReg;
 	assign	Addr_o	=	addrReg;
 	assign	Val_o	=	valReg;
+	assign	Be_o	=	beReg;
 	
 	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
 	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
@@ -74,6 +77,7 @@ always	@(posedge	Clk_i)	begin
 				addrReg	<=	{SmcA_i,1'b0};
 				inDataReg	<=	SmcD_i;
 				valReg	<=	1'b1;
+				beReg	<=	SmcBe_i;
 			end	else	begin
 				valReg	<=	0;
 			end
@@ -91,6 +95,7 @@ always	@(posedge	Clk_i)	begin
 		outDataReg	<=	0;
 		addrReg	<=	0;
 		valReg		<=	0;
+		beReg	<=	2'b0;
 	end
 end
 

sources_1/new/Mux/DataMuxer.v

@@ -1,5 +1,5 @@
 
-module SmcDataMux 
+module DataMuxer 
 #(
     parameter	CmdRegWidth	=	16,
     parameter	AddrRegWidth=	12,

sources_1/new/S5443_3Top.v

@@ -197,6 +197,7 @@ wire [SpiNum-1:0] Assel;
 wire	[SpiNum-1:0]	spiClkBus;
 wire	[SpiNum-1:0]	spiSyncRst;
 
+wire	[1:0]	smcBe;
 wire	[AddrRegWidth-1:0]	smcAddr;
 wire	[CmdRegWidth/2-1:0]	smcData;
 wire	smcVal;
@@ -528,12 +529,13 @@ SmcRx	SmcRx
 	
 	.AnsData_i	(muxedData),
 	
+	.Be_o		(smcBe),
 	.Data_o		(smcData),
 	.Addr_o		(smcAddr),
 	.Val_o		(smcVal)
 );
 
-SmcDataMux SmcDataMuxer
+DataMuxer DataMuxer
 (
     .Clk_i	(gclk),
     .Rst_i	(initRst),
@@ -563,7 +565,7 @@ RegMap_inst
     .Data_i(toRegMapData),
     .Addr_i(toRegMapAddr),
     .Val_i(toRegMapVal),
-    .SmcBe_i(SmcBe_i),
+    .SmcBe_i(smcBe),
     .Led_o(Led_o),
     .AnsDataReg_o(ansData),
     //Spi0

sources_1/new/SRAM/RegMap.v

@@ -161,6 +161,7 @@ reg [CmdRegWidth/2-1:0] GPIOARegS;
 (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg;
 (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] LedReg;
 
+reg	[1:0]	beReg;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
@@ -309,7 +310,13 @@ localparam GPIOCtrlAddrS = 12'hFF2;
 localparam Debug0Addr = 12'hFF8;
 localparam Debug1Addr = 12'hFFC;
 //================================================================================
-
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		beReg	<=	2'b0;
+	end	else	begin
+		beReg	<=	SmcBe_i;
+	end
+end
 
 
 always @(posedge Clk_i) begin 
@@ -377,7 +384,7 @@ always @(posedge Clk_i) begin
     end
     else begin 
         if (Val_i) begin 
-            case (SmcBe_i)  
+            case (beReg)  
                 0 : begin 
                     case (Addr_i) 
                         Spi0CtrlAddr : begin 
@@ -940,7 +947,7 @@ always @(*) begin
         ansReg = 0;
     end	else begin
 		if	(Val_i)	begin
-			case(SmcBe_i) 
+			case(beReg) 
 				0 : begin 
 					case (Addr_i)
 						Spi0CtrlAddr : begin