Исправления ошибок в адресации.

sources_1/new/Mux/DataMuxer.v

@@ -15,20 +15,20 @@ module SmcDataMux
 	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
 	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
 	
-	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
-	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
-	parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
-	parameter	Fifo1WriteMsbAddr	=	12'h50+12'h26,
-	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'h24,
-	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'h26,
-	parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
-	parameter	Fifo3WriteMsbAddr	=	12'h140+12'h26,
-	parameter	Fifo4WriteLsbAddr	=	12'h190+12'h24,
-	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
-	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
-	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h26,
-	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h24,
-	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
+	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
+	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
+	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
+	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
+	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
+	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
+	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
+	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
+	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
+	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
+	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
+	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
+	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
+	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26
 )
 (
     input	Clk_i,
@@ -77,7 +77,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 		ToRegMapAddr_o	<=	12'h0;
 		
 		ToFifoVal_o		<=	7'h0;
-		ToFifoData_o	<=	16'h0;
+		ToFifoData_o	<=	0;
 	end	else	begin
 		if	(requestToFifo)	begin	
 			case(SmcAddr_i)	
@@ -89,6 +89,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[0]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo1WriteLsbAddr:	begin
 									ToFifoVal_o[1]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
@@ -97,12 +98,17 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[1]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo2WriteLsbAddr:	begin
 									ToFifoVal_o[2]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
 								end
 				Fifo2WriteMsbAddr:	begin
 									ToFifoVal_o[2]	<=	SmcVal_i;
+									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+								end
+								
+				Fifo3WriteLsbAddr:	begin
 									ToFifoVal_o[3]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
 								end
@@ -110,6 +116,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[3]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo4WriteLsbAddr:	begin
 									ToFifoVal_o[4]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
@@ -118,12 +125,17 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[4]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo5WriteLsbAddr:	begin
 									ToFifoVal_o[5]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
 								end
 				Fifo5WriteMsbAddr:	begin
 									ToFifoVal_o[5]	<=	SmcVal_i;
+									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+								end
+								
+				Fifo6WriteLsbAddr:	begin
 									ToFifoVal_o[6]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
 								end