Top and xdc changes are made

SRAM/QuadSPIm.v

@@ -1,19 +1,24 @@
 module QuadSPIm(
     input Clk_i,
     input Rst_i,
-    input [27:0] Data_i,
     input Start_i,
+    input CPHA_i,
+    input [31:0] SPIdata,
+    input SELST_i,
+    input [1:0] WidthSel_i,
+    input [1:0] LAG_i,
+    input [1:0] LEAD_i,
+    input EndianSel_i,
+    input [1:0] Stop_i,
+    input PulsePol_i,
 
 
-
-
-
-
-    output Mosi0_i,
-    output Mosi1_i,
-    output Mosi2_i,
-    output Mosi3_i,
-    output Sck_o,
+    output reg Mosi0_i,
+    output reg Mosi1_i,
+    output reg Mosi2_i,
+    output reg Mosi3_i,
+    output reg  Sck_o,
+    output reg Val_o,
     output Ss_o
 
 );
@@ -28,21 +33,203 @@ reg [6:0] mosiReg0;
 reg [6:0] mosiReg1;
 reg [6:0] mosiReg2;
 reg [6:0] mosiReg3;
+reg [3:0] ssNum;
+reg [2:0] delayCnt;
+reg stopFlag;
+
+wire SsPol = SELST_i ? Ss : ~Ss;
 
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-assign Mosi0_i = (!Ss) ? (mosiReg3[6]):1'b0;
-assign Mosi1_i = (!Ss) ? (mosiReg2[6]):1'b0;
-assign Mosi2_i = (!Ss) ? (mosiReg1[6]):1'b0;
-assign Mosi3_i = (!Ss) ? (mosiReg0[6]):1'b0;
-assign Ss_o    = Ss; 
-assign Sck_i   = (!Ss) ? (~Clk_i) : 1'b0;
+
+assign Ss_o = SsPol; 
 
 //================================================================================
 //  CODING
 //================================================================================	
 
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        delayCnt <= 1'b0;
+    end
+    else begin 
+        if (stopFlag &&delayCnt < Stop_i) begin 
+            delayCnt <= delayCnt + 1'b1;
+        end
+        else begin 
+            delayCnt <= 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        stopFlag <= 1'b0;
+    end
+    else begin
+        if (SELST_i) begin 
+            if (Ss && !SSr) begin 
+                stopFlag <= 1'b1;
+            end
+            else if ( delayCnt == Stop_i) begin 
+                stopFlag <= 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss && SSr) begin 
+                stopFlag <= 1'b1;
+            end
+            else if (delayCnt == Stop_i) begin 
+                stopFlag <= 1'b0;
+            end
+        end
+    end
+end
+
+
+
+always @(*) begin 
+    if (PulsePol_i) begin 
+        if (CPHA_i) begin
+            if (LEAD_i == 0) begin 
+            if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                Sck_o = ~(~Clk_i);
+            end
+            else begin 
+                Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+        else begin
+            if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+    end
+    else begin 
+        if (CPHA_i) begin
+            if (LEAD_i == 0) begin  
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end 
+        else begin
+            if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+    end
+end
+
+
+always @(*) begin
+    if (EndianSel_i) begin 
+        case (WidthSel_i) 
+            0 : begin 
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg3[1]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[1]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[1]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[1]):1'b0;
+            end
+            1 : begin 
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[3]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[3]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[3]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[3]):1'b0;
+            end
+            2 : begin 
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[5]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[5]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[5]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[5]):1'b0;
+            end
+            3 : begin 
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[7]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[7]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[7]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[7]):1'b0;
+            end
+        endcase
+    end
+    else begin 
+        case (WidthSel_i)
+            0 : begin
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+            end
+            1 : begin
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+            end
+            2 : begin
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+            end
+            3 : begin
+                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+            end
+        endcase
+    end
+end
+
+
 always @(posedge Clk_i) begin
     if (Rst_i) begin
         SSr <=1'b0;
@@ -53,42 +240,87 @@ always @(posedge Clk_i) begin
 end
 
 
+always @(*) begin
+    if (SELST_i) begin 
+        if (Ss && !SSr) begin 
+            Val_o = 1'b1;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    else begin 
+        if (!Ss&& SSr) begin 
+            Val_o = 1'b1;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+end
 
-always @(posedge Clk_i) begin 
+
+
+always @(*) begin 
     if (Rst_i) begin 
-        startFlag <= 1'b0;
+        startFlag = 1'b0;
     end
     else begin 
-        if (!Start_i) begin 
-            startFlag <= 1'b1;
+        if (Start_i&& !stopFlag) begin 
+            startFlag = 1'b1;
         end
         else begin 
-            startFlag <= 1'b0;
+            startFlag = 1'b0;
         end
     end
 end
 
+always @(*) begin 
+    if (Rst_i) begin 
+        ssNum = 1'b0;
+    end
+    else begin 
+        case (WidthSel_i) 
+            0 : begin 
+                ssNum = 2;
+            end
+            1 : begin 
+                ssNum = 4;
+            end
+            2 : begin 
+                ssNum = 6;
+            end
+            3 : begin 
+                ssNum = 8;
+            end
+        endcase
+    end
+end
+
 
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         ssCnt <= 1'b0;
     end
-    else if (ssCnt < 7 && startFlag  ) begin 
+    else if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag  ) begin 
         ssCnt <= ssCnt + 1'b1;
     end
     else begin
-        if (ssCnt == 6 || !startFlag) begin 
+        if (ssCnt == ssNum-1 || !startFlag) begin 
             ssCnt <= 1'b0;
         end
     end
 end
 
+
+
+
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         Ss <= 1'b1;
     end
     else begin 
-        if (ssCnt < 7 && startFlag ) begin 
+        if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
             Ss <= 1'b0;
         end
         else begin 
@@ -97,58 +329,59 @@ always @(negedge Clk_i) begin
     end
 end
 
+
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
-        mosiReg0 <= Data_i[27:21];
+        mosiReg0 <= SPIdata[31:24];
     end
     else begin 
-        if (!SSr) begin
-            mosiReg0 <= { mosiReg0[5:0],1'b0 };
+        if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            mosiReg0 <= { mosiReg0[6:0],1'b0 };
         end
         else begin 
-            mosiReg0 <= Data_i[27:21];
+            mosiReg0 <= SPIdata[31:24];
         end
     end
 end
 
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
-        mosiReg1 <= Data_i[20:14];
+        mosiReg1 <= SPIdata[23:16];
     end
     else begin 
-        if (!SSr) begin
-            mosiReg1 <= { mosiReg1[5:0],1'b0 };
+        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            mosiReg1 <= { mosiReg1[6:0],1'b0 };
         end
         else begin 
-            mosiReg1 <= Data_i[20:14];
+            mosiReg1 <= SPIdata[23:16];
         end
     end
 end
 
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
-        mosiReg2 <= Data_i[13:7];
+        mosiReg2 <= SPIdata[15:8];
     end
     else begin 
-        if (!SSr) begin
-            mosiReg2 <= { mosiReg2[5:0],1'b0 };
+        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            mosiReg2 <= { mosiReg2[6:0],1'b0 };
         end
         else begin 
-            mosiReg2 <= Data_i[13:7];
+            mosiReg2 <= SPIdata[15:8];
         end
     end
 end
 
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
-        mosiReg3<= Data_i[6:0];
+        mosiReg3 <= SPIdata[7:0];
     end
     else begin 
-        if (!SSr) begin
-            mosiReg3 <= { mosiReg3[5:0],1'b0 };
+        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            mosiReg3 <= { mosiReg3[6:0],1'b0 };
         end
         else begin 
-            mosiReg3<= Data_i[6:0];
+            mosiReg3 <= SPIdata[7:0];
         end
     end
 end
@@ -162,4 +395,7 @@ end
 
 
 
+
+
+
 endmodule

constrs_1/new/S5443_3.xdc

@@ -79,8 +79,125 @@ set_property PACKAGE_PIN L14 [get_ports {BE_i[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {BE_i[0]}]
 
 
-
-
+#==========================================================================
+#	SPI INTERFACES
+
+#SPI0
+set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
+set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
+set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
+set_property PACKAGE_PIN J3 [get_ports {Mosi1_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[0]}]
+set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
+set_property PACKAGE_PIN L1  [get_ports {Mosi3_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
+set_property PACKAGE_PIN J2 [get_ports {SpiRs_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[0]}]
+
+#SPI1
+set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
+set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
+set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
+set_property PACKAGE_PIN R2 [get_ports {Mosi1_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[1]}]
+set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
+set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
+set_property PACKAGE_PIN P2 [get_ports {SpiRst_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[1]}]
+
+
+#SPI2
+set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
+set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
+set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
+set_property PACKAGE_PIN D2 [get_ports {Mosi1_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[2]}]
+set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
+set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
+set_property PACKAGE_PIN E3 [get_ports {SpiRst_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[2]}]
+
+#SPI3
+set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
+set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
+set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
+set_property PACKAGE_PIN R8 [get_ports {Mosi1_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[3]}]
+set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
+set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
+set_property PACKAGE_PIN R9 [get_ports {SpiRst_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[3]}]
+
+
+
+#SPI4
+set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
+set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
+set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
+set_property PACKAGE_PIN P12 [get_ports {Mosi1_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi_o[4]}]
+set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
+set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
+set_property PACKAGE_PIN N15 [get_ports {SpiRst_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[4]}]
+
+
+#SPI5
+set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
+set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
+set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
+set_property PACKAGE_PIN R3 [get_ports {Mosi1_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[5]}]
+set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
+set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
+set_property PACKAGE_PIN N6 [get_ports {SpiRst_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[5]}]
+
+
+#SPI6
+set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
+set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
+set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
+set_property PACKAGE_PIN C4 [get_ports {Mosi1_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[6]}]
+set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
+set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
+set_property PACKAGE_PIN A2 [get_ports {SpiRst_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[6]}]
 
 #==========================================================================
 #	INPUT CLOCKS
@@ -110,66 +227,6 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]
 
 
 
-connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
-connect_debug_port u_ila_0/probe3 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
-
-
-
-connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
-connect_debug_port u_ila_0/probe2 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
-
 
-connect_debug_port u_ila_0/probe9 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_2_n_0}]]
 
-connect_debug_port u_ila_0/probe6 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_1_n_0}]]
 
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list Clk123_i_IBUF_BUFG]]
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
-set_property port_width 2 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {BE_i_IBUF[0]} {BE_i_IBUF[1]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
-set_property port_width 11 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {Addr_i_IBUF[0]} {Addr_i_IBUF[1]} {Addr_i_IBUF[2]} {Addr_i_IBUF[3]} {Addr_i_IBUF[4]} {Addr_i_IBUF[5]} {Addr_i_IBUF[6]} {Addr_i_IBUF[7]} {Addr_i_IBUF[8]} {Addr_i_IBUF[9]} {Addr_i_IBUF[10]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
-set_property port_width 16 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {Data_i_IBUF[0]} {Data_i_IBUF[1]} {Data_i_IBUF[2]} {Data_i_IBUF[3]} {Data_i_IBUF[4]} {Data_i_IBUF[5]} {Data_i_IBUF[6]} {Data_i_IBUF[7]} {Data_i_IBUF[8]} {Data_i_IBUF[9]} {Data_i_IBUF[10]} {Data_i_IBUF[11]} {Data_i_IBUF[12]} {Data_i_IBUF[13]} {Data_i_IBUF[14]} {Data_i_IBUF[15]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
-set_property port_width 16 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {Data_i_OBUF[0]} {Data_i_OBUF[1]} {Data_i_OBUF[2]} {Data_i_OBUF[3]} {Data_i_OBUF[4]} {Data_i_OBUF[5]} {Data_i_OBUF[6]} {Data_i_OBUF[7]} {Data_i_OBUF[8]} {Data_i_OBUF[9]} {Data_i_OBUF[10]} {Data_i_OBUF[11]} {Data_i_OBUF[12]} {Data_i_OBUF[13]} {Data_i_OBUF[14]} {Data_i_OBUF[15]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
-set_property port_width 16 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
-set_property port_width 16 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list readEn_i_IBUF]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-set_property port_width 1 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list writeEn_i_IBUF]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {RegMap_inst/LedReg[31]_i_1_n_0}]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets Clk123_i_IBUF_BUFG]

sources_1/new/S5443_3Top.v

@@ -0,0 +1,174 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 10/30/2023 11:24:31 AM
+// Design Name: 
+// Module Name: S5443_3Top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module S5443_3Top #(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12,
+    parameter SpiNum = 7
+
+)(
+    input Clk123_i,
+    input [AddrRegWidth-2:0] Addr_i,
+    inout [CmdRegWidth/2-1:0] Data_i,
+    input [SpiNum-1:0] SpiRst_i,
+    input writeEn_i,
+    input readEn_i,
+    // input DspRst_i,
+    input [1:0] BE_i,
+    input outputEn_i,
+
+    output  Led_o,
+   
+    output  [SpiNum-1:0] Mosi0_o,
+    output  [SpiNum-1:0] Mosi1_o,
+    output  [SpiNum-1:0] Mosi2_o,
+    output  [SpiNum-1:0] Mosi3_o,
+    output  [SpiNum-1:0] Ss_o,
+    output  [SpiNum-1:0] Sck_o
+
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+wire Clk100_i;
+wire [SpiNum-1:0]Sck;
+wire [SpiNum-1:0] Ss; 
+wire [SpiNum-1:0]Mosi0;
+wire [SpiNum-1:0]Mosi1;
+wire [SpiNum-1:0]Mosi2;
+wire [SpiNum-1:0]Mosi3;
+wire [SpiNum-1:0] ten;
+wire clk80;
+wire clk61;
+wire Rst_i;
+wire gclk;
+wire [15:0] baudRate;
+wire [19:0] baudRateexp;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign addr = {Addr_i, 1'b0};
+assign Data_i = (!outputEn_i) ? data : 16'bz;
+assign ten = 8'b00000001;
+assign Mosi0_o = Mosi0;
+assign Mosi1_o = Mosi1;
+assign Mosi2_o = Mosi2;
+assign Mosi3_o = Mosi3;
+assign Ss_o = Ss;
+assign Sck_o = Sck;
+assign baudRate = 16'h4;
+assign baudRateexp = baudRate*13+1;
+//================================================================================
+//  CODING
+//================================================================================	
+
+BUFG BUFG_inst (
+   .O(gclk), // 1-bit output: Clock output
+   .I(Clk123_i)  // 1-bit input: Clock input
+);
+
+
+  clk_wiz_0 ClkGen
+   (
+   .s_axi_aclk      (),        // input s_axi_aclk                        
+   .s_axi_aresetn   (),     // input s_axi_aresetn,                                                          
+   .s_axi_awaddr    (),      // input [10 : 0] s_axi_awaddr,                              
+   .s_axi_awvalid   (),     // input s_axi_awvalid,                                                          
+   .s_axi_awready   (),     // output s_axi_awready,                                                         
+   .s_axi_wdata     (),       // input [31 : 0] s_axi_wdata,                             
+   .s_axi_wstrb     (),       // input [3 : 0] s_axi_wstrb,                         
+   .s_axi_wvalid    (),      // input s_axi_wvalid,                                                         
+   .s_axi_wready    (),      // output s_axi_wready,                                                        
+   .s_axi_bresp     (),       // output [1 : 0] s_axi_bresp,                                               
+   .s_axi_bvalid    (),      // output s_axi_bvalid,                                                        
+   .s_axi_bready    (),      // input s_axi_bready,                                                         
+   .s_axi_araddr    (),      // input [10 : 0] s_axi_araddr,                              
+   .s_axi_arvalid   (),     // input s_axi_arvalid,                                                          
+   .s_axi_arready   (),     // output s_axi_arready,                                                         
+   .s_axi_rdata     (),       // output [31 : 0] s_axi_rdata,                            
+   .s_axi_rresp     (),       // output [1 : 0] s_axi_rresp,                                               
+   .s_axi_rvalid    (),      // output s_axi_rvalid,                                                        
+   .s_axi_rready    (),      // input s_axi_rready,                                                         
+    // Clock out ports
+    .clk_out1(Clk100_i),     // output clk_out1
+    // Status and control signals
+    .locked(),       // output locked
+   // Clock in ports
+    .clk_in1(gclk));      // input clk_in1
+
+
+RegMap #(
+    .CmdRegWidth(32),
+    .AddrRegWidth(12)
+)
+RegMap_inst (
+    .Clk_i(gclk),
+    .Rst_i(Rst_i),
+    .Data_i(Data_i),
+    .Addr_i(addr),
+    .wrEn_i(writeEn_i),
+    .rdEn_i(readEn_i),
+    .BE_i(BE_i),
+    .Led_o(Led_o),
+    .AnsDataReg_o(data)
+
+);
+
+
+
+
+genvar i;
+
+generate
+    for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
+        QuadSPIm QuadSPIm_inst (
+            .Clk_i(Clk100_i),
+            .Start_i(ten[i]),
+            .Rst_i(Rst_i|SpiRst_i[i]),
+            .SPIdata(32'h2aaa00aa),
+            .Sck_o(Sck[i]),
+            .Ss_o(Ss[i]),
+            .Mosi0_i(Mosi0[i]),
+            .Mosi1_i(Mosi1[i]),
+            .Mosi2_i(Mosi2[i]),
+            .Mosi3_i(Mosi3[i]),
+            .WidthSel_i(3),
+            .PulsePol_i(0),
+            .EndianSel_i(1),
+            .LAG_i(0),
+            .LEAD_i(0),
+            .SELST_i(1)
+        );
+    end
+endgenerate
+
+
+InitRst InitRst_inst (
+    .clk_i(gclk),
+    .signal_o(Rst_i)
+
+);
+
+
+endmodule