Отлажено вычитывание.

sources_1/new/DataFifo/DataOutMux.v

@@ -6,6 +6,7 @@ module DataOutMux#(
 
 ) (
     input Rst_i,
+    input FifoRxRst_i,
     input Clk_i,
     input SmcAre_i,
     input [AddrRegWidth-1:0] Addr_i,
@@ -29,6 +30,7 @@ wire [0:31] dataFromRxFifo [6:0];
 wire [15:0] dataFromRegMap;
 
 reg [15:0] dataFromRxFifoR;
+reg [1:0] readEnCnt;
 
 (* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1;
 reg [CmdRegWidth-1:0] dataFromRxFifoR2;
@@ -52,6 +54,20 @@ assign dataFromRegMap = DataFromRegMap_i;
 assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
 
 
+always @(posedge Clk_i) begin 
+    if (FifoRxRst_i) begin 
+        readEnCnt <= 1'b0;
+    end
+    else begin 
+        if (!SmcAre_i) begin 
+            readEnCnt <= readEnCnt + 1'b1;
+        end
+        else begin 
+            readEnCnt <= 1'b0;
+        end
+    end
+end
+
 
 
 always @(*) begin
@@ -65,7 +81,7 @@ always @(*) begin
         dataFromRxFifoR7 = 0;
     end
     else begin
-        if (!SmcAre_i) begin  
+        if (!SmcAre_i && readEnCnt < 1 ) begin  
             case(Addr_i) 
                 12'h1c : begin
                     dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];

sources_1/new/DataFifo/FifoCtrl.v

@@ -58,6 +58,8 @@ reg FifoRxReadEn;
 (* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
 (* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;
 
+reg [1:0] readEnCnt;    
+
 
 
 wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
@@ -87,6 +89,21 @@ assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
 // //================================================================================
 
 
+always @(posedge FifoRxRdClock_i) begin 
+    if (FifoRxRst_i) begin 
+        readEnCnt <= 1'b0;
+    end
+    else begin 
+        if (ToFifoRxReadVal_i) begin 
+            readEnCnt <= readEnCnt + 1'b1;
+        end
+        else begin 
+            readEnCnt <= 1'b0;
+        end
+    end
+end
+
+
 
 always @(posedge FifoTxWrClock_i) begin 
     if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
@@ -119,7 +136,7 @@ end
 
 
 always @(posedge FifoRxRdClock_i) begin 
-    if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo) begin 
+    if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
         FifoRxReadEn <= 1'b1;
     end
     else begin 

sources_1/new/DspSmc/SmcRx.v

@@ -65,7 +65,7 @@ module	SmcRx
 	assign	Val_o	=	valReg;
 	assign	Be_o	=	beReg;
 	
-	assign	SmcD_i	=	(!SmcAre_i && !SmcAoe_i)?AnsData_i:16'bz;
+	// assign	SmcD_i	=	(!SmcAre_i && !SmcAoe_i)?AnsData_i:16'bz;
 //================================================================================
 //  CODING
 	

sources_1/new/S5443_3Top.v

@@ -250,6 +250,7 @@ wire [CmdRegWidth/2-1:0] muxedData;
 wire Clk100_o;
 wire Clk40_o;
 
+wire smcValComb; 
 
 
 
@@ -262,6 +263,8 @@ wire	[CmdRegWidth/2-1:0]	ansData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
+assign addr = {SmcAddr_i, 1'b0};
+assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
 assign ten = SpiTxRxEn[6:0];
 assign Mosi1_io[0] =(spiMode[0])?Mosi1[0]:1'bz;
 assign Mosi1_io[1] =(spiMode[1])?Mosi1[1]:1'bz;
@@ -537,7 +540,7 @@ assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 
 
 
-	// assign	SmcD_i	=	(!SmcAre_i)?muxedData:16'bz;
+	assign	SmcData_i	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
 
 //================================================================================
 //  CODING
@@ -548,8 +551,10 @@ assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 DataOutMux DataOutMuxer
 (
     // .Rst_i	(initRst),
-    .Addr_i  (smcAddr),
+    .Clk_i	(gclk),
+    .Addr_i  (addr),
     .ToRegMapAddr_i (toRegMapAddr),
+    .FifoRxRst_i(fifoRxRst[0]),
     .DataFromRegMap_i (ansData),
     .SmcAre_i (SmcAre_i),
     .DataFromRxFifo1_i (dataFromRxFifo[0]),
@@ -568,34 +573,34 @@ BUFG BUFG_inst (
    .I(Clk123_i)  // 1-bit input: Clock input
 );
 
-SmcRx	SmcRx
-(
-	.Clk_i		(gclk),
-	.Rst_i		(initRst),
-
-	.SmcD_i		(SmcData_i),
-	.SmcA_i		(SmcAddr_i),
-	.SmcAwe_i	(SmcAwe_i),
-	.SmcAmsN_i	(SmcAmsN_i),
-	.SmcAoe_i	(SmcAoe_i),
-	.SmcAre_i	(SmcAre_i),
-	.SmcBe_i	(SmcBe_i),
+// SmcRx	SmcRx
+// (
+// 	.Clk_i		(gclk),
+// 	.Rst_i		(initRst),
+
+// 	.SmcD_i		(SmcData_i),
+// 	.SmcA_i		(SmcAddr_i),
+// 	.SmcAwe_i	(SmcAwe_i),
+// 	.SmcAmsN_i	(SmcAmsN_i),
+// 	.SmcAoe_i	(SmcAoe_i),
+// 	.SmcAre_i	(SmcAre_i),
+// 	.SmcBe_i	(SmcBe_i),
 	
-	.AnsData_i	(muxedData),
+// 	.AnsData_i	(muxedData),
 	
-	.Data_o		(smcData),
-	.Addr_o		(smcAddr),
-	.Val_o		(smcVal)
-);
+// 	.Data_o		(smcData),
+// 	.Addr_o		(smcAddr),
+// 	.Val_o		(smcVal)
+// );
 
 DataMuxer DataMuxer
 (
     .Clk_i	(gclk),
     .Rst_i	(initRst),
 
-	.SmcVal_i	(smcVal),
-	.SmcData_i	(smcData),
-    .SmcAddr_i	(smcAddr),
+	.SmcVal_i	(smcValComb),
+	.SmcData_i	(SmcData_i),
+    .SmcAddr_i	(addr),
 
 	.ToRegMapVal_o	(toRegMapVal),
 	.ToRegMapData_o	(toRegMapData),
@@ -768,7 +773,7 @@ generate
             .FifoTxRst_i    (fifoTxRst[i]),
             .SmcAre_i   (SmcAre_i),
             .SmcAwe_i   (SmcAwe_i),
-            .SmcAddr_i  (smcAddr),
+            .SmcAddr_i  (addr),
             .TxFifoWrdCnt_i (wordCntTx[i]),
             .RxFifoWrdCnt_i (wordCntRx[i]),
 			.ToFifoVal_i	(toFifoVal[i]),

sources_1/new/SRAM/RegMap.v

@@ -111,20 +111,20 @@ reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi0TxFifoReg;
 reg [CmdRegWidth/2-1:0] Spi0RxFifoReg;
 
-(* dont_touch = "yes" *) reg [CmdRegWidth-1:0] TxFifoCtrlReg0Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg0Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg1Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg1Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg2Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg2Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg3Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg3Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg4Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg4Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg5Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg5Reg;
-reg [CmdRegWidth-1:0] TxFifoCtrlReg6Reg;
-reg [CmdRegWidth-1:0] RxFifoCtrlReg6Reg;
+// (* dont_touch = "yes" *) reg [CmdRegWidth-1:0] TxFifoCtrlReg0Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg0Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg1Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg1Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg2Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg2Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg3Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg3Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg4Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg4Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg5Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg5Reg;
+// reg [CmdRegWidth-1:0] TxFifoCtrlReg6Reg;
+// reg [CmdRegWidth-1:0] RxFifoCtrlReg6Reg;
 
 
 reg [CmdRegWidth/2-1:0] Spi1CtrlReg;
@@ -357,40 +357,40 @@ localparam Debug0Addr = 12'hFF8;
 localparam Debug1Addr = 12'hFFC;
 //================================================================================
 
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        TxFifoCtrlReg0Reg <= 0;
-        RxFifoCtrlReg0Reg <= 0;
-        TxFifoCtrlReg1Reg <= 0;
-        RxFifoCtrlReg1Reg <= 0;
-        TxFifoCtrlReg2Reg <= 0;
-        RxFifoCtrlReg2Reg <= 0;
-        TxFifoCtrlReg3Reg <= 0;
-        RxFifoCtrlReg3Reg <= 0;
-        TxFifoCtrlReg4Reg <= 0;
-        RxFifoCtrlReg4Reg <= 0;
-        TxFifoCtrlReg5Reg <= 0;
-        RxFifoCtrlReg5Reg <= 0;
-        TxFifoCtrlReg6Reg <= 0;
-        RxFifoCtrlReg6Reg <= 0;
-    end
-    else begin 
-        TxFifoCtrlReg0Reg <= TxFifoCtrlReg0_i;
-        RxFifoCtrlReg0Reg <= RxFifoCtrlReg0_i;
-        TxFifoCtrlReg1Reg <= TxFifoCtrlReg1_i;
-        RxFifoCtrlReg1Reg <= RxFifoCtrlReg1_i;
-        TxFifoCtrlReg2Reg <= TxFifoCtrlReg2_i;
-        RxFifoCtrlReg2Reg <= RxFifoCtrlReg2_i;
-        TxFifoCtrlReg3Reg <= TxFifoCtrlReg3_i;
-        RxFifoCtrlReg3Reg <= RxFifoCtrlReg3_i;
-        TxFifoCtrlReg4Reg <= TxFifoCtrlReg4_i;
-        RxFifoCtrlReg4Reg <= RxFifoCtrlReg4_i;
-        TxFifoCtrlReg5Reg <= TxFifoCtrlReg5_i;
-        RxFifoCtrlReg5Reg <= RxFifoCtrlReg5_i;
-        TxFifoCtrlReg6Reg <= TxFifoCtrlReg6_i;
-        RxFifoCtrlReg6Reg <= RxFifoCtrlReg6_i;
-    end
-end
+// always @(posedge Clk_i) begin 
+//     if (Rst_i) begin 
+//         TxFifoCtrlReg0Reg <= 0;
+//         RxFifoCtrlReg0Reg <= 0;
+//         TxFifoCtrlReg1Reg <= 0;
+//         RxFifoCtrlReg1Reg <= 0;
+//         TxFifoCtrlReg2Reg <= 0;
+//         RxFifoCtrlReg2Reg <= 0;
+//         TxFifoCtrlReg3Reg <= 0;
+//         RxFifoCtrlReg3Reg <= 0;
+//         TxFifoCtrlReg4Reg <= 0;
+//         RxFifoCtrlReg4Reg <= 0;
+//         TxFifoCtrlReg5Reg <= 0;
+//         RxFifoCtrlReg5Reg <= 0;
+//         TxFifoCtrlReg6Reg <= 0;
+//         RxFifoCtrlReg6Reg <= 0;
+//     end
+//     else begin 
+//         TxFifoCtrlReg0Reg <= TxFifoCtrlReg0_i;
+//         RxFifoCtrlReg0Reg <= RxFifoCtrlReg0_i;
+//         TxFifoCtrlReg1Reg <= TxFifoCtrlReg1_i;
+//         RxFifoCtrlReg1Reg <= RxFifoCtrlReg1_i;
+//         TxFifoCtrlReg2Reg <= TxFifoCtrlReg2_i;
+//         RxFifoCtrlReg2Reg <= RxFifoCtrlReg2_i;
+//         TxFifoCtrlReg3Reg <= TxFifoCtrlReg3_i;
+//         RxFifoCtrlReg3Reg <= RxFifoCtrlReg3_i;
+//         TxFifoCtrlReg4Reg <= TxFifoCtrlReg4_i;
+//         RxFifoCtrlReg4Reg <= RxFifoCtrlReg4_i;
+//         TxFifoCtrlReg5Reg <= TxFifoCtrlReg5_i;
+//         RxFifoCtrlReg5Reg <= RxFifoCtrlReg5_i;
+//         TxFifoCtrlReg6Reg <= TxFifoCtrlReg6_i;
+//         RxFifoCtrlReg6Reg <= RxFifoCtrlReg6_i;
+//     end
+// end
 
 
 
@@ -1048,16 +1048,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg;
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0Reg[15:0];
+							ansReg = TxFifoCtrlReg0_i[15:0];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0Reg[31:16];
+                            ansReg = TxFifoCtrlReg0_i[31:16];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0Reg[15:0];
+							ansReg = RxFifoCtrlReg0_i[15:0];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0Reg[31:16];
+                            ansReg = RxFifoCtrlReg0_i[31:16];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg;
@@ -1078,16 +1078,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg;
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1Reg[15:0];
+							ansReg = TxFifoCtrlReg1_i[15:0];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1Reg[31:16];
+                            ansReg = TxFifoCtrlReg1_i[31:16];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1Reg[15:0];
+							ansReg = RxFifoCtrlReg1_i[15:0];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1Reg[31:16];
+                            ansReg = RxFifoCtrlReg1_i[31:16];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg;
@@ -1108,16 +1108,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg;
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2Reg[15:0];
+							ansReg = TxFifoCtrlReg2_i[15:0];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2Reg[31:16];
+                            ansReg = TxFifoCtrlReg2_i[31:16];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2Reg[15:0];
+							ansReg = RxFifoCtrlReg2_i[15:0];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2Reg[31:16];
+                            ansReg = RxFifoCtrlReg2_i[31:16];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg;
@@ -1138,16 +1138,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg;
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3Reg[15:0];
+							ansReg = TxFifoCtrlReg3_i[15:0];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3Reg[31:16];
+                            ansReg = TxFifoCtrlReg3_i[31:16];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3Reg[15:0];
+							ansReg = RxFifoCtrlReg3_i[15:0];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3Reg[31:16];
+                            ansReg = RxFifoCtrlReg3_i[31:16];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg;
@@ -1168,16 +1168,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg;
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4Reg[15:0];
+							ansReg = TxFifoCtrlReg4_i[15:0];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4Reg[31:16];
+                            ansReg = TxFifoCtrlReg4_i[31:16];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4Reg[15:0];
+							ansReg = RxFifoCtrlReg4_i[15:0];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4Reg[31:16];
+                            ansReg = RxFifoCtrlReg4_i[31:16];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg;
@@ -1198,16 +1198,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg;
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5Reg[15:0];
+							ansReg = TxFifoCtrlReg5_i[15:0];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5Reg[31:16];
+                            ansReg = TxFifoCtrlReg5_i[31:16];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5Reg[15:0];
+							ansReg = RxFifoCtrlReg5_i[15:0];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5Reg[31:16];
+                            ansReg = RxFifoCtrlReg5_i[31:16];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg;
@@ -1228,16 +1228,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg;
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6Reg[15:0];
+							ansReg = TxFifoCtrlReg6_i[15:0];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6Reg[31:16];
+                            ansReg = TxFifoCtrlReg6_i[31:16];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6Reg[15:0];
+							ansReg = RxFifoCtrlReg6_i[15:0];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6Reg[31:16];
+                            ansReg = RxFifoCtrlReg6_i[31:16];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg;
@@ -1274,16 +1274,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg[15:8];
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0Reg[15:8];
+							ansReg = TxFifoCtrlReg0_i[15:8];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0Reg[31:24];
+                            ansReg = TxFifoCtrlReg0_i[31:24];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0Reg[15:8];
+							ansReg = RxFifoCtrlReg0_i[15:8];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0Reg[31:24];
+                            ansReg = RxFifoCtrlReg0_i[31:24];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg[15:8];
@@ -1304,16 +1304,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg[15:8];
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1Reg[15:8];
+							ansReg = TxFifoCtrlReg1_i[15:8];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1Reg[31:24];
+                            ansReg = TxFifoCtrlReg1_i[31:24];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1Reg[15:8];
+							ansReg = RxFifoCtrlReg1_i[15:8];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1Reg[31:24];
+                            ansReg = RxFifoCtrlReg1_i[31:24];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg[15:8];
@@ -1334,16 +1334,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg[15:8];
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2Reg[15:8];
+							ansReg = TxFifoCtrlReg2_i[15:8];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2Reg[31:24];
+                            ansReg = TxFifoCtrlReg2_i[31:24];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2Reg[15:8];
+							ansReg = RxFifoCtrlReg2_i[15:8];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2Reg[31:24];
+                            ansReg = RxFifoCtrlReg2_i[31:24];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg[15:8];
@@ -1364,16 +1364,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg[15:8];
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3Reg[15:8];
+							ansReg = TxFifoCtrlReg3_i[15:8];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3Reg[31:24];
+                            ansReg = TxFifoCtrlReg3_i[31:24];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3Reg[15:8];
+							ansReg = RxFifoCtrlReg3_i[15:8];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3Reg[31:24];
+                            ansReg = RxFifoCtrlReg3_i[31:24];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg[15:8];
@@ -1394,16 +1394,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg[15:8];
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4Reg[15:8];
+							ansReg = TxFifoCtrlReg4_i[15:8];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4Reg[31:24];
+                            ansReg = TxFifoCtrlReg4_i[31:24];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4Reg[15:8];
+							ansReg = RxFifoCtrlReg4_i[15:8];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4Reg[31:24];
+                            ansReg = RxFifoCtrlReg4_i[31:24];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg[15:8];
@@ -1424,16 +1424,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg[15:8];
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5Reg[15:8];
+							ansReg = TxFifoCtrlReg5_i[15:8];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5Reg[31:24];
+                            ansReg = TxFifoCtrlReg5_i[31:24];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5Reg[15:8];
+							ansReg = RxFifoCtrlReg5_i[15:8];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5Reg[31:24];
+                            ansReg = RxFifoCtrlReg5_i[31:24];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg[15:8];
@@ -1454,16 +1454,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg[15:8];
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6Reg[15:8];
+							ansReg = TxFifoCtrlReg6_i[15:8];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6Reg[31:24];
+                            ansReg = TxFifoCtrlReg6_i[31:24];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6Reg[15:8];
+							ansReg = RxFifoCtrlReg6_i[15:8];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6Reg[31:24];
+                            ansReg = RxFifoCtrlReg6_i[31:24];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg[15:8];
@@ -1500,16 +1500,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg[7:0];
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0Reg[7:0];
+							ansReg = TxFifoCtrlReg0_i[7:0];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0Reg[23:16];
+                            ansReg = TxFifoCtrlReg0_i[23:16];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0Reg[7:0];
+							ansReg = RxFifoCtrlReg0_i[7:0];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0Reg[23:16];
+                            ansReg = RxFifoCtrlReg0_i[23:16];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg[7:0];
@@ -1530,16 +1530,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg[7:0];
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1Reg[7:0];
+							ansReg = TxFifoCtrlReg1_i[7:0];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1Reg[23:16];
+                            ansReg = TxFifoCtrlReg1_i[23:16];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1Reg[7:0];
+							ansReg = RxFifoCtrlReg1_i[7:0];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1Reg[23:16];
+                            ansReg = RxFifoCtrlReg1_i[23:16];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg[7:0];
@@ -1560,16 +1560,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg[7:0];
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2Reg[7:0];
+							ansReg = TxFifoCtrlReg2_i[7:0];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2Reg[23:16];
+                            ansReg = TxFifoCtrlReg2_i[23:16];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2Reg[7:0];
+							ansReg = RxFifoCtrlReg2_i[7:0];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2Reg[23:16];
+                            ansReg = RxFifoCtrlReg2_i[23:16];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg[7:0];
@@ -1590,16 +1590,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg[7:0];
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3Reg[7:0];
+							ansReg = TxFifoCtrlReg3_i[7:0];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3Reg[23:16];
+                            ansReg = TxFifoCtrlReg3_i[23:16];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3Reg[7:0];
+							ansReg = RxFifoCtrlReg3_i[7:0];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3Reg[23:16];
+                            ansReg = RxFifoCtrlReg3_i[23:16];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg[7:0];
@@ -1620,16 +1620,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg[7:0];
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4Reg[7:0];
+							ansReg = TxFifoCtrlReg4_i[7:0];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4Reg[23:16];
+                            ansReg = TxFifoCtrlReg4_i[23:16];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4Reg[7:0];
+							ansReg = RxFifoCtrlReg4_i[7:0];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4Reg[23:16];
+                            ansReg = RxFifoCtrlReg4_i[23:16];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg[7:0];
@@ -1650,16 +1650,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg[7:0];
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5Reg[7:0];
+							ansReg = TxFifoCtrlReg5_i[7:0];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5Reg[23:16];
+                            ansReg = TxFifoCtrlReg5_i[23:16];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5Reg[7:0];
+							ansReg = RxFifoCtrlReg5_i[7:0];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5Reg[23:16];
+                            ansReg = RxFifoCtrlReg5_i[23:16];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg[7:0];
@@ -1680,16 +1680,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg[7:0];
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6Reg[7:0];
+							ansReg = TxFifoCtrlReg6_i[7:0];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6Reg[23:16];
+                            ansReg = TxFifoCtrlReg6_i[23:16];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6Reg[7:0];
+							ansReg = RxFifoCtrlReg6_i[7:0];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6Reg[23:16];
+                            ansReg = RxFifoCtrlReg6_i[23:16];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg[7:0];