Исправлена разрядность входных данных DataMuxer, создан простой тестбенч

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -52,7 +52,7 @@ module DataFifoWrapper
 //================================================================================
 
 FifoCtrl FifoCtrl_inst (
-	.ToFifoTxWriteVal_i	(!SmcAwe_i && ToFifoVal_i),
+	.ToFifoTxWriteVal_i	(ToFifoVal_i),
 	.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
 	.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
 	.ToFifoRxReadVal_i	(!SmcAre_i),
@@ -60,6 +60,10 @@ FifoCtrl FifoCtrl_inst (
 	.FifoTxEmpty_i		(emptyFlagTx),
 	.FifoRxFull_i		(fullFlagRx),
 	.FifoRxEmpty_i		(emptyFlagRx),
+	.FifoTxWrClock_i	(WrClk_i),
+	.FifoTxRdClock_i	(RdClk_i),
+	.FifoRxWrClock_i	(RdClk_i),
+	.FifoRxRdClock_i	(WrClk_i),
 	.FifoTxWriteEn_o	(txFifoWrEn),
 	.FifoTxReadEn_o		(txFifoRdEn),
 	.FifoRxWriteEn_o	(rxFifoWrEn),

sources_1/new/DataFifo/FifoCtrl.v

@@ -10,6 +10,11 @@ module FifoCtrl (
     input FifoRxEmpty_i,
 
 
+    input FifoTxWrClock_i,
+    input FifoTxRdClock_i,
+    input FifoRxWrClock_i,
+    input FifoRxRdClock_i,
+
     output FifoTxWriteEn_o,
     output FifoTxReadEn_o,
     output FifoRxWriteEn_o,
@@ -39,39 +44,39 @@ assign FifoRxReadEn_o = FifoRxReadEn;
 
 
 
-always @(*) begin 
-    if (ToFifoTxWriteVal_i && ~FifoTxFull_i) begin 
-        FifoTxWriteEn = 1'b1;
+always @(posedge FifoTxWrClock_i) begin 
+    if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+        FifoTxWriteEn <= 1'b1;
     end
     else begin 
-        FifoTxWriteEn = 1'b0;
+        FifoTxWriteEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoTxReadVal_i && ~FifoTxEmpty_i) begin 
-        FifoTxReadEn = 1'b1;
+always @(posedge FifoTxRdClock_i ) begin 
+    if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+        FifoTxReadEn <= 1'b1;
     end
     else begin 
-        FifoTxReadEn = 1'b0;
+        FifoTxReadEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoRxWriteVal_i && ~FifoRxFull_i) begin 
-        FifoRxWriteEn = 1'b1;
+always @(posedge FifoRxWrClock_i) begin 
+    if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+        FifoRxWriteEn <= 1'b1;
     end
     else begin 
-        FifoRxWriteEn = 1'b0;
+        FifoRxWriteEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoRxReadVal_i && ~FifoRxEmpty_i) begin 
-        FifoRxReadEn = 1'b1;
+always @(posedge FifoRxRdClock_i) begin 
+    if (ToFifoRxReadVal_i && !FifoRxEmpty_i) begin 
+        FifoRxReadEn <= 1'b1;
     end
     else begin 
-        FifoRxReadEn = 1'b0;
+        FifoRxReadEn <= 1'b0;
     end
 end
 

sources_1/new/DspSmc/SmcRx.v

@@ -62,7 +62,7 @@ module	SmcRx
 	assign	Addr_o	=	addrReg;
 	assign	Val_o	=	valReg;
 	
-	assign	SmcD_i	=	(!SmcAre_i)?	outDataReg:16'bz;
+	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
 //================================================================================
 //  CODING
 	
@@ -82,6 +82,9 @@ always	@(posedge	Clk_i	or	negedge	Rst_i)	begin
 				outDataReg	<=	AnsData_i;
 			end	
 		end
+		else begin 
+			valReg	<=	0;
+		end
 	end	else	begin
 		inDataReg	<=	0;
 		outDataReg	<=	0;

sources_1/new/MMCM/Division.c

@@ -6,13 +6,11 @@ int main() {
     double quotient, fractional_part;
     int whole_part, count_0125;
 
-    // Запрос ввода чисел у пользователя
     printf("Введите делимое: ");
     scanf("%lf", &dividend);
     printf("Введите делитель: ");
     scanf("%lf", &divisor);
 
-    // Проверка деления на ноль
     if (divisor == 0) {
         printf("Ошибка: Деление на ноль!\n");
         return 1;

sources_1/new/Mux/DataMuxer.v

@@ -35,7 +35,7 @@ module SmcDataMux
     input	Rst_i,
 
 	input	SmcVal_i,
-	input	[CmdRegWidth/2-1:0]	SmcData_i,
+	input	[CmdRegWidth-1:0]	SmcData_i,
     input	[AddrRegWidth-1:0]	SmcAddr_i,
 
 	output	reg	ToRegMapVal_o,
@@ -147,6 +147,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 			ToRegMapAddr_o	<=	0;
 		end	else	begin
 			ToRegMapVal_o	<=	SmcVal_i;
+			ToFifoVal_o		<=	7'h0;
 			ToRegMapData_o	<=	SmcData_i;
 			ToRegMapAddr_o	<=	SmcAddr_i;
 		end

sources_1/new/S5443_3Top.v

@@ -25,7 +25,7 @@ module S5443_3Top
 #(
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
-    parameter SpiNum = 7
+    parameter SpiNum = 1
 
 )
 (
@@ -447,8 +447,6 @@ assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
 assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
 
 
-// assign SmcData_i = (!SmcAoe_i)?muxedData:16'bz;
-
 //================================================================================
 //  CODING
 //================================================================================	

sources_1/new/S5443_3_tb.v

@@ -0,0 +1,338 @@
+`timescale 1ns / 1ps
+module S5443_3_tb;
+
+parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+
+
+
+reg Clk_i;
+reg Rst_i;
+reg [10:0] SmcAddr_i;
+reg [15:0]SmcData_i;
+reg SmcAre_i;
+reg SmcAwe_i;
+wire SmcAmsN_i;
+wire [1:0] SmcBe_i;
+reg SmcAoe_i;
+
+reg [31:0] tb_cnt;
+
+wire [15:0] smcData;
+
+assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
+assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
+assign smcData = SmcData_i;
+
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+
+
+    S5443_3Top uut (
+        .Clk123_i(Clk_i), 
+        .SmcAddr_i(SmcAddr_i), 
+        .SmcData_i(smcData), 
+        .SmcAwe_i(SmcAwe_i), 
+        .SmcAmsN_i(SmcAmsN_i), 
+        .SmcAre_i(SmcAre_i), 
+        .SmcBe_i(SmcBe_i), 
+        .SmcAoe_i(SmcAoe_i), 
+        .Ld_i(Ld_i), 
+        .Led_o(), 
+        .Mosi0_o(), 
+        .Mosi1_o(), 
+        .Mosi2_o(), 
+        .Mosi3_o(), 
+        .Ss_o(), 
+        .SsFlash_o(), 
+        .Sck_o(), 
+        .SpiRst_o(), 
+        .LD_o()
+    );
+
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin
+        SmcAwe_i <= 1'b1;
+    end
+    else begin 
+        case (tb_cnt)
+        0: begin 
+            SmcAwe_i <= 1'b1;
+        end 
+        1: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        2: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        3: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        4: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        5: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        6: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        7: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        8: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        9: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        10: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        11: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        12: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        13: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        14: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        15: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        16: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        17: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        18: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        19: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        20: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        21: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        22: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        23: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        24: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        25: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        26: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        27: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        28: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        29: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        30: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        31: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        32: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        33: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        34: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        35: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        36: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        37: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        38: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        39: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        40: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        41: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        42: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        43: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        44: begin 
+            SmcAwe_i <= 1'b1;
+        end
+    endcase
+    end
+end
+
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        SmcAddr_i <= 0;
+        SmcData_i <= 0;
+    end
+    else begin
+        case (tb_cnt)
+        0: begin 
+            SmcAddr_i <= 12'h00f;
+            SmcData_i <= 16'h0000;
+        end
+        2: begin 
+            SmcAddr_i <= 12'h7fc;
+            SmcData_i <= 16'h0001;
+        end
+        4: begin 
+            SmcAddr_i <= 12'h7fd;
+            SmcData_i <= 16'h0000;
+        end
+        6: begin 
+            SmcAddr_i <= 12'h7fe;
+        end
+        8: begin 
+            SmcAddr_i <= 12'h0;
+            SmcData_i <= 16'he7;
+        end
+        10: begin 
+            SmcAddr_i <= 12'h1;
+        end
+        12: begin 
+             SmcAddr_i <= 12'h2;
+        end
+        14: begin 
+            SmcAddr_i <= 12'h3;
+        end
+        16: begin 
+            SmcAddr_i <= 12'h4;
+            SmcData_i <= 16'hc;
+        end
+        18: begin 
+            SmcAddr_i <= 12'h5;
+        end
+        20: begin 
+             SmcAddr_i <= 12'h6;
+        end
+        22:  begin 
+            SmcAddr_i <= 12'h7;
+        end
+        24: begin
+             SmcAddr_i <= 12'h8;
+             SmcData_i <= 16'h0;
+        end
+        26: begin 
+            SmcAddr_i <= 12'h9;
+        end
+        28: begin 
+             SmcAddr_i <= 12'ha;
+        end
+        30: begin 
+             SmcAddr_i <= 12'hb;
+        end
+        32: begin 
+             SmcAddr_i <= 12'h780;
+             SmcData_i <= 16'h1;
+        end
+        34: begin
+             SmcAddr_i <= 12'h781;
+             SmcData_i <= 16'h0;
+        end
+        36: begin
+             SmcAddr_i <= 12'h7f8;
+             SmcData_i <= 16'h0;
+        end
+        38: begin 
+             SmcAddr_i <= 12'h7f9;
+             SmcData_i <= 16'h0;
+        end
+        40: begin 
+            SmcAddr_i <= 12'h00c;
+            SmcData_i <= 16'h1;
+        end
+        42: begin 
+            SmcAddr_i <= 12'h00d;
+            SmcData_i <= 16'h0;
+        end
+    endcase
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        tb_cnt <= 0;
+    end
+    else begin 
+        tb_cnt <= tb_cnt + 1;
+    end
+end
+
+
+// always @(*) begin 
+//     txNextState = IDLE;
+//     case(txCurrState)
+//     IDLE : begin 
+//             if (txWork) begin 
+//                 txNextState = CMD;
+//             end
+//             else begin 
+//                 txNextState = IDLE;
+//             end
+//         end
+//     WRITE : begin 
+//             if () begin 
+//                 txNextState = WRITE;
+//             end
+//             else begin 
+//                 txNextState = IDLE;
+//             end
+//         end
+
+
+initial begin 
+    Clk_i = 1'b0;
+    Rst_i = 1'b1;
+    SmcAre_i = 1'b1;
+    SmcAoe_i = 1'b1;
+    #(CLK_PERIOD*10) Rst_i = 1'b0;
+
+
+
+
+end
+
+endmodule
+