MMCM Reconfig

AdcInit/AdcInitInterface.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:56:45 07/11/2019 
+// design name: 
+// module name:    adc_init_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcInitInterface	
+#(
+	parameter	DelayValue		=	24000,
+	parameter	LengthWidth		=	2000,
+	parameter	DataWidth		=	24,
+	parameter	DataNum			=	26
+)
+(
+    input	wire	Clk_i,
+	input	wire	Rst_i,
+	
+	output	wire	AdcMosi_o,
+	output	wire	AdcClk_o,
+	output	wire	AdcCs_o,
+	output	wire	AdcRst_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire			adcRstDone;
+	wire			adcFilteredRst;
+//================================================================================
+//  instantiations
+//================================================================================	
+
+ResetFilter #(
+    .STAGE_NUM      (4),
+    .RESET_FRONT    ("RISING")
+) 
+adcResetFilter 
+(
+    .clk_i          (Clk_i),
+    .rst_i          (Rst_i),
+    .perm_i         (1'b0),
+    .filtered_rst_o (adcFilteredRst)
+);
+
+AdcInitRst
+#(
+	.DELAY_VALUE    (DelayValue),	//задержка перед выдачей reset'а
+	.LENGTH_WIDTH   (LengthWidth)		//длительность сигнала reset
+) 
+AdcInitRst 
+(
+	.clk_i      (Clk_i),
+	.rst_i      (adcFilteredRst),
+	.signal_o   (AdcRst_o),
+	.done_o     (adcRstDone)
+);
+
+PeriphSpiInit 
+#(
+	.DATA_WIDTH             (DataWidth),
+	.DATA_NUM               (DataNum), 
+	.ROM_INIT_FILE          ("C:/Users/User/Desktop/4portCompact/S5443/S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt"),
+	.FILE_DATA_BASE         ("HEX"),
+	.SPI_CLK_DIVISOR_POWER  (4),
+	.SPI_CPOL               (0),
+	.SPI_CPHA               (0),
+	.SPI_DATA_DIRECTION     ("MSB"),
+	.SPI_EN_START_DELAY     ("YES")
+) 
+PeriphSpiInitController 
+(
+	.clk_i                  (Clk_i),
+	.rst_i                  (adcFilteredRst),
+	.enable_i               (adcRstDone),
+	.mosi_o                 (AdcMosi_o),
+	.sck_o                  (AdcClk_o),
+	.ss_o                   (AdcCs_o),
+	.done_o                 ()
+);
+
+endmodule

AdcInit/AdcInitRst.v

@@ -0,0 +1,130 @@
+module AdcInitRst (
+    clk_i,
+    rst_i,
+
+    signal_o,
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 24000;
+    parameter   LENGTH_WIDTH    = 2;
+
+    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    output  reg     signal_o;
+    output  reg     done_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [1:0]   SM_RST_S    = 2'b00;
+    localparam  [1:0]   SM_DELAY_S  = 2'b01;
+    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
+    localparam  [1:0]   SM_DONE_S   = 2'b11;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               curr_state;
+    reg     [1:0]               next_state;
+
+    reg     [DELAY_CNT_W-1:0]   delay_cnt;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
+    reg                         signal_next;
+    reg                         done_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        curr_state  <= SM_RST_S;
+        delay_cnt   <= {DELAY_CNT_W{1'b0}};
+        signal_o    <= 1'b0;
+        done_o      <= 1'b0;
+    end else begin
+        curr_state  <= next_state;
+        delay_cnt   <= delay_cnt_next;
+        signal_o    <= signal_next;
+        done_o      <= done_next;
+    end
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+    signal_next     = 1'b0;
+    done_next       = 1'b0;
+    case(curr_state)
+        SM_RST_S    : begin
+            next_state  = SM_DELAY_S;
+        end
+
+        SM_DELAY_S  : begin
+            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+            end else begin
+                next_state      = SM_DELAY_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_SIGNAL_S : begin
+            signal_next = 1'b1;
+            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_DONE_S   : begin
+            done_next   = 1'b1;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

AdcInit/PeriphSpiInit.v

@@ -0,0 +1,217 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :   16.05.2019
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   0.01 - File Created
+// Additional Comments      :
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module PeriphSpiInit (
+    clk_i,
+    rst_i,
+
+    enable_i,
+
+    mosi_o,
+    sck_o,
+    ss_o,
+
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DATA_WIDTH              = 24;
+    parameter   DATA_NUM                = 26; 
+    parameter   ROM_INIT_FILE           = "./initFiles/AdcInitData.txt";
+    parameter   FILE_DATA_BASE          = "HEX";
+    parameter   SPI_CLK_DIVISOR_POWER   = 4;
+    parameter   SPI_CPOL                = 0;
+    parameter   SPI_CPHA                = 0;
+    parameter   SPI_DATA_DIRECTION      = "MSB";   //  MSB or LSB
+    parameter   SPI_EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  ROM_ADDR_WIDTH          = bit_num(DATA_NUM);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [7:0]   SM_RST_S        = 8'd0;
+    localparam  [7:0]   SM_SEND_DATA_S  = 8'd2;
+    localparam  [7:0]   SM_READ_DATA_S  = 8'd3;
+    localparam  [7:0]   SM_WAIT_SPI_S   = 8'd4;
+    localparam  [7:0]   SM_DONE_S       = 8'd5;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input       clk_i;
+    input       rst_i;
+    input       enable_i;
+    output      mosi_o;
+    output      sck_o;
+    output      ss_o;
+    output      done_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr;
+    reg                             rom_valid;
+    wire    [DATA_WIDTH-1:0]        rom_data;
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr_next;
+    wire                            spi_ready;
+    reg     [7:0]                   sm_curr_state;
+    reg     [7:0]                   sm_next_state;
+    wire                            data_end_flag;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  data_end_flag   = (rom_addr == DATA_NUM);
+    assign  done_o          = sm_curr_state == SM_DONE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+SpiMaster #(
+    .CLK_DIVISOR_POWER  (SPI_CLK_DIVISOR_POWER),
+    .DATA_WIDTH         (DATA_WIDTH),
+    .CPOL               (SPI_CPOL),
+    .CPHA               (SPI_CPHA),
+    .DATA_DIRECTION     (SPI_DATA_DIRECTION),
+    .EN_START_DELAY     (SPI_EN_START_DELAY)
+) SpiMaster (
+    .clk_i      (clk_i),
+    .rst_i      (rst_i),
+
+    .data_i     (rom_data),
+    .valid_i    (rom_valid),
+    .ready_o    (spi_ready),
+    .mosi_o     (mosi_o),
+    .sck_o      (sck_o),
+    .ss_o       (ss_o)
+);
+
+SinglePortRom #(
+    .DATA_WIDTH     (DATA_WIDTH), 
+    .ADDR_WIDTH     (ROM_ADDR_WIDTH),
+    .INIT_FILE_NAME (ROM_INIT_FILE),
+    .DATA_BASE      (FILE_DATA_BASE)
+) Rom (
+    .clk_i  (clk_i),
+    .addr_i (rom_addr),
+    .q_o    (rom_data)
+    );
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        rom_addr        <= SM_RST_S;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        rom_addr        <= rom_addr_next;
+    end
+end
+
+always @(*) begin
+    sm_next_state   = 0;
+    rom_addr_next   = rom_addr;
+    rom_valid       = 1'b0;
+    case(sm_curr_state)
+        SM_RST_S        :   begin
+            if (enable_i) begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end else begin
+                sm_next_state   = SM_RST_S;
+            end
+        end
+
+        SM_SEND_DATA_S  :   begin
+            rom_valid       = 1'b1;
+            sm_next_state   = SM_SEND_DATA_S;
+            if (spi_ready) begin
+                rom_addr_next   = rom_addr + {{(ROM_ADDR_WIDTH-1){1'b0}}, 1'b1};
+                sm_next_state   = SM_READ_DATA_S;
+            end
+        end
+
+        SM_READ_DATA_S  :   begin
+            if (data_end_flag) begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end else begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end
+        end
+
+        SM_WAIT_SPI_S   : begin
+            if (spi_ready) begin
+                sm_next_state   = SM_DONE_S;
+            end else begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end
+        end
+
+        SM_DONE_S       :   begin
+            sm_next_state   = SM_DONE_S;
+        end
+
+    endcase
+end
+
+endmodule

AdcInit/Power2ClkDivider.v

@@ -0,0 +1,90 @@
+`timescale 1ns / 1ps
+module Power2ClkDivider (
+    clk_i,
+    rst_i,
+    valid_i,
+    signal_o,
+    rising_edge_o,
+    falling_edge_o
+);
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DIVISOR_POWER   = 2;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    input           valid_i;
+    output  reg     signal_o;
+    output  reg     rising_edge_o;
+    output  reg     falling_edge_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    wire    clk_div_flag;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//initial begin
+//    if (DIVISOR_POWER < 1) begin
+//        $error("parameter DIVISOR_POWER of module power2_clk_divider must be greater then 0");
+//        $stop;
+//    end
+//end
+
+generate
+    if (DIVISOR_POWER < 2) begin
+        assign  clk_div_flag    = 1'b1;
+    end else begin
+        reg     [DIVISOR_POWER-2:0] clk_div_cnt;
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end else if (valid_i) begin
+                clk_div_cnt <= clk_div_cnt + 1;
+            end else begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end
+        end
+
+        assign  clk_div_flag    = &clk_div_cnt;
+    end
+endgenerate
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end else if (valid_i) begin
+        if (clk_div_flag) begin
+            signal_o    <= ~signal_o;
+        end
+        rising_edge_o   <= ~signal_o & clk_div_flag;
+        falling_edge_o  <= signal_o & clk_div_flag;
+    end else begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end
+end
+
+endmodule

AdcInit/ResetFilter.v

@@ -0,0 +1,60 @@
+module ResetFilter (
+    clk_i,
+    rst_i,
+    perm_i,
+    filtered_rst_o
+);
+
+    parameter   STAGE_NUM   = 1;
+    parameter   RESET_FRONT = "RISING"; //  FALLING
+
+    input   clk_i;
+    input   rst_i;
+    input   perm_i;
+    output  filtered_rst_o;
+
+    reg [STAGE_NUM-1:0] rst_filter;
+
+    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];
+
+generate
+    if (RESET_FRONT == "RISING") begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end
+    end else begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end    
+    end
+endgenerate
+
+endmodule

AdcInit/SinglePortRom.v

@@ -0,0 +1,30 @@
+module SinglePortRom (
+    clk_i, 
+    addr_i,
+    q_o
+);
+
+    parameter   DATA_WIDTH      = 16; 
+    parameter   ADDR_WIDTH      = 5;
+    parameter   INIT_FILE_NAME  = "./initFiles/AdcInitData.txt";
+    parameter   DATA_BASE       = "HEX";    //  HEX or BIN
+
+    input                                   clk_i;
+    input           [(ADDR_WIDTH-1):0]      addr_i;
+    output  reg     [(DATA_WIDTH-1):0]      q_o;
+
+    reg     [DATA_WIDTH-1:0]    rom[2**ADDR_WIDTH-1:0];
+
+initial begin
+    if (DATA_BASE == "HEX") begin
+        $readmemh(INIT_FILE_NAME, rom);
+    end else begin
+        $readmemb(INIT_FILE_NAME, rom);
+    end
+end
+
+always @ (posedge clk_i) begin
+    q_o <=  rom[addr_i];
+end
+
+endmodule

AdcInit/SpiMaster.v

@@ -0,0 +1,273 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   1.0 - It only send data (no miso port)
+// Additional Comments      :   MISO port need to be add. What about multiple slave select?
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module SpiMaster (
+    clk_i,
+    rst_i,
+
+    data_i,
+    valid_i,
+    ready_o,
+
+    mosi_o,
+    sck_o,
+    ss_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   CLK_DIVISOR_POWER   = 4; //WAS 2 !! DONT FORGET TO CHANGE!
+    parameter   DATA_WIDTH          = 24;
+    parameter   CPOL                = 0;
+    parameter   CPHA                = 0;
+    parameter   DATA_DIRECTION      = "MSBT";   //  MSB or LSB
+    parameter   EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  BIT_CNT_W           = bit_num(DATA_WIDTH);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  SM_IDLE_S   = 2'b00;
+    localparam  SM_START_S  = 2'b01;
+    localparam  SM_DATA_S   = 2'b10;
+    localparam  SM_STOP_S   = 2'b11;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input                               clk_i;
+    input                               rst_i;
+
+    input           [DATA_WIDTH-1:0]    data_i;
+    input                               valid_i;
+    output                              ready_o;
+
+    output  reg                         mosi_o;
+    output  reg                         sck_o;
+    output  reg                         ss_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               sm_curr_state;
+    reg     [1:0]               sm_next_state;
+
+    reg                         sm_clk_div_en;
+
+    //  Clock divider outputs
+
+    wire                        clk_divider_redge;
+    wire                        clk_divider_fedge;
+
+    //  Bits counter
+
+    reg     [BIT_CNT_W-1:0]     bit_cnt_r;
+    reg     [BIT_CNT_W-1:0]     bit_cnt_next;
+
+    //  Data buffers
+
+    reg     [DATA_WIDTH-1:0]    tx_buffer_r;
+    reg     [DATA_WIDTH-1:0]    tx_buffer_next;
+    wire    [DATA_WIDTH-1:0]    tx_buffer_shifted;
+    wire                        tx_curr_bit;
+
+    //  Output data next
+    reg                         mosi_next;
+    reg                         sck_next;
+    reg                         ss_next;
+
+    //  Edges
+
+    wire                        mosi_shift_edge;
+
+    wire                        ss_start_edge;
+    wire                        ss_stop_edge;
+
+    wire                        sck_leading_edge;
+    wire                        sck_trailing_edge;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  mosi_shift_edge     = (CPHA[0] == 1'b1) && (EN_START_DELAY != "YES") || (CPHA[0] == 1'b0) && (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_start_edge       = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_stop_edge        = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_leading_edge    = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_trailing_edge   = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  tx_buffer_shifted   = (DATA_DIRECTION == "MSB") ? tx_buffer_r << 1 : tx_buffer_r >> 1;
+    assign  tx_curr_bit         = (DATA_DIRECTION == "MSB") ? tx_buffer_r[DATA_WIDTH-1] : tx_buffer_r[0];
+
+    assign  ready_o             = sm_curr_state == SM_IDLE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//  Sequential logic
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        tx_buffer_r     <= {DATA_WIDTH{1'b0}};
+        bit_cnt_r       <= {BIT_CNT_W{1'b0}};
+        mosi_o          <= 1'b0;
+        sck_o           <= CPOL[0];
+        ss_o            <= 1'b1;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        tx_buffer_r     <= tx_buffer_next;
+        bit_cnt_r       <= bit_cnt_next;
+        mosi_o          <= mosi_next;
+        sck_o           <= sck_next;
+        ss_o            <= ss_next;
+    end
+end
+
+//  Combinational logic
+
+always @(*) begin
+    sm_next_state   = SM_IDLE_S;
+    tx_buffer_next  = tx_buffer_r;
+    mosi_next       = mosi_o;
+    sck_next        = sck_o;
+    ss_next         = ss_o;
+    sm_clk_div_en   = 1'b1;
+    bit_cnt_next    = bit_cnt_r;
+
+    case(sm_curr_state)
+
+        SM_IDLE_S   : begin
+            if (valid_i) begin
+                sm_next_state   = SM_START_S;
+            end else begin
+                sm_next_state   = SM_IDLE_S;
+            end
+            tx_buffer_next  = data_i;
+            sm_clk_div_en   = 1'b0;
+            bit_cnt_next    = {BIT_CNT_W{1'b0}};
+        end
+
+        SM_START_S  : begin
+            if (ss_start_edge) begin
+                sm_next_state   = SM_DATA_S;
+                ss_next         = 1'b0;
+                if (!CPHA[0]) begin
+                    mosi_next       = tx_curr_bit;
+                    tx_buffer_next  = tx_buffer_shifted;
+                    bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+                end
+            end else begin
+                sm_next_state   = SM_START_S;
+            end
+        end
+
+        SM_DATA_S   : begin
+            sm_next_state   = SM_DATA_S;
+            if (sck_leading_edge) begin
+                sck_next    = ~CPOL[0];
+            end
+
+            if  (sck_trailing_edge) begin
+                sck_next    = CPOL[0];
+                if (bit_cnt_r == DATA_WIDTH[BIT_CNT_W-1:0]) begin
+                    sm_next_state   = SM_STOP_S;
+                end
+            end
+
+            if (mosi_shift_edge) begin
+                mosi_next       = tx_curr_bit;
+                tx_buffer_next  = tx_buffer_shifted;
+                bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+            end
+
+        end
+
+        SM_STOP_S   : begin
+            if (ss_stop_edge) begin
+                if (CPHA[0]) begin
+                    mosi_next   = tx_curr_bit;
+                end
+                sm_next_state   = SM_IDLE_S;
+                ss_next         = 1'b1;
+            end else begin
+                sm_next_state   = SM_STOP_S;
+            end
+        end
+
+    endcase
+end
+
+//  Clock divider
+
+Power2ClkDivider #(
+    .DIVISOR_POWER      (CLK_DIVISOR_POWER)
+) ClkDividerInst (
+    .clk_i              (clk_i),
+    .rst_i              (rst_i),
+    .valid_i            (sm_clk_div_en),
+    .signal_o           (),
+    .rising_edge_o      (clk_divider_redge),
+    .falling_edge_o     (clk_divider_fedge)
+);
+
+endmodule

AdcInit/initFiles/AdcInitData.txt

@@ -0,0 +1,26 @@
+400601
+40013C
+400300
+400400
+400533
+400602 
+400700
+400900
+400A02
+400B20
+400ED1
+400FD4
+401300
+401500
+402500
+402700
+441D00
+442202
+443428
+443908
+451D00
+452202
+453428
+453908
+460800
+470A00

SRAM/QuadSPIm.v

@@ -32,7 +32,7 @@ reg startR;
 reg [31:0] trCnt;
 reg valReg;
 reg valToRxFifo1;
-reg [2:0] ssCnt;
+reg [5:0] ssCnt;
 reg Ss;
 reg SSr;
 reg [7:0] mosiReg0;
@@ -49,7 +49,7 @@ wire SsPol = SELST_i ? Ss : ~Ss;
 //  ASSIGNMENTS
 //================================================================================
 
-assign Ss_o = SsPol; 
+assign Ss_o = Ss; 
 assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
 //================================================================================
 //  CODING
@@ -126,146 +126,288 @@ end
 
 
 
-always @(*) begin 
-    if (PulsePol_i) begin 
-        if (CPHA_i) begin
-            if (LEAD_i == 0) begin 
-            if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                Sck_o = ~(~Clk_i);
-            end
-            else begin 
-                Sck_o = 1'b0;
-                end
-            end
-            else begin 
-                if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+always @(*) begin
+    if (SELST_i) begin 
+        if (PulsePol_i) begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                     Sck_o = ~(~Clk_i);
                 end
                 else begin 
                     Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-        end
-        else begin
-            if (LEAD_i == 0) begin 
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(Clk_i);
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-            else begin 
-                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(Clk_i);
+        end
+        else begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin  
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
+                end
+            end 
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
         end
     end
     else begin 
-        if (CPHA_i) begin
-            if (LEAD_i == 0) begin  
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(Clk_i);
+          if (PulsePol_i) begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin 
+                if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(~Clk_i);
                 end
                 else begin 
                     Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-            else begin 
-                if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(Clk_i);
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-        end 
-        else begin
-            if (LEAD_i == 0) begin 
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(~Clk_i);
+        end
+        else begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin  
+                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
-            end
-            else begin 
-                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(~Clk_i);
+            end 
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
         end
     end
+        
 end
 
 
 always @(*) begin
-    if (EndianSel_i) begin 
-        case (WidthSel_i) 
-            0 : begin 
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg3[1]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[1]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[1]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[1]):1'b0;
-            end
-            1 : begin 
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[3]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[3]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[3]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[3]):1'b0;
-            end
-            2 : begin 
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[5]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[5]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[5]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[5]):1'b0;
-            end
-            3 : begin 
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[7]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[7]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[7]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[7]):1'b0;
-            end
-        endcase
+    if (SELST_i) begin 
+        if (EndianSel_i) begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                1 : begin 
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                2 : begin 
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                3 : begin 
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+            endcase
+        end
+        else begin 
+            case (WidthSel_i)
+                0 : begin
+                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                end
+                1 : begin
+                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                end
+                2 : begin
+                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                end
+                3 : begin
+                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                end
+            endcase
+        end
     end
     else begin 
-        case (WidthSel_i)
-            0 : begin
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
-            end
-            1 : begin
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
-            end
-            2 : begin
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
-            end
-            3 : begin
-                Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
-                Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
-                Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
-            end
-        endcase
+        if (EndianSel_i) begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                1 : begin 
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                2 : begin
+                    Mosi0_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+                3 : begin 
+                    Mosi0_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
+                    Mosi1_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi2_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi3_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                end
+            endcase
+        end
+        else begin 
+            case (WidthSel_i)
+                0 : begin
+                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                end
+                1 : begin
+                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                end
+                2 : begin
+                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                end
+                3 : begin
+                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                end
+            endcase
+        end
     end
 end
 
 
+
 always @(posedge Clk_i) begin
     SSr <= Ss;
 end
@@ -346,16 +488,31 @@ end
 
 
 
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        Ss <= 1'b1;
+always @(negedge Clk_i) begin
+    if (SELST_i) begin  
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
     end
     else begin 
-        if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+        if (Rst_i) begin 
             Ss <= 1'b0;
         end
         else begin 
-            Ss <= 1'b1;
+            if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+                Ss <= 1'b1;
+            end
+            else begin 
+                Ss <= 1'b0;
+            end
         end
     end
 end
@@ -365,12 +522,42 @@ always @(negedge Clk_i) begin
     if (Rst_i) begin 
         mosiReg0 <= SPIdata[31:24];
     end
-    else begin 
-        if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-            mosiReg0 <= { mosiReg0[6:0],1'b0 };
+    else begin
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin 
+                if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg0 <= { mosiReg0[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg0 <= SPIdata[31:24];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg0 <= { mosiReg0[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg0 <= SPIdata[31:24];
+                end
+            end
         end
         else begin 
-            mosiReg0 <= SPIdata[31:24];
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg0 <= {1'b0, mosiReg0[7:1] };
+                end
+                else begin 
+                    mosiReg0 <= SPIdata[31:24];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg0 <= {1'b0, mosiReg0[7:1] };
+                end
+                else begin 
+                    mosiReg0 <= SPIdata[31:24];
+                end
+            end
         end
     end
 end
@@ -379,12 +566,42 @@ always @(negedge Clk_i) begin
     if (Rst_i) begin 
         mosiReg1 <= SPIdata[23:16];
     end
-    else begin 
-        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-            mosiReg1 <= { mosiReg1[6:0],1'b0 };
+    else begin
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg1 <= { mosiReg1[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg1 <= SPIdata[23:16];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg1 <= { mosiReg1[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg1 <= SPIdata[23:16];
+                end
+            end
         end
         else begin 
-            mosiReg1 <= SPIdata[23:16];
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg1 <= {1'b0, mosiReg1[7:1] };
+                end
+                else begin 
+                    mosiReg1 <= SPIdata[23:16];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg1 <= {1'b0, mosiReg1[7:1] };
+                end
+                else begin 
+                    mosiReg1 <= SPIdata[23:16];
+                end
+            end
         end
     end
 end
@@ -393,12 +610,42 @@ always @(negedge Clk_i) begin
     if (Rst_i) begin 
         mosiReg2 <= SPIdata[15:8];
     end
-    else begin 
-        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-            mosiReg2 <= { mosiReg2[6:0],1'b0 };
+    else begin
+        if (!EndianSel_i) begin
+            if (SELST_i) begin  
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg2 <= { mosiReg2[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg2 <= SPIdata[15:8];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg2 <= { mosiReg2[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg2 <= SPIdata[15:8];
+                end
+            end
         end
         else begin 
-            mosiReg2 <= SPIdata[15:8];
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg2 <= {1'b0, mosiReg2[7:1] };
+                end
+                else begin 
+                    mosiReg2 <= SPIdata[15:8];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg2 <= {1'b0, mosiReg2[7:1] };
+                end
+                else begin 
+                    mosiReg2 <= SPIdata[15:8];
+                end
+            end
         end
     end
 end
@@ -407,12 +654,42 @@ always @(negedge Clk_i) begin
     if (Rst_i) begin 
         mosiReg3 <= SPIdata[7:0];
     end
-    else begin 
-        if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-            mosiReg3 <= { mosiReg3[6:0],1'b0 };
+    else begin
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg3 <= { mosiReg3[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg3 <= SPIdata[7:0];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg3 <= { mosiReg3[6:0],1'b0 };
+                end
+                else begin 
+                    mosiReg3 <= SPIdata[7:0];
+                end
+            end
         end
         else begin 
-            mosiReg3 <= SPIdata[7:0];
+            if (SELST_i) begin 
+                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg3 <= {1'b0, mosiReg3[7:1] };
+                end
+                else begin 
+                    mosiReg3 <= SPIdata[7:0];
+                end
+            end
+            else begin 
+                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                    mosiReg3 <= {1'b0, mosiReg3[7:1] };
+                end
+                else begin 
+                    mosiReg3 <= SPIdata[7:0];
+                end
+            end
         end
     end
 end

SRAM/QuadSPIs.v

@@ -11,6 +11,7 @@ module QuadSPIs (
 
     input [1:0] WidthSel_i,
     input SELST_i,
+    input EndianSel_i,
    
 
     output reg [23:0] Data_o,
@@ -138,7 +139,7 @@ always @(posedge Sck_i) begin
     else begin
         if (SELST_i) begin   
             if (!Ss_i) begin 
-                shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
             end
             else begin 
                 shiftReg0 <= 8'h0;
@@ -146,7 +147,7 @@ always @(posedge Sck_i) begin
         end
         else begin 
             if (Ss_i) begin 
-                shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
             end
             else begin 
                 shiftReg0<= 8'h0;
@@ -163,7 +164,7 @@ always @(posedge Sck_i ) begin
     else begin
         if (SELST_i) begin   
             if (!Ss_i) begin 
-                shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
             end
             else begin 
                 shiftReg1 <= 8'h0;
@@ -171,7 +172,7 @@ always @(posedge Sck_i ) begin
         end
         else begin 
             if (Ss_i) begin 
-                shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
             end
             else begin 
                 shiftReg1 <= 8'h0;
@@ -188,7 +189,7 @@ always @(posedge Sck_i ) begin
     else begin
         if (SELST_i) begin   
             if (!Ss_i) begin 
-                shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
             end
             else begin 
                 shiftReg2 <= 8'h0;
@@ -196,7 +197,7 @@ always @(posedge Sck_i ) begin
         end
         else begin 
             if (Ss_i) begin 
-                shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
             end
             else begin 
                 shiftReg2 <= 8'h0;
@@ -213,7 +214,7 @@ always @(posedge Sck_i ) begin
     else begin
         if (SELST_i) begin 
             if (!Ss_i) begin 
-                addrReg <= {addrReg[6:0], Mosi3_i};
+                addrReg <= {addrReg[6:0], Mosi0_i};
             end
             else begin 
                 addrReg <= 8'h0;
@@ -221,7 +222,7 @@ always @(posedge Sck_i ) begin
         end
         else begin 
             if (Ss_i) begin 
-                addrReg <= {addrReg[6:0], Mosi3_i};
+                addrReg <= {addrReg[6:0], Mosi0_i};
             end
             else begin 
                 addrReg <= 8'h0;

SRAM/RegMap.v

@@ -77,7 +77,7 @@ module RegMap #(
     output   [CmdRegWidth/2-1:0] Spi6RxFifoReg_o,
 
     output   [CmdRegWidth/2-1:0] SpiTxRxEnReg_o,
-    output   [CmdRegWidth/2-1:0] GPIOAReg_o,
+    output   [CmdRegWidth-1:0] GPIOAReg_o,
 
     output   [CmdRegWidth/2-1:0] AnsDataReg_o,
     output Led_o
@@ -155,6 +155,7 @@ reg [CmdRegWidth/2-1:0] Spi6RxFifoReg;
 
 reg [CmdRegWidth/2-1:0] SpiTxRxEnReg;
 reg [CmdRegWidth/2-1:0] GPIOAReg;
+reg [CmdRegWidth/2-1:0] GPIOARegS;
 
 
 (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg;
@@ -227,7 +228,7 @@ assign Spi6TxFifoReg_o = Spi6TxFifoReg;
 assign Spi6RxFifoReg_o = Spi6RxFifoReg;
 
 assign SpiTxRxEnReg_o = SpiTxRxEnReg;
-assign GPIOAReg_o = GPIOAReg;
+assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
 
 
 
@@ -303,6 +304,7 @@ localparam Spi6RxFifo = 12'h24c;
 
 localparam SpiTxRxEn = 12'hF00;
 localparam GPIOCtrlAddr = 12'hFF0;
+localparam GPIOCtrlAddrS = 12'hFF2;
 
 localparam Debug0Addr = 12'hFF8;
 localparam Debug1Addr = 12'hFFC;
@@ -370,6 +372,7 @@ always @(posedge Clk_i) begin
         Spi6RxFifoReg <= 0;
         SpiTxRxEnReg <= 0;
         GPIOAReg <= 0;
+        GPIOARegS <= 0;
         LedReg <= 0;
     end
     else begin 
@@ -549,7 +552,10 @@ always @(posedge Clk_i) begin
                             SpiTxRxEnReg <= Data_i;
                         end
                         GPIOCtrlAddr : begin 
-                            GPIOAReg <= Data_i;
+                            GPIOAReg <= Data_i[15:0];
+                        end
+                        GPIOCtrlAddrS : begin 
+                            GPIOARegS <= Data_i[31:16];
                         end
                         Debug0Addr : begin 
                             LedReg <= Data_i;
@@ -732,6 +738,9 @@ always @(posedge Clk_i) begin
                         GPIOCtrlAddr : begin 
                             GPIOAReg[15:8] <= Data_i[15:8];
                         end
+                        GPIOCtrlAddrS : begin 
+                            GPIOARegS[15:8] <= Data_i[31:24];
+                        end
                         Debug0Addr : begin 
                             LedReg[15:8] <= Data_i[15:8];
                         end
@@ -913,6 +922,9 @@ always @(posedge Clk_i) begin
                         GPIOCtrlAddr : begin 
                             GPIOAReg[7:0] <= Data_i[7:0];
                         end
+                        GPIOCtrlAddrS : begin 
+                            GPIOARegS[7:0] <= Data_i[23:16];
+                        end
                         Debug0Addr : begin 
                             LedReg[7:0] <= Data_i[7:0];
                         end
@@ -1105,6 +1117,9 @@ always @(*) begin
 						GPIOCtrlAddr : begin 
 							ansReg = GPIOAReg;
 						end
+                        GPIOCtrlAddrS : begin 
+                            ansReg = GPIOARegS;
+                        end
 						Debug0Addr : begin 
 							ansReg = LedReg;
 						end
@@ -1286,6 +1301,9 @@ always @(*) begin
 						GPIOCtrlAddr : begin 
 							ansReg = GPIOAReg[15:8];
 						end
+                        GPIOCtrlAddrS : begin 
+                            ansReg = GPIOARegS[15:8];
+                        end
 						Debug0Addr : begin 
 							ansReg = LedReg[15:8];
 						end
@@ -1467,6 +1485,9 @@ always @(*) begin
 						GPIOCtrlAddr : begin 
 							ansReg = GPIOAReg[7:0];
 						end
+                        GPIOCtrlAddrS : begin 
+                            ansReg = GPIOARegS[7:0];
+                        end
 						Debug0Addr : begin 
 							ansReg = LedReg[7:0];
 						end

sources_1/new/MMCM/.idea/.gitignore

@@ -0,0 +1,8 @@
+# Default ignored files
+/shelf/
+/workspace.xml
+# Editor-based HTTP Client requests
+/httpRequests/
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml

sources_1/new/MMCM/.idea/MMCM.iml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<module classpath="CMake" type="CPP_MODULE" version="4">
+  <component name="SonarLintModuleSettings">
+    <option name="uniqueId" value="2a230afb-35f1-403e-a433-548af2d8ebe0" />
+  </component>
+</module>

sources_1/new/MMCM/.idea/misc.xml

@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="CMakeWorkspace" PROJECT_DIR="$PROJECT_DIR$" />
+</project>

sources_1/new/MMCM/.idea/modules.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="ProjectModuleManager">
+    <modules>
+      <module fileurl="file://$PROJECT_DIR$/.idea/MMCM.iml" filepath="$PROJECT_DIR$/.idea/MMCM.iml" />
+    </modules>
+  </component>
+</project>

sources_1/new/MMCM/.idea/sonarlint/issuestore/index.pb

@@ -0,0 +1,5 @@
+
+>
+CMakeLists.txt,9\a\9a2aa4db38d3115ed60da621e012c0efc0172aae
+=
+
MmcmWrapper.v,d\a\da020c612d0c4048d719bfbe42bb8803a425696a

sources_1/new/MMCM/.idea/sonarlint/securityhotspotstore/index.pb

@@ -0,0 +1,5 @@
+
+>
+CMakeLists.txt,9\a\9a2aa4db38d3115ed60da621e012c0efc0172aae
+=
+
MmcmWrapper.v,d\a\da020c612d0c4048d719bfbe42bb8803a425696a

sources_1/new/MMCM/.idea/vcs.xml

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$/../../.." vcs="Git" />
+  </component>
+</project>

sources_1/new/MMCM/CMakeLists.txt

@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.25)
+project(MMCM C)
+
+set(CMAKE_C_STANDARD 11)
+
+include_directories(.)
+
+add_executable(MMCM
+        mmcme2_drp_func.h)

sources_1/new/MMCM/Division.c

@@ -0,0 +1,39 @@
+#include <stdio.h>
+#include <math.h>
+
+int main() {
+    double dividend, divisor;
+    double quotient, fractional_part;
+    int whole_part, count_0125;
+
+    // Запрос ввода чисел у пользователя
+    printf("Введите делимое: ");
+    scanf("%lf", &dividend);
+    printf("Введите делитель: ");
+    scanf("%lf", &divisor);
+
+    // Проверка деления на ноль
+    if (divisor == 0) {
+        printf("Ошибка: Деление на ноль!\n");
+        return 1;
+    }
+
+    
+    quotient = dividend / divisor;
+    whole_part = (int)quotient; // целая часть
+    fractional_part = quotient - whole_part; // дробная часть
+
+   
+    double count_0125_exact = fractional_part * 8;
+    if (count_0125_exact - floor(count_0125_exact) < 0.5) {
+        count_0125 = (int)floor(count_0125_exact);
+    } else {
+        count_0125 = (int)ceil(count_0125_exact);
+    }
+
+    printf("Целая часть: %d\n", whole_part);
+    printf("Дробная часть: %lf\n", fractional_part);
+    printf("Округленное количество единиц 0.125 в дробной части: %d\n", count_0125);
+
+    return 0;
+}

sources_1/new/MMCM/MmcmWrapper.v

@@ -4,124 +4,254 @@ module MmcmWrapper
 	parameter	SpiNum	=	7
 )
 (
-    input	Clk_i,
-    input	Rst_i,
+   input	Clk_i,
+   input	Rst_i,
+   input [6:0] ClkDiv1_i,
+   input [15:0] ClkDiv2_i,
+   input [15:0] ClkDiv3_i,
+   input [15:0] ClkDiv4_i,
+   input [15:0] ClkDiv5_i,
+   input [15:0] ClkDiv6_i,
+   input [15:0] ClkDiv7_i,
 
-	output	[SpiNum-1:0]	SpiCLk_o
+
+
+	output	[SpiNum-1:0]	SpiClk_o
 );
 //================================================================================
 //	REG/WIRE
 //================================================================================
 	
-wire            clkfb_bufgout;
-wire            clkfb_bufgin;
-wire            clk0_bufgin;
-wire            clk1_bufgin;
-wire            clk2_bufgin;
-wire            clk3_bufgin;
-wire            clk4_bufgin;
-wire            clk5_bufgin;
-wire            clk6_bufgin;
+wire            clk0out;
+wire            clk1out;
+wire            clk2out;
+wire            clk3out;
+wire            clk4out;
+wire            clk5out;
+wire            clk6out;
+wire            SRDY;
+wire            locked;
+
+reg [1:0] SM = STARTUP;
+reg SSTEP;
+
+reg sStep1;
+reg sStep2;
+reg sStep3;
+reg sStep4;
+reg sStep5;
+reg sStep6;
+reg sStep7;
+
+
+reg clkDiv1R;
+reg clkDiv2R;
+reg clkDiv3R;
+reg clkDiv4R;
+reg clkDiv5R;
+reg clkDiv6R;
+reg clkDiv7R;
+
+
 
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	
+	assign SpiClk_o[0]	=	clk0out;
+   assign SpiClk_o[1]	=	clk1out;
+   assign SpiClk_o[2]	=	clk2out;
+   assign SpiClk_o[3]	=	clk3out;
+   assign SpiClk_o[4]	=	clk4out;
+   assign SpiClk_o[5]	=	clk5out;
+   assign SpiClk_o[6]	=	clk6out;
+
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
+parameter [1:0] STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;
 
 //================================================================================
 //	CODING
 //================================================================================
+top_mmcme2 MMCE2_inst (
+   .SSTEP      (),
+   .STATE      (),
+   .RST        (Rst_i),
+   .CLKIN      (Clk_i),
+   .SRDY       (SRDY),
+   .LOCKED_OUT (locked),
+   .CLK0OUT    (clk0out),
+   .CLK1OUT    (clk1out),
+   .CLK2OUT    (clk2out),
+   .CLK3OUT    (clk3out),
+   .CLK4OUT    (clk4out),
+   .CLK5OUT    (clk5out),
+   .CLK6OUT    (clk6out)
+
+
+
+
+
+
+
+
 
-MMCME2_ADV 
-#(
-   .BANDWIDTH           ("OPTIMIZED"),
-   .DIVCLK_DIVIDE       (1),
-   .CLKFBOUT_MULT_F     (10),
-   .CLKFBOUT_PHASE      (0.0),
-   .CLKFBOUT_USE_FINE_PS("FALSE"),
-   // .CLKIN1_PERIOD       (10.000),
-   .CLKIN1_PERIOD       (8.130081300813),
-   .CLKIN2_PERIOD       (10.000),
-   .CLKOUT0_DIVIDE_F    (15.25),
-   .CLKOUT0_DUTY_CYCLE  (0.5),
-   .CLKOUT0_PHASE       (0.0),
-   .CLKOUT0_USE_FINE_PS ("FALSE"),
-   .CLKOUT1_DIVIDE      (12.3),
-   .CLKOUT1_DUTY_CYCLE  (0.5),
-   .CLKOUT1_PHASE       (0.0),
-   .CLKOUT1_USE_FINE_PS ("FALSE"),
-   .CLKOUT2_DIVIDE      (12.3),
-   .CLKOUT2_DUTY_CYCLE  (0.5),
-   .CLKOUT2_PHASE       (0.0),
-   .CLKOUT2_USE_FINE_PS ("FALSE"),
-   .CLKOUT3_DIVIDE      (12.3),
-   .CLKOUT3_DUTY_CYCLE  (0.5),
-   .CLKOUT3_PHASE       (0.0),
-   .CLKOUT3_USE_FINE_PS ("FALSE"),
-   .CLKOUT4_DIVIDE      (12.3),
-   .CLKOUT4_DUTY_CYCLE  (0.5),
-   .CLKOUT4_PHASE       (0.0),
-   .CLKOUT4_USE_FINE_PS ("FALSE"),
-   .CLKOUT4_CASCADE     ("FALSE"),
-   .CLKOUT5_DIVIDE      (12.3),
-   .CLKOUT5_DUTY_CYCLE  (0.5),
-   .CLKOUT5_PHASE       (0.0),
-   .CLKOUT5_USE_FINE_PS ("FALSE"),
-   .CLKOUT6_DIVIDE      (12.3),
-   .CLKOUT6_DUTY_CYCLE  (0.5),
-   .CLKOUT6_PHASE       (0.0),
-   .CLKOUT6_USE_FINE_PS ("FALSE"),
-   .COMPENSATION        ("ZHOLD"),
-   .STARTUP_WAIT        ("FALSE")
-) 
-mmcme2_test_inst 
-(
-   .CLKFBOUT            (clkfb_bufgin),
-   .CLKFBOUTB           (),
-   .CLKFBSTOPPED        (),
-   .CLKINSTOPPED        (),
-   .CLKOUT0             (clk0_bufgin),
-   .CLKOUT0B            (),
-   .CLKOUT1             (clk1_bufgin),
-   .CLKOUT1B            (),
-   .CLKOUT2             (clk2_bufgin),
-   .CLKOUT2B            (),
-   .CLKOUT3             (clk3_bufgin),
-   .CLKOUT3B            (),
-   .CLKOUT4             (clk4_bufgin),
-   .CLKOUT5             (clk5_bufgin),
-   .CLKOUT6             (clk6_bufgin),
-   .DO                  (dout),
-   .DRDY                (drdy),
-   .DADDR               (daddr),
-   .DCLK                (dclk),
-   .DEN                 (den),
-   .DI                  (di),
-   .DWE                 (dwe),
-   .LOCKED              (LOCKED),
-   .CLKFBIN             (clkfb_bufgout),
-   .CLKIN1              (Clk_i),
-   .CLKIN2              (),
-   .CLKINSEL            (1'b1),
-   .PSDONE              (),
-   .PSCLK               (1'b0),
-   .PSEN                (1'b0),
-   .PSINCDEC            (1'b0),
-   .PWRDWN              (1'b0),
-   .RST                 (Rst_i)
 );
 
-BUFG BUFG_FB    (.O (clkfb_bufgout),    .I (clkfb_bufgin));
-BUFG BUFG_CLK0  (.O (SpiCLk_o[0]),     .I (clk0_bufgin));
-BUFG BUFG_CLK1  (.O (SpiCLk_o[1]),     .I (clk0_bufgin));
-BUFG BUFG_CLK2  (.O (SpiCLk_o[2]),     .I (clk0_bufgin));
-BUFG BUFG_CLK3  (.O (SpiCLk_o[3]),     .I (clk0_bufgin));
-BUFG BUFG_CLK4  (.O (SpiCLk_o[4]),     .I (clk0_bufgin));
-BUFG BUFG_CLK5  (.O (SpiCLk_o[5]),     .I (clk0_bufgin));
-BUFG BUFG_CLK6  (.O (SpiCLk_o[6]),     .I (clk0_bufgin));
+always @(posedge Clk_i) begin 
+   if (Rst_i) begin 
+      clkDiv1R <= 1'b0;
+      clkDiv2R <= 1'b0;
+      clkDiv3R <= 1'b0;
+      clkDiv4R <= 1'b0;
+      clkDiv5R <= 1'b0;
+      clkDiv6R <= 1'b0;
+      clkDiv7R <= 1'b0;
+   end
+   else begin 
+      clkDiv1R <= ClkDiv1_i;
+      clkDiv2R <= ClkDiv2_i;
+      clkDiv3R <= ClkDiv3_i;
+      clkDiv4R <= ClkDiv4_i;
+      clkDiv5R <= ClkDiv5_i;
+      clkDiv6R <= ClkDiv6_i;
+      clkDiv7R <= ClkDiv7_i;
+   end
+end
+
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep1<= 1'b0;
+   end
+   else begin 
+      if (clkDiv1R != ClkDiv1_i) begin 
+         sStep1 <= 1'b1;
+      end
+      else begin 
+         sStep1 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep2<= 1'b0;
+   end
+   else begin 
+      if (clkDiv2R != ClkDiv2_i) begin 
+         sStep2 <= 1'b1;
+      end
+      else begin 
+         sStep2 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep3<= 1'b0;
+   end
+   else begin 
+      if (clkDiv3R != ClkDiv3_i) begin 
+         sStep3 <= 1'b1;
+      end
+      else begin 
+         sStep3 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep4<= 1'b0;
+   end
+   else begin 
+      if (clkDiv4R!= ClkDiv4_i) begin 
+         sStep4 <= 1'b1;
+      end
+      else begin 
+         sStep4 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep5<= 1'b0;
+   end
+   else begin 
+      if (clkDiv5R != ClkDiv5_i) begin 
+         sStep5 <= 1'b1;
+      end
+      else begin 
+         sStep5 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep6<= 1'b0;
+   end
+   else begin 
+      if (clkDiv6R != ClkDiv6_i) begin 
+         sStep6 <= 1'b1;
+      end
+      else begin 
+         sStep6 <= 1'b0;
+      end
+   end
+end
+
+always @(*) begin 
+   if (Rst_i) begin 
+      sStep7<= 1'b0;
+   end
+   else begin 
+      if (clkDiv7R != ClkDiv7_i) begin 
+         sStep7 <= 1'b1;
+      end
+      else begin 
+         sStep7 <= 1'b0;
+      end
+   end
+end
+
+// always @ (posedge Clk_i) begin 
+//    if (Rst_i) begin
+//       SM <= STARTUP;
+//    end
+//    else begin 
+//       case (SM)
+//          STARTUP: begin
+//             SM <= STATE0;
+//             SSTEP <= 1'b0;
+//             STATE <= 1'b0;
+//          end
+//          STATE0: begin
+//                if(locked) begin 
+//                   if (ssTep1 | ssTep2 | ssTep3 | ssTep4 | ssTep5 | ssTep6 | ssTep7) begin 
+//                      SSTEP <= 1'b1;
+//                   end
+//                   else begin 
+//                      SSTEP <= 1'b0;
+//                   end
+//                end
+//             end
+//          end
+//          STATE1: begin
+//             if (SRDY) begin
+//                SM <= STATE0;
+//             end
+//          end
+//          UNDEFINED: begin
+//             SM <= STARTUP;
+//          end
+//       endcase
+//    end
+// end
+
 
 
 endmodule

sources_1/new/MMCM/cmake-build-debug/CMakeCache.txt

@@ -0,0 +1,363 @@
+# This is the CMakeCache file.
+# For build in directory: c:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug
+# It was generated by CMake: C:/Program Files/JetBrains/CLion 2023.1.4/bin/cmake/win/x64/bin/cmake.exe
+# You can edit this file to change values found and used by cmake.
+# If you do not want to change any of the values, simply exit the editor.
+# If you do want to change a value, simply edit, save, and exit the editor.
+# The syntax for the file is as follows:
+# KEY:TYPE=VALUE
+# KEY is the name of a variable in the cache.
+# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!.
+# VALUE is the current value for the KEY.
+
+########################
+# EXTERNAL cache entries
+########################
+
+//Path to a program.
+CMAKE_ADDR2LINE:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/addr2line.exe
+
+//Path to a program.
+CMAKE_AR:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ar.exe
+
+//Choose the type of build, options are: None Debug Release RelWithDebInfo
+// MinSizeRel ...
+CMAKE_BUILD_TYPE:STRING=Debug
+
+//Enable colored diagnostics throughout.
+CMAKE_COLOR_DIAGNOSTICS:BOOL=ON
+
+//C compiler
+CMAKE_C_COMPILER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc.exe
+
+//A wrapper around 'ar' adding the appropriate '--plugin' option
+// for the GCC compiler
+CMAKE_C_COMPILER_AR:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc-ar.exe
+
+//A wrapper around 'ranlib' adding the appropriate '--plugin' option
+// for the GCC compiler
+CMAKE_C_COMPILER_RANLIB:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc-ranlib.exe
+
+//Flags used by the C compiler during all build types.
+CMAKE_C_FLAGS:STRING=
+
+//Flags used by the C compiler during DEBUG builds.
+CMAKE_C_FLAGS_DEBUG:STRING=-g
+
+//Flags used by the C compiler during MINSIZEREL builds.
+CMAKE_C_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG
+
+//Flags used by the C compiler during RELEASE builds.
+CMAKE_C_FLAGS_RELEASE:STRING=-O3 -DNDEBUG
+
+//Flags used by the C compiler during RELWITHDEBINFO builds.
+CMAKE_C_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG
+
+//Libraries linked by default with all C applications.
+CMAKE_C_STANDARD_LIBRARIES:STRING=-lkernel32 -luser32 -lgdi32 -lwinspool -lshell32 -lole32 -loleaut32 -luuid -lcomdlg32 -ladvapi32
+
+//Path to a program.
+CMAKE_DLLTOOL:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/dlltool.exe
+
+//Flags used by the linker during all build types.
+CMAKE_EXE_LINKER_FLAGS:STRING=
+
+//Flags used by the linker during DEBUG builds.
+CMAKE_EXE_LINKER_FLAGS_DEBUG:STRING=
+
+//Flags used by the linker during MINSIZEREL builds.
+CMAKE_EXE_LINKER_FLAGS_MINSIZEREL:STRING=
+
+//Flags used by the linker during RELEASE builds.
+CMAKE_EXE_LINKER_FLAGS_RELEASE:STRING=
+
+//Flags used by the linker during RELWITHDEBINFO builds.
+CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO:STRING=
+
+//Enable/Disable output of compile commands during generation.
+CMAKE_EXPORT_COMPILE_COMMANDS:BOOL=
+
+//Value Computed by CMake.
+CMAKE_FIND_PACKAGE_REDIRECTS_DIR:STATIC=C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug/CMakeFiles/pkgRedirects
+
+//Convert GNU import libraries to MS format (requires Visual Studio)
+CMAKE_GNUtoMS:BOOL=OFF
+
+//Install path prefix, prepended onto install directories.
+CMAKE_INSTALL_PREFIX:PATH=C:/Program Files (x86)/MMCM
+
+//Path to a program.
+CMAKE_LINKER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ld.exe
+
+//make program
+CMAKE_MAKE_PROGRAM:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/ninja/win/x64/ninja.exe
+
+//Flags used by the linker during the creation of modules during
+// all build types.
+CMAKE_MODULE_LINKER_FLAGS:STRING=
+
+//Flags used by the linker during the creation of modules during
+// DEBUG builds.
+CMAKE_MODULE_LINKER_FLAGS_DEBUG:STRING=
+
+//Flags used by the linker during the creation of modules during
+// MINSIZEREL builds.
+CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL:STRING=
+
+//Flags used by the linker during the creation of modules during
+// RELEASE builds.
+CMAKE_MODULE_LINKER_FLAGS_RELEASE:STRING=
+
+//Flags used by the linker during the creation of modules during
+// RELWITHDEBINFO builds.
+CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO:STRING=
+
+//Path to a program.
+CMAKE_NM:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/nm.exe
+
+//Path to a program.
+CMAKE_OBJCOPY:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/objcopy.exe
+
+//Path to a program.
+CMAKE_OBJDUMP:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/objdump.exe
+
+//Value Computed by CMake
+CMAKE_PROJECT_DESCRIPTION:STATIC=
+
+//Value Computed by CMake
+CMAKE_PROJECT_HOMEPAGE_URL:STATIC=
+
+//Value Computed by CMake
+CMAKE_PROJECT_NAME:STATIC=MMCM
+
+//Path to a program.
+CMAKE_RANLIB:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ranlib.exe
+
+//RC compiler
+CMAKE_RC_COMPILER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/windres.exe
+
+//Flags for Windows Resource Compiler during all build types.
+CMAKE_RC_FLAGS:STRING=
+
+//Flags for Windows Resource Compiler during DEBUG builds.
+CMAKE_RC_FLAGS_DEBUG:STRING=
+
+//Flags for Windows Resource Compiler during MINSIZEREL builds.
+CMAKE_RC_FLAGS_MINSIZEREL:STRING=
+
+//Flags for Windows Resource Compiler during RELEASE builds.
+CMAKE_RC_FLAGS_RELEASE:STRING=
+
+//Flags for Windows Resource Compiler during RELWITHDEBINFO builds.
+CMAKE_RC_FLAGS_RELWITHDEBINFO:STRING=
+
+//Path to a program.
+CMAKE_READELF:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/readelf.exe
+
+//Flags used by the linker during the creation of shared libraries
+// during all build types.
+CMAKE_SHARED_LINKER_FLAGS:STRING=
+
+//Flags used by the linker during the creation of shared libraries
+// during DEBUG builds.
+CMAKE_SHARED_LINKER_FLAGS_DEBUG:STRING=
+
+//Flags used by the linker during the creation of shared libraries
+// during MINSIZEREL builds.
+CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL:STRING=
+
+//Flags used by the linker during the creation of shared libraries
+// during RELEASE builds.
+CMAKE_SHARED_LINKER_FLAGS_RELEASE:STRING=
+
+//Flags used by the linker during the creation of shared libraries
+// during RELWITHDEBINFO builds.
+CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO:STRING=
+
+//If set, runtime paths are not added when installing shared libraries,
+// but are added when building.
+CMAKE_SKIP_INSTALL_RPATH:BOOL=NO
+
+//If set, runtime paths are not added when using shared libraries.
+CMAKE_SKIP_RPATH:BOOL=NO
+
+//Flags used by the linker during the creation of static libraries
+// during all build types.
+CMAKE_STATIC_LINKER_FLAGS:STRING=
+
+//Flags used by the linker during the creation of static libraries
+// during DEBUG builds.
+CMAKE_STATIC_LINKER_FLAGS_DEBUG:STRING=
+
+//Flags used by the linker during the creation of static libraries
+// during MINSIZEREL builds.
+CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL:STRING=
+
+//Flags used by the linker during the creation of static libraries
+// during RELEASE builds.
+CMAKE_STATIC_LINKER_FLAGS_RELEASE:STRING=
+
+//Flags used by the linker during the creation of static libraries
+// during RELWITHDEBINFO builds.
+CMAKE_STATIC_LINKER_FLAGS_RELWITHDEBINFO:STRING=
+
+//Path to a program.
+CMAKE_STRIP:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/strip.exe
+
+//If this value is on, makefiles will be generated without the
+// .SILENT directive, and all commands will be echoed to the console
+// during the make.  This is useful for debugging only. With Visual
+// Studio IDE projects all commands are done without /nologo.
+CMAKE_VERBOSE_MAKEFILE:BOOL=FALSE
+
+//Value Computed by CMake
+MMCM_BINARY_DIR:STATIC=C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug
+
+//Value Computed by CMake
+MMCM_IS_TOP_LEVEL:STATIC=ON
+
+//Value Computed by CMake
+MMCM_SOURCE_DIR:STATIC=C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM
+
+
+########################
+# INTERNAL cache entries
+########################
+
+//ADVANCED property for variable: CMAKE_ADDR2LINE
+CMAKE_ADDR2LINE-ADVANCED:INTERNAL=1
+//ADVANCED property for variable: CMAKE_AR
+CMAKE_AR-ADVANCED:INTERNAL=1
+//This is the directory where this CMakeCache.txt was created
+CMAKE_CACHEFILE_DIR:INTERNAL=c:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug
+//Major version of cmake used to create the current loaded cache
+CMAKE_CACHE_MAJOR_VERSION:INTERNAL=3
+//Minor version of cmake used to create the current loaded cache
+CMAKE_CACHE_MINOR_VERSION:INTERNAL=25
+//Patch version of cmake used to create the current loaded cache
+CMAKE_CACHE_PATCH_VERSION:INTERNAL=2
+//Path to CMake executable.
+CMAKE_COMMAND:INTERNAL=C:/Program Files/JetBrains/CLion 2023.1.4/bin/cmake/win/x64/bin/cmake.exe
+//Path to cpack program executable.
+CMAKE_CPACK_COMMAND:INTERNAL=C:/Program Files/JetBrains/CLion 2023.1.4/bin/cmake/win/x64/bin/cpack.exe
+//Path to ctest program executable.
+CMAKE_CTEST_COMMAND:INTERNAL=C:/Program Files/JetBrains/CLion 2023.1.4/bin/cmake/win/x64/bin/ctest.exe
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+//Name of generator.
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+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION     % 10000)
+#else
+  /* __ARMCC_VERSION = VRPPPP */
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION    % 10000)
+#endif
+
+
+#elif defined(__clang__) && defined(__apple_build_version__)
+# define COMPILER_ID "AppleClang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
+
+#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
+# define COMPILER_ID "ARMClang"
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION     % 10000)
+# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
+
+#elif defined(__clang__)
+# define COMPILER_ID "Clang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+
+#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
+# define COMPILER_ID "LCC"
+# define COMPILER_VERSION_MAJOR DEC(1)
+# if defined(__LCC__)
+#  define COMPILER_VERSION_MINOR DEC(__LCC__- 100)
+# endif
+# if defined(__LCC_MINOR__)
+#  define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
+# endif
+# if defined(__GNUC__) && defined(__GNUC_MINOR__)
+#  define SIMULATE_ID "GNU"
+#  define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+#  define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+#  if defined(__GNUC_PATCHLEVEL__)
+#   define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+#  endif
+# endif
+
+#elif defined(__GNUC__)
+# define COMPILER_ID "GNU"
+# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
+# if defined(__GNUC_MINOR__)
+#  define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
+# endif
+# if defined(__GNUC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+# endif
+
+#elif defined(_MSC_VER)
+# define COMPILER_ID "MSVC"
+  /* _MSC_VER = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
+# if defined(_MSC_FULL_VER)
+#  if _MSC_VER >= 1400
+    /* _MSC_FULL_VER = VVRRPPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
+#  else
+    /* _MSC_FULL_VER = VVRRPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
+#  endif
+# endif
+# if defined(_MSC_BUILD)
+#  define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
+# endif
+
+#elif defined(_ADI_COMPILER)
+# define COMPILER_ID "ADSP"
+#if defined(__VERSIONNUM__)
+  /* __VERSIONNUM__ = 0xVVRRPPTT */
+#  define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
+#  define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
+#  define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
+#  define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
+#endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# define COMPILER_ID "IAR"
+# if defined(__VER__) && defined(__ICCARM__)
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
+#  define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
+#  define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
+#  define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
+#  define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# endif
+
+#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
+# define COMPILER_ID "SDCC"
+# if defined(__SDCC_VERSION_MAJOR)
+#  define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
+#  define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
+#  define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
+# else
+  /* SDCC = VRP */
+#  define COMPILER_VERSION_MAJOR DEC(SDCC/100)
+#  define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
+#  define COMPILER_VERSION_PATCH DEC(SDCC    % 10)
+# endif
+
+
+/* These compilers are either not known or too old to define an
+  identification macro.  Try to identify the platform and guess that
+  it is the native compiler.  */
+#elif defined(__hpux) || defined(__hpua)
+# define COMPILER_ID "HP"
+
+#else /* unknown compiler */
+# define COMPILER_ID ""
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
+#ifdef SIMULATE_ID
+char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
+#endif
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+#ifdef __QNXNTO__
+char const* qnxnto = "INFO" ":" "qnxnto[]";
+#endif
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+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
+#endif
+
+#define STRINGIFY_HELPER(X) #X
+#define STRINGIFY(X) STRINGIFY_HELPER(X)
+
+/* Identify known platforms by name.  */
+#if defined(__linux) || defined(__linux__) || defined(linux)
+# define PLATFORM_ID "Linux"
+
+#elif defined(__MSYS__)
+# define PLATFORM_ID "MSYS"
+
+#elif defined(__CYGWIN__)
+# define PLATFORM_ID "Cygwin"
+
+#elif defined(__MINGW32__)
+# define PLATFORM_ID "MinGW"
+
+#elif defined(__APPLE__)
+# define PLATFORM_ID "Darwin"
+
+#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
+# define PLATFORM_ID "Windows"
+
+#elif defined(__FreeBSD__) || defined(__FreeBSD)
+# define PLATFORM_ID "FreeBSD"
+
+#elif defined(__NetBSD__) || defined(__NetBSD)
+# define PLATFORM_ID "NetBSD"
+
+#elif defined(__OpenBSD__) || defined(__OPENBSD)
+# define PLATFORM_ID "OpenBSD"
+
+#elif defined(__sun) || defined(sun)
+# define PLATFORM_ID "SunOS"
+
+#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
+# define PLATFORM_ID "AIX"
+
+#elif defined(__hpux) || defined(__hpux__)
+# define PLATFORM_ID "HP-UX"
+
+#elif defined(__HAIKU__)
+# define PLATFORM_ID "Haiku"
+
+#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
+# define PLATFORM_ID "BeOS"
+
+#elif defined(__QNX__) || defined(__QNXNTO__)
+# define PLATFORM_ID "QNX"
+
+#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
+# define PLATFORM_ID "Tru64"
+
+#elif defined(__riscos) || defined(__riscos__)
+# define PLATFORM_ID "RISCos"
+
+#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
+# define PLATFORM_ID "SINIX"
+
+#elif defined(__UNIX_SV__)
+# define PLATFORM_ID "UNIX_SV"
+
+#elif defined(__bsdos__)
+# define PLATFORM_ID "BSDOS"
+
+#elif defined(_MPRAS) || defined(MPRAS)
+# define PLATFORM_ID "MP-RAS"
+
+#elif defined(__osf) || defined(__osf__)
+# define PLATFORM_ID "OSF1"
+
+#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
+# define PLATFORM_ID "SCO_SV"
+
+#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
+# define PLATFORM_ID "ULTRIX"
+
+#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
+# define PLATFORM_ID "Xenix"
+
+#elif defined(__WATCOMC__)
+# if defined(__LINUX__)
+#  define PLATFORM_ID "Linux"
+
+# elif defined(__DOS__)
+#  define PLATFORM_ID "DOS"
+
+# elif defined(__OS2__)
+#  define PLATFORM_ID "OS2"
+
+# elif defined(__WINDOWS__)
+#  define PLATFORM_ID "Windows3x"
+
+# elif defined(__VXWORKS__)
+#  define PLATFORM_ID "VxWorks"
+
+# else /* unknown platform */
+#  define PLATFORM_ID
+# endif
+
+#elif defined(__INTEGRITY)
+# if defined(INT_178B)
+#  define PLATFORM_ID "Integrity178"
+
+# else /* regular Integrity */
+#  define PLATFORM_ID "Integrity"
+# endif
+
+# elif defined(_ADI_COMPILER)
+#  define PLATFORM_ID "ADSP"
+
+#else /* unknown platform */
+# define PLATFORM_ID
+
+#endif
+
+/* For windows compilers MSVC and Intel we can determine
+   the architecture of the compiler being used.  This is because
+   the compilers do not have flags that can change the architecture,
+   but rather depend on which compiler is being used
+*/
+#if defined(_WIN32) && defined(_MSC_VER)
+# if defined(_M_IA64)
+#  define ARCHITECTURE_ID "IA64"
+
+# elif defined(_M_ARM64EC)
+#  define ARCHITECTURE_ID "ARM64EC"
+
+# elif defined(_M_X64) || defined(_M_AMD64)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# elif defined(_M_ARM64)
+#  define ARCHITECTURE_ID "ARM64"
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+# elif defined(_M_ARM)
+#  if _M_ARM == 4
+#   define ARCHITECTURE_ID "ARMV4I"
+#  elif _M_ARM == 5
+#   define ARCHITECTURE_ID "ARMV5I"
+#  else
+#   define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
+#  endif
+
+# elif defined(_M_MIPS)
+#  define ARCHITECTURE_ID "MIPS"
+
+# elif defined(_M_SH)
+#  define ARCHITECTURE_ID "SHx"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__WATCOMC__)
+# if defined(_M_I86)
+#  define ARCHITECTURE_ID "I86"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# if defined(__ICCARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__ICCRX__)
+#  define ARCHITECTURE_ID "RX"
+
+# elif defined(__ICCRH850__)
+#  define ARCHITECTURE_ID "RH850"
+
+# elif defined(__ICCRL78__)
+#  define ARCHITECTURE_ID "RL78"
+
+# elif defined(__ICCRISCV__)
+#  define ARCHITECTURE_ID "RISCV"
+
+# elif defined(__ICCAVR__)
+#  define ARCHITECTURE_ID "AVR"
+
+# elif defined(__ICC430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__ICCV850__)
+#  define ARCHITECTURE_ID "V850"
+
+# elif defined(__ICC8051__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__ICCSTM8__)
+#  define ARCHITECTURE_ID "STM8"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__ghs__)
+# if defined(__PPC64__)
+#  define ARCHITECTURE_ID "PPC64"
+
+# elif defined(__ppc__)
+#  define ARCHITECTURE_ID "PPC"
+
+# elif defined(__ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__x86_64__)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(__i386__)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__TI_COMPILER_VERSION__)
+# if defined(__TI_ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__MSP430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__TMS320C28XX__)
+#  define ARCHITECTURE_ID "TMS320C28x"
+
+# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
+#  define ARCHITECTURE_ID "TMS320C6x"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+# elif defined(__ADSPSHARC__)
+#  define ARCHITECTURE_ID "SHARC"
+
+# elif defined(__ADSPBLACKFIN__)
+#  define ARCHITECTURE_ID "Blackfin"
+
+#elif defined(__TASKING__)
+
+# if defined(__CTC__) || defined(__CPTC__)
+#  define ARCHITECTURE_ID "TriCore"
+
+# elif defined(__CMCS__)
+#  define ARCHITECTURE_ID "MCS"
+
+# elif defined(__CARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__CARC__)
+#  define ARCHITECTURE_ID "ARC"
+
+# elif defined(__C51__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__CPCP__)
+#  define ARCHITECTURE_ID "PCP"
+
+# else
+#  define ARCHITECTURE_ID ""
+# endif
+
+#else
+#  define ARCHITECTURE_ID
+#endif
+
+/* Convert integer to decimal digit literals.  */
+#define DEC(n)                   \
+  ('0' + (((n) / 10000000)%10)), \
+  ('0' + (((n) / 1000000)%10)),  \
+  ('0' + (((n) / 100000)%10)),   \
+  ('0' + (((n) / 10000)%10)),    \
+  ('0' + (((n) / 1000)%10)),     \
+  ('0' + (((n) / 100)%10)),      \
+  ('0' + (((n) / 10)%10)),       \
+  ('0' +  ((n) % 10))
+
+/* Convert integer to hex digit literals.  */
+#define HEX(n)             \
+  ('0' + ((n)>>28 & 0xF)), \
+  ('0' + ((n)>>24 & 0xF)), \
+  ('0' + ((n)>>20 & 0xF)), \
+  ('0' + ((n)>>16 & 0xF)), \
+  ('0' + ((n)>>12 & 0xF)), \
+  ('0' + ((n)>>8  & 0xF)), \
+  ('0' + ((n)>>4  & 0xF)), \
+  ('0' + ((n)     & 0xF))
+
+/* Construct a string literal encoding the version number. */
+#ifdef COMPILER_VERSION
+char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
+
+/* Construct a string literal encoding the version number components. */
+#elif defined(COMPILER_VERSION_MAJOR)
+char const info_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
+  COMPILER_VERSION_MAJOR,
+# ifdef COMPILER_VERSION_MINOR
+  '.', COMPILER_VERSION_MINOR,
+#  ifdef COMPILER_VERSION_PATCH
+   '.', COMPILER_VERSION_PATCH,
+#   ifdef COMPILER_VERSION_TWEAK
+    '.', COMPILER_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct a string literal encoding the internal version number. */
+#ifdef COMPILER_VERSION_INTERNAL
+char const info_version_internal[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
+  'i','n','t','e','r','n','a','l','[',
+  COMPILER_VERSION_INTERNAL,']','\0'};
+#elif defined(COMPILER_VERSION_INTERNAL_STR)
+char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
+#endif
+
+/* Construct a string literal encoding the version number components. */
+#ifdef SIMULATE_VERSION_MAJOR
+char const info_simulate_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
+  SIMULATE_VERSION_MAJOR,
+# ifdef SIMULATE_VERSION_MINOR
+  '.', SIMULATE_VERSION_MINOR,
+#  ifdef SIMULATE_VERSION_PATCH
+   '.', SIMULATE_VERSION_PATCH,
+#   ifdef SIMULATE_VERSION_TWEAK
+    '.', SIMULATE_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
+char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
+
+
+
+#if !defined(__STDC__) && !defined(__clang__)
+# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__)
+#  define C_VERSION "90"
+# else
+#  define C_VERSION
+# endif
+#elif __STDC_VERSION__ > 201710L
+# define C_VERSION "23"
+#elif __STDC_VERSION__ >= 201710L
+# define C_VERSION "17"
+#elif __STDC_VERSION__ >= 201000L
+# define C_VERSION "11"
+#elif __STDC_VERSION__ >= 199901L
+# define C_VERSION "99"
+#else
+# define C_VERSION "90"
+#endif
+const char* info_language_standard_default =
+  "INFO" ":" "standard_default[" C_VERSION "]";
+
+const char* info_language_extensions_default = "INFO" ":" "extensions_default["
+#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) ||           \
+     defined(__TI_COMPILER_VERSION__)) &&                                     \
+  !defined(__STRICT_ANSI__)
+  "ON"
+#else
+  "OFF"
+#endif
+"]";
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef ID_VOID_MAIN
+void main() {}
+#else
+# if defined(__CLASSIC_C__)
+int main(argc, argv) int argc; char *argv[];
+# else
+int main(int argc, char* argv[])
+# endif
+{
+  int require = 0;
+  require += info_compiler[argc];
+  require += info_platform[argc];
+  require += info_arch[argc];
+#ifdef COMPILER_VERSION_MAJOR
+  require += info_version[argc];
+#endif
+#ifdef COMPILER_VERSION_INTERNAL
+  require += info_version_internal[argc];
+#endif
+#ifdef SIMULATE_ID
+  require += info_simulate[argc];
+#endif
+#ifdef SIMULATE_VERSION_MAJOR
+  require += info_simulate_version[argc];
+#endif
+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+  require += info_cray[argc];
+#endif
+  require += info_language_standard_default[argc];
+  require += info_language_extensions_default[argc];
+  (void)argv;
+  return require;
+}
+#endif

sources_1/new/MMCM/cmake-build-debug/CMakeFiles/TargetDirectories.txt

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+C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug/CMakeFiles/edit_cache.dir
+C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug/CMakeFiles/rebuild_cache.dir

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+-- The C compiler identification is GNU 11.2.0
+-- Detecting C compiler ABI info
+-- Detecting C compiler ABI info - done
+-- Check for working C compiler: C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc.exe - skipped
+-- Detecting C compile features
+-- Detecting C compile features - done
+-- Configuring done
+CMake Error: CMake can not determine linker language for target: MMCM
+-- Generating done
+CMake Generate step failed.  Build files cannot be regenerated correctly.

sources_1/new/MMCM/cmake-build-debug/CMakeFiles/clion-environment.txt

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sources_1/new/MMCM/cmake-build-debug/CMakeFiles/cmake.check_cache

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sources_1/new/MMCM/cmake-build-debug/cmake_install.cmake

@@ -0,0 +1,49 @@
+# Install script for directory: C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM
+
+# Set the install prefix
+if(NOT DEFINED CMAKE_INSTALL_PREFIX)
+  set(CMAKE_INSTALL_PREFIX "C:/Program Files (x86)/MMCM")
+endif()
+string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}")
+
+# Set the install configuration name.
+if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME)
+  if(BUILD_TYPE)
+    string(REGEX REPLACE "^[^A-Za-z0-9_]+" ""
+           CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}")
+  else()
+    set(CMAKE_INSTALL_CONFIG_NAME "Debug")
+  endif()
+  message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"")
+endif()
+
+# Set the component getting installed.
+if(NOT CMAKE_INSTALL_COMPONENT)
+  if(COMPONENT)
+    message(STATUS "Install component: \"${COMPONENT}\"")
+    set(CMAKE_INSTALL_COMPONENT "${COMPONENT}")
+  else()
+    set(CMAKE_INSTALL_COMPONENT)
+  endif()
+endif()
+
+# Is this installation the result of a crosscompile?
+if(NOT DEFINED CMAKE_CROSSCOMPILING)
+  set(CMAKE_CROSSCOMPILING "FALSE")
+endif()
+
+# Set default install directory permissions.
+if(NOT DEFINED CMAKE_OBJDUMP)
+  set(CMAKE_OBJDUMP "C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/objdump.exe")
+endif()
+
+if(CMAKE_INSTALL_COMPONENT)
+  set(CMAKE_INSTALL_MANIFEST "install_manifest_${CMAKE_INSTALL_COMPONENT}.txt")
+else()
+  set(CMAKE_INSTALL_MANIFEST "install_manifest.txt")
+endif()
+
+string(REPLACE ";" "\n" CMAKE_INSTALL_MANIFEST_CONTENT
+       "${CMAKE_INSTALL_MANIFEST_FILES}")
+file(WRITE "C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug/${CMAKE_INSTALL_MANIFEST}"
+     "${CMAKE_INSTALL_MANIFEST_CONTENT}")

sources_1/new/MMCM/mmcme2_drp.v

@@ -139,7 +139,7 @@ module mmcme2_drp
         //    _FRAC_EN: This indicates fractional divide has been enabled. If 1
         //          then the fractional divide algorithm will be used to calculate
         //          register settings. If 0 then default calculation to be used.
-        parameter S1_CLKFBOUT_MULT          = 5,
+        parameter S1_CLKFBOUT_MULT          = 13,
         parameter S1_CLKFBOUT_PHASE         = 0,
         parameter S1_CLKFBOUT_FRAC          = 125,
         parameter S1_CLKFBOUT_FRAC_EN       = 1,
@@ -168,7 +168,7 @@ module mmcme2_drp
         //          a duty cycle of .24567 was desired the input would be
         //          24567.
         //
-        parameter S1_CLKOUT0_DIVIDE         = 1,
+        parameter S1_CLKOUT0_DIVIDE         = 2,
         parameter S1_CLKOUT0_PHASE          = 0,
         parameter S1_CLKOUT0_DUTY           = 50000,
         parameter S1_CLKOUT0_FRAC          = 125,
@@ -287,6 +287,18 @@ module mmcme2_drp
         input             SCLK,
         input             RST,
         output reg        SRDY,
+
+
+         // input [7:0]     ClkDiv1_i,
+         // input [7:0]     ClkDiv2_i,
+         // input [7:0]     ClkDiv3_i,
+         // input [7:0]     ClkDiv4_i,
+         // input [7:0]     ClkDiv5_i,
+         // input [7:0]     ClkDiv6_i,
+         // input [7:0]     ClkDiv7_i,
+
+
+
         //
         // These signals are to be connected to the MMCM_ADV by port name.
         // Their use matches the MMCM port description in the Device User Guide.
@@ -306,6 +318,12 @@ module mmcme2_drp
     //
     wire        IntLocked;
     wire        IntRstMmcm;
+    wire  [15:0] clkVal; 
+    wire  [15:0] fracPart;
+    assign clkVal = 16'h208;
+   
+
+
     //
     // 100 ps delay for behavioral simulations
     localparam  TCQ = 100;
@@ -522,11 +540,11 @@ module mmcme2_drp
 
        // Store CLKOUT0 divide and phase
        rom[1]  = (S1_CLKOUT0_FRAC_EN == 0) ?
-                         {7'h09, 16'h8000, S1_CLKOUT0[31:16]}:
-                         {7'h09, 16'h8000, S1_CLKOUT0_FRAC_CALC[31:16]};
+                         {7'h09, 16'h8000, 16'h0480}:
+                         {7'h09, 16'h8000, 16'h0480};
        rom[2]  = (S1_CLKOUT0_FRAC_EN == 0) ?
-                         {7'h08, 16'h1000, S1_CLKOUT0[15:0]}:
-                         {7'h08, 16'h1000, S1_CLKOUT0_FRAC_CALC[15:0]};
+                         {7'h08, 16'h1000, clkVal}:
+                         {7'h08, 16'h1000, clkVal};
 
        // Store CLKOUT1 divide and phase
        rom[3]  = {7'h0A, 16'h1000, S1_CLKOUT1[15:0]};
@@ -589,11 +607,11 @@ module mmcme2_drp
 
        // Store CLKOUT0 divide and phase
        rom[24] = (S2_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h09, 16'h8000, S2_CLKOUT0[31:16]}:
-                 {7'h09, 16'h8000, S2_CLKOUT0_FRAC_CALC[31:16]};
+                 {7'h09, 16'h8000, 16'h0480}:
+                 {7'h09, 16'h8000, 16'h0480};
        rom[25] = (S2_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h08, 16'h1000, S2_CLKOUT0[15:0]}:
-                 {7'h08, 16'h1000, S2_CLKOUT0_FRAC_CALC[15:0]};
+                 {7'h08, 16'h1000, clkVal}:
+                 {7'h08, 16'h1000, clkVal};
 
        // Store CLKOUT1 divide and phase
        rom[26] = {7'h0A, 16'h1000, S2_CLKOUT1[15:0]};
@@ -683,7 +701,7 @@ module mmcme2_drp
     //    each state takes to reconfigure.
     // STATE_COUNT_CONST is used to reset the counters and should match the
     //    number of registers necessary to reconfigure each state.
-    localparam STATE_COUNT_CONST  = 23;
+    localparam STATE_COUNT_CONST  = 4;
     reg [4:0] state_count         = STATE_COUNT_CONST;
     reg [4:0] next_state_count    = STATE_COUNT_CONST;
 

sources_1/new/MMCM/mmcme2_drp_func.h

@@ -696,7 +696,7 @@ endfunction
 //
 function [37:0] mmcm_frac_count_calc
    (
-      input [7:0] divide, // Max divide is 128
+      input  [7:0] divide, // Max divide is 128
       input signed [31:0] phase,
       input [31:0] duty_cycle, // Multiplied by 1,000
       input [9:0] frac // Multiplied by 1000

sources_1/new/MMCM/top_mmcme2.v

@@ -90,6 +90,13 @@ module top_mmcme2
         input    STATE,
         input    RST,
         input    CLKIN,
+        input   [7:0] ClkDiv1_i,
+        input   [7:0] ClkDiv2_i,
+        input   [7:0] ClkDiv3_i,
+        input   [7:0] ClkDiv4_i,
+        input   [7:0] ClkDiv5_i,
+        input   [7:0] ClkDiv6_i,
+        input   [7:0] ClkDiv7_i,
         output   SRDY,
  		output 	 LOCKED_OUT,
         output   CLK0OUT,
@@ -179,10 +186,10 @@ ODDR ODDR_CLK6 (.Q(CLK6OUT), .C(clk6_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0),
 MMCME2_ADV #(
    .BANDWIDTH           ("OPTIMIZED"),
    .DIVCLK_DIVIDE       (1),
-   .CLKFBOUT_MULT_F     (6),
+   .CLKFBOUT_MULT_F     (13),
    .CLKFBOUT_PHASE      (0.0),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
-   .CLKIN1_PERIOD       (10.000),
+   .CLKIN1_PERIOD       (8.130081300813),
    .REF_JITTER1         (0.010),
    .CLKIN2_PERIOD       (10.000),
    .REF_JITTER2         (0.010),
@@ -222,6 +229,14 @@ MMCME2_ADV #(
    .CLKFBOUTB           (),
    .CLKFBSTOPPED        (),
    .CLKINSTOPPED        (),
+//    .ClkDiv1_i           (ClkDiv1_i),
+//    .ClkDiv2_i           (ClkDiv2_i),
+//    .ClkDiv3_i           (ClkDiv3_i),
+//    .ClkDiv4_i           (ClkDiv4_i),
+//    .ClkDiv5_i           (ClkDiv5_i),
+//    .ClkDiv6_i           (ClkDiv6_i),
+//    .ClkDiv7_i           (ClkDiv7_i),
+
    .CLKOUT0             (clk0_bufgin),
    .CLKOUT0B            (),
    .CLKOUT1             (clk1_bufgin),
@@ -276,7 +291,7 @@ mmcme2_drp #(
     // State 1 Parameters - These are for the first reconfiguration state.
     //***********************************************************************
     // Set the multiply to 6.0 with 0 deg phase offset, optimized bandwidth, input divide of 1
-    .S1_CLKFBOUT_MULT(6),
+    .S1_CLKFBOUT_MULT(13),
     .S1_CLKFBOUT_PHASE(000_000),
     .S1_CLKFBOUT_FRAC(000),
     .S1_CLKFBOUT_FRAC_EN(0),
@@ -315,7 +330,7 @@ mmcme2_drp #(
     //***********************************************************************
     // State 2 Parameters - These are for the second reconfiguration state.
     //***********************************************************************
-    .S2_CLKFBOUT_MULT(7),
+    .S2_CLKFBOUT_MULT(13),
     .S2_CLKFBOUT_PHASE(000_000),
     .S2_CLKFBOUT_FRAC(000),
     .S2_CLKFBOUT_FRAC_EN(0),

sources_1/new/MMCM/top_mmcme2_tb.v

@@ -86,7 +86,7 @@ module top_tb  ();
     );
 //-------------------------------------------------------------------------------------------
     localparam one_ns = 1000;
-    localparam clock_period = 10;
+    localparam clock_period = 8.13;
     parameter [1:0]    STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;
     reg [1:0] SM = STARTUP ;
 
@@ -108,7 +108,7 @@ always @ (posedge CLKin)
                             begin
                                 #(1 * clock_period * one_ns) SSTEP= 1'b1;
                                 #(1 * clock_period * one_ns) SSTEP=1'b0;
-                                #(100 * clock_period * one_ns) SM = STATE1 ;
+                                #(2000 * clock_period * one_ns) SM = STATE1 ;
                                 STATE=1'b1;
                             end
                     end

sources_1/new/Mux/DataMuxer.v

@@ -15,20 +15,20 @@ module SmcDataMux
 	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
 	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
 	
-	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
-	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
-	parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
-	parameter	Fifo1WriteMsbAddr	=	12'h50+12'h26,
-	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'h24,
-	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'h26,
-	parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
-	parameter	Fifo3WriteMsbAddr	=	12'h140+12'h26,
-	parameter	Fifo4WriteLsbAddr	=	12'h190+12'h24,
-	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
-	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
-	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h26,
-	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h24,
-	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
+	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
+	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
+	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
+	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
+	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
+	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
+	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
+	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
+	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
+	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
+	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
+	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
+	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
+	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26
 )
 (
     input	Clk_i,
@@ -77,7 +77,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 		ToRegMapAddr_o	<=	12'h0;
 		
 		ToFifoVal_o		<=	7'h0;
-		ToFifoData_o	<=	16'h0;
+		ToFifoData_o	<=	0;
 	end	else	begin
 		if	(requestToFifo)	begin	
 			case(SmcAddr_i)	
@@ -89,6 +89,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[0]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo1WriteLsbAddr:	begin
 									ToFifoVal_o[1]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
@@ -97,12 +98,17 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[1]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo2WriteLsbAddr:	begin
 									ToFifoVal_o[2]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
 								end
 				Fifo2WriteMsbAddr:	begin
 									ToFifoVal_o[2]	<=	SmcVal_i;
+									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+								end
+								
+				Fifo3WriteLsbAddr:	begin
 									ToFifoVal_o[3]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
 								end
@@ -110,6 +116,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[3]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo4WriteLsbAddr:	begin
 									ToFifoVal_o[4]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
@@ -118,12 +125,17 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoVal_o[4]	<=	SmcVal_i;
 									ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
 								end
+								
 				Fifo5WriteLsbAddr:	begin
 									ToFifoVal_o[5]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
 								end
 				Fifo5WriteMsbAddr:	begin
 									ToFifoVal_o[5]	<=	SmcVal_i;
+									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+								end
+								
+				Fifo6WriteLsbAddr:	begin
 									ToFifoVal_o[6]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
 								end

sources_1/new/S5443_3Top.v

@@ -181,7 +181,7 @@ wire	[AddrRegWidth-1:0]	smcAddr;
 wire	[CmdRegWidth/2-1:0]	smcData;
 wire	smcVal;
 //RxFifo 
-wire [0:23] dataToRxFifo [SpiNum-1:0];
+wire [0:31] dataToRxFifo [SpiNum-1:0];
 wire [0:7] addrToRxFifo [SpiNum-1:0];
 wire [SpiNum-1:0] valToRxFifo;
 wire [SpiNum-1:0] valToTxFifoRead;
@@ -446,6 +446,8 @@ assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
 
 assign dataFromRxFifoW =  dataFromRxFifoR;
 
+assign Data_i = (!SmcAre_i)?((toRegMapAddr)? ansData: dataFromRxFifoW):16'bz;
+
 //================================================================================
 //  CODING
 //================================================================================	
@@ -455,27 +457,48 @@ always @(*) begin
         dataFromRxFifoR = 16'b0;
     end
     else begin 
-        case (Ss_o)  
-            7'b0000001: begin 
-                dataFromRxFifoR = dataFromRxFifo[0];
+        case (smcAddr)  
+            12'h1c: begin 
+                dataFromRxFifoR = dataFromRxFifo[0][15:0];
+            end
+            12'h1e: begin
+                dataFromRxFifoR = dataFromRxFifo[0][31:16];
+            end 
+            12'h6c: begin 
+                dataFromRxFifoR = dataFromRxFifo[1][15:0];
+            end
+            12'h6e: begin 
+                dataFromRxFifoR = dataFromRxFifo[1][31:16];
+            end
+            12'h10c: begin 
+                dataFromRxFifoR = dataFromRxFifo[2][15:0];
+            end
+            12'h10e: begin 
+                dataFromRxFifoR = dataFromRxFifo[2][31:16];
+            end
+            12'h15c: begin 
+                dataFromRxFifoR = dataFromRxFifo[3][15:0];
+            end
+            12'h15e: begin 
+                dataFromRxFifoR = dataFromRxFifo[3][31:16];
             end
-            7'b0000010: begin 
-                dataFromRxFifoR = dataFromRxFifo[1];
+            12'h1ac: begin 
+                dataFromRxFifoR = dataFromRxFifo[4][15:0];
             end
-            7'b0000011: begin 
-                dataFromRxFifoR = dataFromRxFifo[2];
+            12'h1ae: begin 
+                dataFromRxFifoR = dataFromRxFifo[4][31:16];
             end
-            7'b0000100: begin 
-                dataFromRxFifoR = dataFromRxFifo[3];
+            12'h1fc: begin 
+                dataFromRxFifoR = dataFromRxFifo[5][15:0];
             end
-            7'b0000101: begin 
-                dataFromRxFifoR = dataFromRxFifo[4];
+            12'h1fe: begin 
+                dataFromRxFifoR = dataFromRxFifo[5][31:16];
             end
-            7'b0000110: begin 
-                dataFromRxFifoR = dataFromRxFifo[5];
+            12'h24c: begin 
+                dataFromRxFifoR = dataFromRxFifo[6][15:0];
             end
-            7'b0000111: begin 
-                dataFromRxFifoR = dataFromRxFifo[6];
+            12'h24e: begin 
+                dataFromRxFifoR = dataFromRxFifo[6][31:16];
             end
             default: dataFromRxFifoR = 16'b0;
         endcase
@@ -615,7 +638,7 @@ MmcmWrapper MainMmcm
 	.Clk_i		(gclk),
 	.Rst_i		(initRst),
 
-	.SpiCLk_o	(spiClkBus)
+	.SpiClk_o	(spiClkBus)
 );
 
 
@@ -651,7 +674,7 @@ generate
 
 			
 			.ToSpiVal_o		(toSpiVal[i]),
-            .DataFromRxFifo_o (dataToRxFifo[i]),
+            .DataFromRxFifo_o (dataFromRxFifo[i]),
 			.ToSpiData_o	(toSpiData[i])
 		);
 

sources_1/new/SpiR/SPIm.v

@@ -30,11 +30,12 @@ reg startR;
 reg [31:0] trCnt;
 reg valReg;
 reg valToRxFifo1;
-reg [2:0] ssCnt;
+reg [5:0] ssCnt;
 reg Ss;
 reg SSr;
+reg SSR;
 reg [31:0] mosiReg0;
-reg [3:0] ssNum;
+reg [5:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;
 
@@ -105,7 +106,7 @@ always @(posedge Clk_i) begin
     end
     else begin
         if (SELST_i) begin 
-            if (Ss && !SSr) begin 
+            if (SsPol && !SSr) begin 
                 stopFlag <= 1'b1;
             end
             else if ( delayCnt == Stop_i) begin 
@@ -113,7 +114,7 @@ always @(posedge Clk_i) begin
             end
         end
         else begin 
-            if (!Ss && SSr) begin 
+            if (!SsPol && SSr) begin 
                 stopFlag <= 1'b1;
             end
             else if (delayCnt == Stop_i) begin 
@@ -126,83 +127,164 @@ end
 
 
 
-always @(*) begin 
-    if (PulsePol_i) begin 
-        if (CPHA_i) begin
-            if (LEAD_i == 0) begin 
-            if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                Sck_o = ~(~Clk_i);
-            end
-            else begin 
-                Sck_o = 1'b0;
-                end
-            end
-            else begin 
-                if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+always @(*) begin
+    if (SELST_i) begin 
+        if (PulsePol_i) begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                     Sck_o = ~(~Clk_i);
                 end
                 else begin 
                     Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-        end
-        else begin
-            if (LEAD_i == 0) begin 
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(Clk_i);
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-            else begin 
-                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(Clk_i);
+        end
+        else begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin  
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
+                end
+            end 
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
         end
     end
     else begin 
-        if (CPHA_i) begin
-            if (LEAD_i == 0) begin  
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(Clk_i);
+          if (PulsePol_i) begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin 
+                if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(~Clk_i);
                 end
                 else begin 
                     Sck_o = 1'b0;
+                    end
+                end
+                else begin 
+                    if (SsPol && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-            else begin 
-                if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(Clk_i);
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (SsPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
-        end 
-        else begin
-            if (LEAD_i == 0) begin 
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                    Sck_o = ~(~Clk_i);
+        end
+        else begin 
+            if (CPHA_i) begin
+                if (LEAD_i == 0) begin  
+                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (SsPol && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
-            end
-            else begin 
-                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                    Sck_o = ~(~Clk_i);
+            end 
+            else begin
+                if (LEAD_i == 0) begin 
+                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
                 else begin 
-                    Sck_o = 1'b0;
+                    if (SsPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                        Sck_o = ~(~Clk_i);
+                    end
+                    else begin 
+                        Sck_o = 1'b0;
+                    end
                 end
             end
         end
     end
+        
 end
 
 
@@ -211,46 +293,82 @@ always @(*) begin
         Mosi0_o = 1'b0;
     end
     else begin
-        if (!EndianSel_i) begin 
-            case (WidthSel_i)  
-                0 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                end
-                1 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
-                end
-                2 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
-                end
-                3 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
-                end
-            endcase
+        if (SELST_i) begin 
+            if (!EndianSel_i) begin 
+                case (WidthSel_i)  
+                    0 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                    end
+                endcase
+            end
+            else begin 
+                case (WidthSel_i)  
+                    0 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                endcase
+            end
         end
         else begin 
-            case (WidthSel_i)  
-                0 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                end
-                1 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                end
-                2 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                end
-                3 : begin
-                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                end
-            endcase
+            if (!EndianSel_i) begin 
+                case (WidthSel_i)  
+                    0 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                    end
+                endcase
+            end
+            else begin 
+                case (WidthSel_i)  
+                    0 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    1 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    2 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                    3 : begin
+                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                    end
+                endcase
+            end
         end
     end
 end
 
 
 
-
 always @(posedge Clk_i) begin
-    SSr <= Ss;
+    SSr <= SsPol;
+    SSR <= Ss;
 end
 
 
@@ -348,7 +466,7 @@ always @(negedge Clk_i) begin
     end
     else begin
         if (!EndianSel_i) begin 
-            if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            if (!SSR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                 mosiReg0 <= mosiReg0 << 1;
             end
             else begin 
@@ -356,7 +474,7 @@ always @(negedge Clk_i) begin
             end
         end
         else begin 
-            if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+            if (!SSR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                 mosiReg0 <= mosiReg0 >> 1;
             end
             else begin 

sources_1/new/SpiR/SPIm_tb.v

@@ -0,0 +1,146 @@
+`timescale 1ns/1ps
+
+module tb_SPIm;
+
+    // Parameters
+    parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    reg Clk_i;
+    reg Rst_i;
+    reg Start_i;
+    reg CPHA_i;
+    reg [31:0] SPIdata;
+	reg SpiDataVal_i;
+    reg SELST_i;
+    reg [1:0] WidthSel_i;
+    reg LAG_i;
+    reg LEAD_i;
+    reg EndianSel_i;
+    reg [5:0] Stop_i;
+    reg PulsePol_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    // SPIm SPIm_inst (
+    //     .Clk_i(Clk_i), 
+    //     .Rst_i(Rst_i), 
+    //     .Start_i(Start_i), 
+    //     .CPHA_i(CPHA_i), 
+    //     .SPIdata(SPIdata),
+    //     .SpiDataVal_i(SpiDataVal_i),
+    //     .SELST_i(SELST_i),
+    //     .WidthSel_i(WidthSel_i),
+    //     .LAG_i(LAG_i),
+    //     .LEAD_i(LEAD_i),
+    //     .EndianSel_i(EndianSel_i),
+    //     .Stop_i(Stop_i),
+    //     .PulsePol_i(PulsePol_i),
+    //     .Mosi0_o(Mosi0_o),
+    //     .Sck_o(Sck_o),
+    //     .Ss_o(Ss_o),
+    //     .Val_o(Val_o)
+    // );
+
+
+    // SPIs SPIs_inst (
+    //     .Clk_i(Clk_i), 
+    //     .Rst_i(Rst_i), 
+    //     .Sck_i(Sck_o), 
+    //     .Ss_i(Ss_o), 
+    //     .Mosi0_i(Mosi0_o), 
+    //     .WidthSel_i(WidthSel_i), 
+    //     .EndianSel_i(EndianSel_i),
+    //     .SELST_i(SELST_i), 
+    //     .Data_o(), 
+    //     .Addr_o(), 
+    //     .DataToRxFifo_o(), 
+    //     .Val_o()
+    // );
+
+
+    QuadSPIm QuadSPIm_inst (
+        .Clk_i(Clk_i),
+        .Rst_i(Rst_i),
+        .Start_i(Start_i),
+        .CPHA_i(CPHA_i),
+        .SPIdata(SPIdata),
+        .SpiDataVal_i(SpiDataVal_i),
+        .SELST_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .LAG_i(LAG_i),
+        .LEAD_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_i(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .Sck_o(Sck_o),
+        .Ss_o(Ss_o),
+        .Val_o(Val_o)
+    );
+
+
+
+    QuadSPIs QuadSPIs_inst (
+        .Clk_i(Clk_i),
+        .Rst_i(Rst_i),
+        .Sck_i(Sck_o),
+        .Ss_i(Ss_o),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_i(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o),
+        .WidthSel_i(WidthSel_i),
+        .SELST_i(SELST_i),
+        .Data_o(),
+        .Addr_o(),
+        .DataToRxFifo_o(),
+        .Val_o()
+    );
+
+    // Clock generation
+    always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+
+    // Initial setup and test sequence
+    initial begin
+        // Initialize Inputs
+        Clk_i = 0;
+        Rst_i = 1;
+        Start_i = 0;
+        CPHA_i = 0;
+        SPIdata =  {1'h0, 7'h2a, 8'haa,8'h00,8'haa}; // Example SPI data
+		SpiDataVal_i = 0;
+        SELST_i = 1;//0:High, 1:Low
+        WidthSel_i = 3; // Full 32-bit width
+        LAG_i = 0;
+        LEAD_i = 0;
+        EndianSel_i = 1; // 0:MSB first, 1:lsb first
+        Stop_i = 6'd0;
+        PulsePol_i = 0;
+
+        // Reset the system
+        #(CLK_PERIOD*10) Rst_i = 0;
+        #(CLK_PERIOD*2) Start_i = 1; // Start SPI transaction
+
+    
+        #(CLK_PERIOD*100);
+
+        // EndianSel_i = 1; // LSB first
+        // SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa}; 
+        // #(CLK_PERIOD*2) Start_i = 0; 
+        // #(CLK_PERIOD) Start_i = 1;
+
+      
+    end
+
+endmodule

sources_1/new/SpiR/SPIs.v

@@ -6,6 +6,7 @@ module SPIs (
     input Ss_i,
     input Mosi0_i,
     input [1:0] WidthSel_i,
+    input EndianSel_i,
     input SELST_i,
    
 
@@ -110,20 +111,40 @@ always @(posedge Sck_i or posedge Rst_i) begin
         shiftReg<= 32'h0;
     end
     else begin
-        if (SELST_i) begin   
-            if (!Ss_i) begin 
-                shiftReg<= {shiftReg[30:0], Mosi0_i};
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin   
+                if (!Ss_i) begin 
+                    shiftReg<= {shiftReg[30:0], Mosi0_i};
+                end
+                else begin 
+                    shiftReg<= 32'h0;
+                end
             end
             else begin 
-                shiftReg<= 32'h0;
+                if (Ss_i) begin 
+                    shiftReg<= {shiftReg[30:0], Mosi0_i};
+                end
+                else begin 
+                    shiftReg<= 32'h0;
+                end
             end
         end
         else begin 
-            if (Ss_i) begin 
-                shiftReg<= {shiftReg[30:0], Mosi0_i};
+            if (SELST_i) begin   
+                if (!Ss_i) begin 
+                    shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                end
+                else begin 
+                    shiftReg<= 32'h0;
+                end
             end
             else begin 
-                shiftReg<= 32'h0;
+                if (Ss_i) begin 
+                    shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                end
+                else begin 
+                    shiftReg<= 32'h0;
+                end
             end
         end
     end