Переименованы модули в блоке генерации клоков

sources_1/ip/ClkDiv/ClkDiv.xci

@@ -6,7 +6,7 @@
   <spirit:version>1.0</spirit:version>
   <spirit:componentInstances>
     <spirit:componentInstance>
-      <spirit:instanceName>ClkDiv</spirit:instanceName>
+      <spirit:instanceName>MMCM</spirit:instanceName>
       <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -148,7 +148,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">99.93750</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
@@ -222,7 +222,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">29.98125</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">1</spirit:configurableElementValue>
@@ -435,7 +435,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1440.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">600.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
@@ -458,7 +458,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">85.478</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
@@ -512,7 +512,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">85.478</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">true</spirit:configurableElementValue>
@@ -536,7 +536,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
@@ -707,7 +707,7 @@
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../S5443_3.gen/sources_1/ip/ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../S5443_3.gen/sources_1/ip/MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
@@ -737,7 +737,6 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
@@ -764,7 +763,6 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_USED" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>

sources_1/new/MMCM/ClkGen.v

@@ -1,4 +1,4 @@
-module ClkGen (
+module ClkDivider (
   input Clk_i,
   input [3:0] ClkDiv_i,
   input Rst_i,
@@ -10,7 +10,6 @@ reg [16:0] cnt;
 reg clk;
 wire clk_o;
 
-
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         cnt <= 0;
@@ -27,10 +26,4 @@ end
 
 assign Clk_o = (cnt < ClkDiv_i/2) ? 1 : 0;
 
-
-
-
-
-
-
 endmodule

sources_1/new/MMCM/MmcmWrapper.v

@@ -1,5 +1,5 @@
 
-module MmcmWrapper 
+module ClkManager 
 #(
 	parameter	SpiNum	=	7,
    parameter   STAGES   =  3
@@ -45,8 +45,6 @@ wire [0:3] clkDivSync [SpiNum-1:0];
 wire [SpiNum-1:0] clkCh; 
 wire [SpiNum-1:0] spiClk;
 
-
-
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
@@ -98,38 +96,37 @@ wire [SpiNum-1:0] spiClk;
 
    generate
       for (i=0; i < SpiNum; i = i +1) begin : ClkGen
-         ClkGen ClkGen_inst (
+         ClkDivider ClkDivider (
             .Clk_i(clk1out),
             .ClkDiv_i(clkDivSync[i]),
             .Rst_i(Rst80_i),
             .Clk_o(clkMan[i])
          );
 
-         ClkDivSync #(
+         CmdSync #(
             .WIDTH(4),
             .STAGES(STAGES)
-         ) ClkDiv_Inst (
+         ) CmdSync (
             .ClkFast_i(Clk_i),
             .ClkSlow_i(clk1out),
             .ClkDiv_i(clkDiv[i]),
             .ClkDiv_o(clkDivSync[i])
-
          );
 
-         clkOutMMCM clkOutMMCM_inst (
+         MmcmClkMux MmcmClkMux (
             .Rst_i(Rst_i),
             .clkNum(clkNum[i]),
-            .clk0out(clk0out),
-            .clk1out(clk1out),
-            .clk2out(clk2out),
-            .clk3out(clk3out),
-            .clk4out(clk4out),
-            .clk5out(clk5out),
-            .clk6out(clk6out),
+            .Clk0_i(clk0out),
+            .Clk1_i(clk1out),
+            .Clk2_i(clk2out),
+            .Clk3_i(clk3out),
+            .Clk4_i(clk4out),
+            .Clk5_i(clk5out),
+            .Clk6_i(clk6out),
             .ClkOutMMCM_o(clkOutMMCM[i])
          );
    
-         ClkCh ClkCh_inst (
+         SpiClkMux SpiClkMux (
             .Rst_i(Rst_i),
             .clkCh(clkCh[i]),
             .clkOutMMCM(clkOutMMCM[i]),
@@ -139,7 +136,7 @@ wire [SpiNum-1:0] spiClk;
       end
    endgenerate
    
-   ClkDiv ClkDiv_inst
+   MMCM MMCM
     (
      // Clock out ports
      .clk_out1(clk0out),     //100 MHz
@@ -151,7 +148,7 @@ wire [SpiNum-1:0] spiClk;
      .clk_out7(clk6out),     // 30MHz 
      // Status and control signals
      .reset(Rst_i), // input reset
-     .locked(locked),       // output locked
+     .locked(locked),// output locked
     // Clock in ports
      .clk_in1(Clk_i));      // input clk_in1
    

sources_1/new/ClkManager/CmdSync.v

@@ -0,0 +1,34 @@
+module CmdSync #(
+    parameter WIDTH = 4,
+    parameter STAGES = 3
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] ClkDiv_i,
+
+    output [WIDTH-1:0] ClkDiv_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+//lauch registers 
+reg [WIDTH-1:0] clkDivReg;
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(posedge ClkFast_i) begin
+    clkDivReg <= ClkDiv_i;
+end
+
+always @(posedge ClkSlow_i) begin
+    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
+end
+
+endmodule

sources_1/new/ClkManager/MmcmClkMux.v

@@ -0,0 +1,51 @@
+module MmcmClkMux(
+input Rst_i,
+input [2:0]clkNum,
+input Clk0_i,
+input Clk1_i,
+input Clk2_i,
+input Clk3_i,
+input Clk4_i,
+input Clk5_i,
+input Clk6_i, 
+
+output   ClkOutMMCM_o
+
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg clkOutMMCMReg;
+
+wire clkOutMMCM;
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign clkOutMMCM = clkOutMMCMReg;
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(*) begin 
+    if (Rst_i) begin 
+        clkOutMMCMReg = 0;
+    end
+    else begin 
+        case (clkNum) 
+            0: clkOutMMCMReg = Clk0_i;
+            1: clkOutMMCMReg = Clk1_i;
+            2: clkOutMMCMReg = Clk2_i;
+            3: clkOutMMCMReg = Clk3_i;
+            4: clkOutMMCMReg = Clk4_i;
+            5: clkOutMMCMReg = Clk5_i;
+            6: clkOutMMCMReg = Clk6_i;
+            default: clkOutMMCMReg = 0;
+        endcase
+    end
+end
+
+BUFG BUFG_inst (
+   .O(ClkOutMMCM_o), // 1-bit output: Clock output
+   .I(clkOutMMCM)  // 1-bit input: Clock input
+);
+
+endmodule

sources_1/new/ClkManager/SpiClkMux.v

@@ -0,0 +1,46 @@
+module SpiClkMux (
+    input Rst_i,
+    input clkCh,
+    input clkOutMMCM,
+    input clkMan,
+
+    output SpiClk_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg spiClkReg;
+
+wire spiClk;
+
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign spiClk = spiClkReg;
+
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(*) begin 
+    if (Rst_i) begin 
+        spiClkReg = 0;
+    end
+    else begin 
+        if (clkCh) begin 
+            spiClkReg = clkOutMMCM;
+        end
+        else begin 
+            spiClkReg = clkMan;
+        end
+    end
+end
+
+BUFG BUFG_inst (
+   .O(SpiClk_o), // 1-bit output: Clock output
+   .I(spiClk)  // 1-bit input: Clock input
+);
+
+endmodule
+
+
+

sources_1/new/MMCM/ClkCh.v

@@ -1,53 +0,0 @@
-module ClkCh (
-    input Rst_i,
-    input clkCh,
-    input clkOutMMCM,
-    input clkMan,
-
-    output SpiClk_o
-
-
-
-);
-
-
-reg spiClkReg;
-
-wire spiClk;
-
-assign spiClk = spiClkReg;
-
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        spiClkReg = 0;
-    end
-    else begin 
-        if (clkCh) begin 
-            spiClkReg = clkOutMMCM;
-        end
-        else begin 
-            spiClkReg = clkMan;
-        end
-    end
-end
-
-
-
-BUFG BUFG_inst (
-   .O(SpiClk_o), // 1-bit output: Clock output
-   .I(spiClk)  // 1-bit input: Clock input
-);
-
-
-
-
-
-
-
-
-endmodule
-
-
-

sources_1/new/MMCM/ClkDivSync.v

@@ -1,44 +0,0 @@
-module ClkDivSync #(
-    parameter WIDTH = 4,
-    parameter STAGES = 3
-
-
-
-)
-(
-    input ClkFast_i,
-    input ClkSlow_i,
-    input [WIDTH-1:0] ClkDiv_i,
-
-    output [WIDTH-1:0] ClkDiv_o
-);
-
-
-//lauch registers 
-reg [WIDTH-1:0] clkDivReg;
-
-// capture registers
-(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
-
-
-assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-
-
-
-always @(posedge ClkFast_i) begin
-    clkDivReg <= ClkDiv_i;
-end
-
-
-
-
-
-always @(posedge ClkSlow_i) begin
-    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
-end
-
-
-
-
-
-endmodule

sources_1/new/MMCM/ClkOutMMCM.v

@@ -1,55 +0,0 @@
-module clkOutMMCM(
-input Rst_i,
-input [2:0]clkNum,
-input clk0out,
-input clk1out,
-input clk2out,
-input clk3out,
-input clk4out,
-input clk5out,
-input clk6out, 
-
-output   ClkOutMMCM_o
-
-);
-
-
-reg clkOutMMCMReg;
-
-wire clkOutMMCM;
-
-assign clkOutMMCM = clkOutMMCMReg;
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        clkOutMMCMReg = 0;
-    end
-    else begin 
-        case (clkNum) 
-            0: clkOutMMCMReg = clk0out;
-            1: clkOutMMCMReg = clk1out;
-            2: clkOutMMCMReg = clk2out;
-            3: clkOutMMCMReg = clk3out;
-            4: clkOutMMCMReg = clk4out;
-            5: clkOutMMCMReg = clk5out;
-            6: clkOutMMCMReg = clk6out;
-            default: clkOutMMCMReg = 0;
-        endcase
-    end
-end
-
-
-
-
-BUFG BUFG_inst (
-   .O(ClkOutMMCM_o), // 1-bit output: Clock output
-   .I(clkOutMMCM)  // 1-bit input: Clock input
-);
-
-
-
-
-
-
-endmodule

sources_1/new/S5443_3Top.v

@@ -811,11 +811,10 @@ module S5443_3Top
 
     );
     
-    MmcmWrapper #(
+    ClkManager #(
         .SpiNum(SpiNum),
         .STAGES(STAGES) 
-
-    ) MainMmcm
+    ) ClkManager
     (
     	.Clk_i(gclk),
     	.Rst_i(initRst),