Добавлен ClkGen

SRAM/RegMap.v

@@ -153,7 +153,7 @@ reg [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi6TxFifoReg;
 reg [CmdRegWidth/2-1:0] Spi6RxFifoReg;
 
-reg [CmdRegWidth/2-1:0] SpiTxRxEnReg;
+(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] SpiTxRxEnReg;
 reg [CmdRegWidth/2-1:0] GPIOAReg;
 reg [CmdRegWidth/2-1:0] GPIOARegS;
 
@@ -552,10 +552,10 @@ always @(posedge Clk_i) begin
                             SpiTxRxEnReg <= Data_i;
                         end
                         GPIOCtrlAddr : begin 
-                            GPIOAReg <= Data_i[15:0];
+                            GPIOAReg <= Data_i;
                         end
                         GPIOCtrlAddrS : begin 
-                            GPIOARegS <= Data_i[31:16];
+                            GPIOARegS <= Data_i;
                         end
                         Debug0Addr : begin 
                             LedReg <= Data_i;
@@ -739,7 +739,7 @@ always @(posedge Clk_i) begin
                             GPIOAReg[15:8] <= Data_i[15:8];
                         end
                         GPIOCtrlAddrS : begin 
-                            GPIOARegS[15:8] <= Data_i[31:24];
+                            GPIOARegS[15:8] <= Data_i[15:8];
                         end
                         Debug0Addr : begin 
                             LedReg[15:8] <= Data_i[15:8];
@@ -923,7 +923,7 @@ always @(posedge Clk_i) begin
                             GPIOAReg[7:0] <= Data_i[7:0];
                         end
                         GPIOCtrlAddrS : begin 
-                            GPIOARegS[7:0] <= Data_i[23:16];
+                            GPIOARegS[7:0] <= Data_i[7:0];
                         end
                         Debug0Addr : begin 
                             LedReg[7:0] <= Data_i[7:0];

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -42,6 +42,7 @@ module DataFifoWrapper
 //	ASSIGNMENTS
 //================================================================================
 	assign	ToSpiVal_o	=	1'b1;
+	assign DataFromRxFifo_o = dataFromRxFifo;
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -72,10 +73,11 @@ FifoCtrl FifoCtrl_inst (
 
 
 
-DataFifo	DataFifoTx
+DataFifoTx	DataFifoTx
 ( 
 	.wr_clk		(WrClk_i), 
 	.rd_clk		(RdClk_i), 
+	.rst		(FifoTxRst_i),
 	.din		(ToFifoData_i), 
 	.wr_en		(txFifoWrEn), 
 	.rd_en		(txFifoRdEn), 
@@ -84,10 +86,11 @@ DataFifo	DataFifoTx
 	.empty		(emptyFlagTx)
 );
 
-DataFifo	DataFifoRx
+DataFifoRx	DataFifoRx
 ( 
 	.wr_clk		(RdClk_i), 
-	.rd_clk		(WrClk_i), 
+	.rd_clk		(WrClk_i),
+	.rst		(FifoRxRst_i), 
 	.din		(ToFifoRxData_i), 
 	.wr_en		(rxFifoWrEn), 
 	.rd_en		(rxFifoRdEn), 

sources_1/new/DataFifo/DataOutMux.v

@@ -0,0 +1,89 @@
+module DataOutMux (
+    input Rst_i,
+    input Clk_i,
+    input [11:0] Addr_i,
+    input [11:0] ToRegMapAddr_i,
+    input [15:0] DataFromRegMap_i,
+    input [31:0] DataFromRxFifo1_i,
+    input [31:0] DataFromRxFifo2_i,
+    input [31:0] DataFromRxFifo3_i,
+    input [31:0] DataFromRxFifo4_i,
+    input [31:0] DataFromRxFifo5_i,
+    input [31:0] DataFromRxFifo6_i,
+    input [31:0] DataFromRxFifo7_i,
+
+    output [15:0] AnsData_o
+
+);
+
+
+wire [0:31] dataFromRxFifo [6:0];
+wire [15:0] dataFromRegMap;
+
+reg [15:0] dataFromRxFifoR;
+
+
+assign dataFromRxFifo[0] = DataFromRxFifo1_i;
+assign dataFromRxFifo[1] = DataFromRxFifo2_i;
+assign dataFromRxFifo[2] = DataFromRxFifo3_i;
+assign dataFromRxFifo[3] = DataFromRxFifo4_i;
+assign dataFromRxFifo[4] = DataFromRxFifo5_i;
+assign dataFromRxFifo[5] = DataFromRxFifo6_i;
+assign dataFromRxFifo[6] = DataFromRxFifo7_i;
+
+assign dataFromRegMap = DataFromRegMap_i;
+assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
+
+
+
+always @(*) begin 
+        case (Addr_i)  
+            12'h1c: begin 
+                dataFromRxFifoR = DataFromRxFifo1_i[15:0];
+            end
+            12'h1e: begin
+                dataFromRxFifoR = DataFromRxFifo1_i[31:16];
+            end 
+            12'h6c: begin 
+                dataFromRxFifoR =  DataFromRxFifo2_i[15:0];
+            end
+            12'h6e: begin 
+                dataFromRxFifoR = DataFromRxFifo2_i[31:16];
+            end
+            12'h10c: begin 
+                dataFromRxFifoR =  DataFromRxFifo3_i[15:0];
+            end
+            12'h10e: begin 
+                dataFromRxFifoR = DataFromRxFifo1_i[31:16];
+            end
+            12'h15c: begin 
+                dataFromRxFifoR =  DataFromRxFifo4_i[15:0];
+            end
+            12'h15e: begin 
+                dataFromRxFifoR = DataFromRxFifo4_i[31:16];
+            end
+            12'h1ac: begin 
+                dataFromRxFifoR =  DataFromRxFifo5_i[15:0];
+            end
+            12'h1ae: begin 
+                dataFromRxFifoR = DataFromRxFifo5_i[31:16];
+            end
+            12'h1fc: begin 
+                dataFromRxFifoR =  DataFromRxFifo6_i[15:0];
+            end
+            12'h1fe: begin 
+                dataFromRxFifoR = DataFromRxFifo6_i[31:16];
+            end
+            12'h24c: begin 
+                dataFromRxFifoR =  DataFromRxFifo7_i[15:0];
+            end
+            12'h24e: begin 
+                dataFromRxFifoR = DataFromRxFifo7_i[31:16];
+            end
+        endcase
+    end
+
+
+
+
+endmodule

sources_1/new/DataFifo/FifoCtrl.v

@@ -18,18 +18,63 @@ module FifoCtrl (
 );
 
 
+reg FifoTxWriteEn;
+reg FifoTxReadEn;
+reg FifoRxWriteEn;
+reg FifoRxReadEn;
+
+
 
 // //================================================================================
 // //	ASSIGNMENTS
 
-assign FifoTxWriteEn_o = ToFifoTxWriteVal_i & ~FifoTxFull_i;
-assign FifoTxReadEn_o = ToFifoTxReadVal_i & ~FifoTxEmpty_i;
-assign FifoRxWriteEn_o = ToFifoRxWriteVal_i & ~FifoRxFull_i;
-assign FifoRxReadEn_o = ToFifoRxReadVal_i & ~FifoRxEmpty_i;
+assign FifoTxWriteEn_o = FifoTxWriteEn;
+assign FifoTxReadEn_o = FifoTxReadEn;
+assign FifoRxWriteEn_o = FifoRxWriteEn;
+assign FifoRxReadEn_o = FifoRxReadEn;
 
 
 
 // //================================================================================
 
 
+
+always @(*) begin 
+    if (ToFifoTxWriteVal_i && ~FifoTxFull_i) begin 
+        FifoTxWriteEn = 1'b1;
+    end
+    else begin 
+        FifoTxWriteEn = 1'b0;
+    end
+end
+
+always @(*) begin 
+    if (ToFifoTxReadVal_i && ~FifoTxEmpty_i) begin 
+        FifoTxReadEn = 1'b1;
+    end
+    else begin 
+        FifoTxReadEn = 1'b0;
+    end
+end
+
+always @(*) begin 
+    if (ToFifoRxWriteVal_i && ~FifoRxFull_i) begin 
+        FifoRxWriteEn = 1'b1;
+    end
+    else begin 
+        FifoRxWriteEn = 1'b0;
+    end
+end
+
+always @(*) begin 
+    if (ToFifoRxReadVal_i && ~FifoRxEmpty_i) begin 
+        FifoRxReadEn = 1'b1;
+    end
+    else begin 
+        FifoRxReadEn = 1'b0;
+    end
+end
+
+// //================================================================================
+
 endmodule

sources_1/new/MMCM/ClkCh.v

@@ -0,0 +1,38 @@
+module ClkCh (
+    input Rst_i,
+    input clkCh,
+    input clkOutMMCM,
+    input clkMan,
+
+    output reg SpiClk_o
+
+
+
+);
+
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        SpiClk_o = 0;
+    end
+    else begin 
+        if (clkCh) begin 
+            SpiClk_o = clkOutMMCM;
+        end
+        else begin 
+            SpiClk_o = clkMan;
+        end
+    end
+end
+
+
+
+
+
+
+
+
+
+
+endmodule

sources_1/new/MMCM/ClkGen.v

@@ -0,0 +1,38 @@
+module ClkGen (
+  input Clk_i,
+  input [3:0] ClkDiv_i,
+  input Rst_i,
+  output Clk_o
+);
+
+reg [16:0] cnt;
+
+reg clk;
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        cnt <= 0;
+    end
+    else begin 
+        if (cnt == ClkDiv_i+1) begin 
+            cnt <= 0;
+        end
+        else begin 
+            cnt <= cnt + 1;
+        end
+    end
+end
+
+assign Clk_o = (cnt < ClkDiv_i/2+1) ? 1 : 0;
+
+
+
+
+
+
+
+
+
+endmodule

sources_1/new/MMCM/ClkOutMMCM.v

@@ -0,0 +1,41 @@
+module clkOutMMCM(
+input Rst_i,
+input [2:0]clkNum,
+input clk0out,
+input clk1out,
+input clk2out,
+input clk3out,
+input clk4out,
+input clk5out,
+input clk6out, 
+
+output reg [6:0] clkOutMMCM
+
+);
+
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        clkOutMMCM = 0;
+    end
+    else begin 
+        case (clkNum) 
+            0: clkOutMMCM = clk0out;
+            1: clkOutMMCM = clk1out;
+            2: clkOutMMCM = clk2out;
+            3: clkOutMMCM = clk3out;
+            4: clkOutMMCM = clk4out;
+            5: clkOutMMCM = clk5out;
+            6: clkOutMMCM = clk6out;
+            default: clkOutMMCM = 0;
+        endcase
+    end
+end
+
+
+
+
+
+
+endmodule

sources_1/new/MMCM/MmcmWrapper.v

@@ -6,17 +6,17 @@ module MmcmWrapper
 (
    input	Clk_i,
    input	Rst_i,
-   input [6:0] ClkDiv1_i,
-   input [15:0] ClkDiv2_i,
-   input [15:0] ClkDiv3_i,
-   input [15:0] ClkDiv4_i,
-   input [15:0] ClkDiv5_i,
-   input [15:0] ClkDiv6_i,
-   input [15:0] ClkDiv7_i,
+   input [7:0] BaudRate0_i,
+   input [7:0] BaudRate1_i,
+   input [7:0] BaudRate2_i,
+   input [7:0] BaudRate3_i,
+   input [7:0] BaudRate4_i,
+   input [7:0] BaudRate5_i,
+   input [7:0] BaudRate6_i,
 
 
 
-	output	[SpiNum-1:0]	SpiClk_o
+	output 	[SpiNum-1:0]	SpiClk_o
 );
 //================================================================================
 //	REG/WIRE
@@ -29,228 +29,136 @@ wire            clk3out;
 wire            clk4out;
 wire            clk5out;
 wire            clk6out;
-wire            SRDY;
 wire            locked;
 
-reg [1:0] SM = STARTUP;
-reg SSTEP;
+wire [SpiNum-1:0] clkOutMMCM;
 
-reg sStep1;
-reg sStep2;
-reg sStep3;
-reg sStep4;
-reg sStep5;
-reg sStep6;
-reg sStep7;
 
+wire [SpiNum-1:0] clkMan;
 
-reg clkDiv1R;
-reg clkDiv2R;
-reg clkDiv3R;
-reg clkDiv4R;
-reg clkDiv5R;
-reg clkDiv6R;
-reg clkDiv7R;
+wire [0:2] clkNum [SpiNum-1:0];
+wire [0:3] clkDiv [SpiNum-1:0];
+wire [SpiNum-1:0] clkCh; 
+wire [SpiNum-1:0] spiClk;
 
 
 
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	assign SpiClk_o[0]	=	clk0out;
-   assign SpiClk_o[1]	=	clk1out;
-   assign SpiClk_o[2]	=	clk2out;
-   assign SpiClk_o[3]	=	clk3out;
-   assign SpiClk_o[4]	=	clk4out;
-   assign SpiClk_o[5]	=	clk5out;
-   assign SpiClk_o[6]	=	clk6out;
+	// assign SpiClk_o[0]	=	clk1out;
+   // assign SpiClk_o[1]	=	clk2out;
+   // assign SpiClk_o[2]	=	clk3out;
+   // assign SpiClk_o[3]	=	clk4out;
+   // assign SpiClk_o[4]	=	clk5out;
+   // assign SpiClk_o[5]	=	clk6out;
+   // assign SpiClk_o[6]	=	clk7out;
+
+   assign clkNum[0] = BaudRate0_i[7:5];
+   assign clkNum[1] = BaudRate1_i[7:5];
+   assign clkNum[2] = BaudRate2_i[7:5];
+   assign clkNum[3] = BaudRate3_i[7:5];
+   assign clkNum[4] = BaudRate4_i[7:5];
+   assign clkNum[5] = BaudRate5_i[7:5];
+   assign clkNum[6] = BaudRate6_i[7:5];
+
+   assign clkDiv[0] = BaudRate0_i[3:0];
+   assign clkDiv[1] = BaudRate1_i[3:0];
+   assign clkDiv[2] = BaudRate2_i[3:0];
+   assign clkDiv[3] = BaudRate3_i[3:0];
+   assign clkDiv[4] = BaudRate4_i[3:0];
+   assign clkDiv[5] = BaudRate5_i[3:0];
+   assign clkDiv[6] = BaudRate6_i[3:0];
+
+   assign clkCh[0] = BaudRate0_i[4];
+   assign clkCh[1] = BaudRate1_i[4];
+   assign clkCh[2] = BaudRate2_i[4];
+   assign clkCh[3] = BaudRate3_i[4];
+   assign clkCh[4] = BaudRate4_i[4];
+   assign clkCh[5] = BaudRate5_i[4];
+   assign clkCh[6] = BaudRate6_i[4];
+
+   assign SpiClk_o[0] = spiClk[0];
+   assign SpiClk_o[1] = spiClk[1];
+   assign SpiClk_o[2] = spiClk[2];
+   assign SpiClk_o[3] = spiClk[3];
+   assign SpiClk_o[4] = spiClk[4];
+   assign SpiClk_o[5] = spiClk[5];
+   assign SpiClk_o[6] = spiClk[6];
+
+
 
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
-parameter [1:0] STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;
+
 
 //================================================================================
 //	CODING
 //================================================================================
-top_mmcme2 MMCE2_inst (
-   .SSTEP      (),
-   .STATE      (),
-   .RST        (Rst_i),
-   .CLKIN      (Clk_i),
-   .SRDY       (SRDY),
-   .LOCKED_OUT (locked),
-   .CLK0OUT    (clk0out),
-   .CLK1OUT    (clk1out),
-   .CLK2OUT    (clk2out),
-   .CLK3OUT    (clk3out),
-   .CLK4OUT    (clk4out),
-   .CLK5OUT    (clk5out),
-   .CLK6OUT    (clk6out)
 
 
 
+   
 
+genvar i;
 
+generate
+   for (i=0; i < SpiNum; i = i +1) begin : ClkGen
+      ClkGen ClkGen_inst (
+         .Clk_i(clk1out),
+         .ClkDiv_i(clkDiv[i]),
+         .Rst_i(Rst_i),
+         .Clk_o(clkMan[i])
+      );
 
+      clkOutMMCM clkOutMMCM_inst (
+         .Rst_i(Rst_i),
+         .clkNum(clkNum[i]),
+         .clk0out(clk0out),
+         .clk1out(clk1out),
+         .clk2out(clk2out),
+         .clk3out(clk3out),
+         .clk4out(clk4out),
+         .clk5out(clk5out),
+         .clk6out(clk6out),
+         .clkOutMMCM(clkOutMMCM[i])
+      );
 
+      ClkCh ClkCh_inst (
+         .Rst_i(Rst_i),
+         .clkCh(clkCh[i]),
+         .clkOutMMCM(clkOutMMCM[i]),
+         .clkMan(clkMan[i]),
+         .SpiClk_o(spiClk[i])
+      );
+   end
 
 
-);
+endgenerate
 
-always @(posedge Clk_i) begin 
-   if (Rst_i) begin 
-      clkDiv1R <= 1'b0;
-      clkDiv2R <= 1'b0;
-      clkDiv3R <= 1'b0;
-      clkDiv4R <= 1'b0;
-      clkDiv5R <= 1'b0;
-      clkDiv6R <= 1'b0;
-      clkDiv7R <= 1'b0;
-   end
-   else begin 
-      clkDiv1R <= ClkDiv1_i;
-      clkDiv2R <= ClkDiv2_i;
-      clkDiv3R <= ClkDiv3_i;
-      clkDiv4R <= ClkDiv4_i;
-      clkDiv5R <= ClkDiv5_i;
-      clkDiv6R <= ClkDiv6_i;
-      clkDiv7R <= ClkDiv7_i;
-   end
-end
 
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep1<= 1'b0;
-   end
-   else begin 
-      if (clkDiv1R != ClkDiv1_i) begin 
-         sStep1 <= 1'b1;
-      end
-      else begin 
-         sStep1 <= 1'b0;
-      end
-   end
-end
-
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep2<= 1'b0;
-   end
-   else begin 
-      if (clkDiv2R != ClkDiv2_i) begin 
-         sStep2 <= 1'b1;
-      end
-      else begin 
-         sStep2 <= 1'b0;
-      end
-   end
-end
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep3<= 1'b0;
-   end
-   else begin 
-      if (clkDiv3R != ClkDiv3_i) begin 
-         sStep3 <= 1'b1;
-      end
-      else begin 
-         sStep3 <= 1'b0;
-      end
-   end
-end
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep4<= 1'b0;
-   end
-   else begin 
-      if (clkDiv4R!= ClkDiv4_i) begin 
-         sStep4 <= 1'b1;
-      end
-      else begin 
-         sStep4 <= 1'b0;
-      end
-   end
-end
+  ClkDiv ClkDiv_inst
+   (
+    // Clock out ports
+    .clk_out1(clk0out),     //100 MHz
+    .clk_out2(clk1out),     // 80 MHz
+    .clk_out3(clk2out),     // 70 MHz
+    .clk_out4(clk3out),     // 60MHz
+    .clk_out5(clk4out),     // 50MHz
+    .clk_out6(clk5out),     // 40MHz
+    .clk_out7(clk6out),     // 30MHz 
+    // Status and control signals
+    .reset(Rst_i), // input reset
+    .locked(locked),       // output locked
+   // Clock in ports
+    .clk_in1(Clk_i));      // input clk_in1
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep5<= 1'b0;
-   end
-   else begin 
-      if (clkDiv5R != ClkDiv5_i) begin 
-         sStep5 <= 1'b1;
-      end
-      else begin 
-         sStep5 <= 1'b0;
-      end
-   end
-end
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep6<= 1'b0;
-   end
-   else begin 
-      if (clkDiv6R != ClkDiv6_i) begin 
-         sStep6 <= 1'b1;
-      end
-      else begin 
-         sStep6 <= 1'b0;
-      end
-   end
-end
 
-always @(*) begin 
-   if (Rst_i) begin 
-      sStep7<= 1'b0;
-   end
-   else begin 
-      if (clkDiv7R != ClkDiv7_i) begin 
-         sStep7 <= 1'b1;
-      end
-      else begin 
-         sStep7 <= 1'b0;
-      end
-   end
-end
-
-// always @ (posedge Clk_i) begin 
-//    if (Rst_i) begin
-//       SM <= STARTUP;
-//    end
-//    else begin 
-//       case (SM)
-//          STARTUP: begin
-//             SM <= STATE0;
-//             SSTEP <= 1'b0;
-//             STATE <= 1'b0;
-//          end
-//          STATE0: begin
-//                if(locked) begin 
-//                   if (ssTep1 | ssTep2 | ssTep3 | ssTep4 | ssTep5 | ssTep6 | ssTep7) begin 
-//                      SSTEP <= 1'b1;
-//                   end
-//                   else begin 
-//                      SSTEP <= 1'b0;
-//                   end
-//                end
-//             end
-//          end
-//          STATE1: begin
-//             if (SRDY) begin
-//                SM <= STATE0;
-//             end
-//          end
-//          UNDEFINED: begin
-//             SM <= STARTUP;
-//          end
-//       endcase
-//    end
-// end
 
 
 

sources_1/new/Mux/DataMuxer.v

@@ -144,6 +144,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 									ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
 								end
 			endcase
+			ToRegMapAddr_o	<=	0;
 		end	else	begin
 			ToRegMapVal_o	<=	SmcVal_i;
 			ToRegMapData_o	<=	SmcData_i;

sources_1/new/S5443_3Top.v

@@ -71,7 +71,7 @@ wire clk80;
 wire clk61;
 wire initRst;
 wire gclk;
-wire [0:15] baudRate [SpiNum-1:0];
+wire [0:7] baudRate [SpiNum-1:0];
 
 
 //SPI0
@@ -150,7 +150,7 @@ wire	[SpiNum-1:0]	toFifoVal;
 wire	[CmdRegWidth*SpiNum-1:0]	toFifoData;
 
 wire	[SpiNum-1:0]	toSpiVal;
-wire	[CmdRegWidth-1:0]	toSpiData;
+wire	[0:31]	toSpiData [SpiNum-1:0];
 
 wire [0:1] widthSel [SpiNum-1:0];
 wire [SpiNum-1:0] CPOL;
@@ -203,9 +203,11 @@ wire [SpiNum-1:0] Mosi0Q;
 wire [SpiNum-1:0] valToTxQ;
 wire [SpiNum-1:0] valToRxQ;
 wire [0:31] dataToRxFifoQ [SpiNum-1:0];
-wire [0:15] dataFromRxFifo [SpiNum-1:0];
-reg  [15:0] dataFromRxFifoR;
-wire [15:0] dataFromRxFifoW;
+wire [0:31] dataFromRxFifo [SpiNum-1:0];
+
+wire [CmdRegWidth/2-1:0] muxedData;
+
+
 
 
 
@@ -319,13 +321,13 @@ assign lag[4] = spi4CsDelay[0];
 assign lag[5] = spi5CsDelay[0];
 assign lag[6] = spi6CsDelay[0];
 
-assign baudRate[0] = spi0Clk[15:0];
-assign baudRate[1] = spi1Clk[15:0];
-assign baudRate[2] = spi2Clk[15:0];
-assign baudRate[3] = spi3Clk[15:0];
-assign baudRate[4] = spi4Clk[15:0];
-assign baudRate[5] = spi5Clk[15:0];
-assign baudRate[6] = spi6Clk[15:0];
+assign baudRate[0] = spi0Clk[7:0];
+assign baudRate[1] = spi1Clk[7:0];
+assign baudRate[2] = spi2Clk[7:0];
+assign baudRate[3] = spi3Clk[7:0];
+assign baudRate[4] = spi4Clk[7:0];
+assign baudRate[5] = spi5Clk[7:0];
+assign baudRate[6] = spi6Clk[7:0];
 
 
 assign SpiRst_o[0] = GPIOA[0];
@@ -444,68 +446,30 @@ assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
 assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
 
 
-assign dataFromRxFifoW =  dataFromRxFifoR;
-
-assign Data_i = (!SmcAre_i)?((toRegMapAddr)? ansData: dataFromRxFifoW):16'bz;
+assign SmcData_i = (!SmcAoe_i)?muxedData:16'bz;
 
 //================================================================================
 //  CODING
 //================================================================================	
 
-always @(*) begin 
-    if (initRst) begin 
-        dataFromRxFifoR = 16'b0;
-    end
-    else begin 
-        case (smcAddr)  
-            12'h1c: begin 
-                dataFromRxFifoR = dataFromRxFifo[0][15:0];
-            end
-            12'h1e: begin
-                dataFromRxFifoR = dataFromRxFifo[0][31:16];
-            end 
-            12'h6c: begin 
-                dataFromRxFifoR = dataFromRxFifo[1][15:0];
-            end
-            12'h6e: begin 
-                dataFromRxFifoR = dataFromRxFifo[1][31:16];
-            end
-            12'h10c: begin 
-                dataFromRxFifoR = dataFromRxFifo[2][15:0];
-            end
-            12'h10e: begin 
-                dataFromRxFifoR = dataFromRxFifo[2][31:16];
-            end
-            12'h15c: begin 
-                dataFromRxFifoR = dataFromRxFifo[3][15:0];
-            end
-            12'h15e: begin 
-                dataFromRxFifoR = dataFromRxFifo[3][31:16];
-            end
-            12'h1ac: begin 
-                dataFromRxFifoR = dataFromRxFifo[4][15:0];
-            end
-            12'h1ae: begin 
-                dataFromRxFifoR = dataFromRxFifo[4][31:16];
-            end
-            12'h1fc: begin 
-                dataFromRxFifoR = dataFromRxFifo[5][15:0];
-            end
-            12'h1fe: begin 
-                dataFromRxFifoR = dataFromRxFifo[5][31:16];
-            end
-            12'h24c: begin 
-                dataFromRxFifoR = dataFromRxFifo[6][15:0];
-            end
-            12'h24e: begin 
-                dataFromRxFifoR = dataFromRxFifo[6][31:16];
-            end
-            default: dataFromRxFifoR = 16'b0;
-        endcase
-    end
-end
 
 
+DataOutMux DataOutMuxer
+(
+    // .Rst_i	(initRst),
+    .Addr_i  (smcAddr),
+    .ToRegMapAddr_i (toRegMapAddr),
+    .DataFromRegMap_i (ansData),
+    .DataFromRxFifo1_i (dataFromRxFifo[0]),
+    .DataFromRxFifo2_i (dataFromRxFifo[1]),
+    .DataFromRxFifo3_i (dataFromRxFifo[2]),
+    .DataFromRxFifo4_i (dataFromRxFifo[3]),
+    .DataFromRxFifo5_i (dataFromRxFifo[4]),
+    .DataFromRxFifo6_i (dataFromRxFifo[5]),
+    .DataFromRxFifo7_i (dataFromRxFifo[6]),
+    .AnsData_o (muxedData)
+    
+);
 
 BUFG BUFG_inst (
    .O(gclk), // 1-bit output: Clock output
@@ -637,7 +601,13 @@ MmcmWrapper MainMmcm
 (
 	.Clk_i		(gclk),
 	.Rst_i		(initRst),
-
+    .BaudRate0_i(baudRate[0]),
+    .BaudRate1_i(baudRate[1]),
+    .BaudRate2_i(baudRate[2]),
+    .BaudRate3_i(baudRate[3]),
+    .BaudRate4_i(baudRate[4]),
+    .BaudRate5_i(baudRate[5]),
+    .BaudRate6_i(baudRate[6]),
 	.SpiClk_o	(spiClkBus)
 );