Рефакторинг топ модуля

sources_1/new/DataFifo/SmcAnsMux.v

@@ -23,16 +23,15 @@ module SmcAnsMux
 	parameter	ADDR_REG_WIDTH	=	12
 )
 (
-	input Rst_i,
-	input FifoRxRst_i,
 	input Clk_i,
-	input SmcAre_i,
 	input [ADDR_REG_WIDTH-1:0] Addr_i,
 	input [ADDR_REG_WIDTH-1:0] ToRegMapAddr_i,
 	input RequestToFifo_i,
-	input ToFifoVal_i,
+	input FifoRxRst_i,
+	input SmcAre_i,
 
 	input [CMD_REG_WIDTH/2-1:0] DataFromRegMap_i,
+
 	input [CMD_REG_WIDTH-1:0] DataFromRxFifo1_i,
 	input [CMD_REG_WIDTH-1:0] DataFromRxFifo2_i,
 	input [CMD_REG_WIDTH-1:0] DataFromRxFifo3_i,
@@ -97,41 +96,30 @@ module SmcAnsMux
 	end
 	
 	always @(*) begin
-		if (Rst_i) begin
-			dataFromRxFifoR1 = 0;
-			dataFromRxFifoR2 = 0;
-			dataFromRxFifoR3 = 0;
-			dataFromRxFifoR4 = 0;
-			dataFromRxFifoR5 = 0;
-			dataFromRxFifoR6 = 0;
-			dataFromRxFifoR7 = 0;
-		end
-		else begin
-			if (!SmcAre_i && readEnCnt < 1) begin  
-				case(Addr_i) 
-					12'h1c: begin
-						dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
-					end
-					12'h6c: begin
-						dataFromRxFifoR2 = DataFromRxFifo2_i;
-					end
-					12'h10c: begin
-						dataFromRxFifoR3 = DataFromRxFifo3_i;
-					end
-					12'h15c: begin
-						dataFromRxFifoR4 = DataFromRxFifo4_i;
-					end
-					12'h1ac: begin
-						dataFromRxFifoR5 = DataFromRxFifo5_i;
-					end
-					12'h1fc: begin
-						dataFromRxFifoR6 = DataFromRxFifo6_i;
-					end
-					12'h24c: begin
-						dataFromRxFifoR7 = DataFromRxFifo7_i;
-					end
-				endcase
-			end
+		if (!SmcAre_i && readEnCnt < 1) begin  
+			case(Addr_i)
+				12'h1c: begin
+					dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
+				end
+				12'h6c: begin
+					dataFromRxFifoR2 = DataFromRxFifo2_i;
+				end
+				12'h10c: begin
+					dataFromRxFifoR3 = DataFromRxFifo3_i;
+				end
+				12'h15c: begin
+					dataFromRxFifoR4 = DataFromRxFifo4_i;
+				end
+				12'h1ac: begin
+					dataFromRxFifoR5 = DataFromRxFifo5_i;
+				end
+				12'h1fc: begin
+					dataFromRxFifoR6 = DataFromRxFifo6_i;
+				end
+				12'h24c: begin
+					dataFromRxFifoR7 = DataFromRxFifo7_i;
+				end
+			endcase
 		end
 	end
 	

sources_1/new/RegMap/RegMap.v

@@ -18,8 +18,8 @@
 // 
 //////////////////////////////////////////////////////////////////////////////////
 module RegMap #(
-	parameter CmdRegWidth = 32,
-	parameter AddrRegWidth = 12
+	parameter CMD_REG_WIDTH = 32,
+	parameter ADDR_REG_WIDTH = 12
 )
 (
 	input Clk_i,