Обновлены констрейны, добавлены примные модули Spi для отладки.

sources_1/new/QuadSPI/QuadSPIs.v

@@ -16,7 +16,8 @@ module QuadSPIs (
 
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
-      output [31:0] DataToRxFifo_o,
+    output [31:0] DataToRxFifo_o,
+    output reg [191:0] DebugData_o,
     output reg Val_o
 );
 
@@ -42,13 +43,15 @@ reg [7:0] shiftReg1M;
 reg [7:0] shiftReg2M;
 reg [7:0] addrRegM;
 
+reg [47:0] shiftReg0Debug;
+reg [47:0] shiftReg1Debug;
+reg [47:0] shiftReg2Debug;
+reg [47:0] shiftReg3Debug;
 
 //===============================================================================
 //  ASSIGNMENTS
 
-
 assign DataToRxFifo_o = {Addr_o, Data_o};
-
 //================================================================================
 //	CODING
 //================================================================================
@@ -159,6 +162,73 @@ always @(posedge Clk_i) begin
     end
 end
 
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        DebugData_o <= 192'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            DebugData_o <= {shiftReg0Debug,shiftReg1Debug, shiftReg2Debug,shiftReg3Debug};
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg0Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg0Debug <= {shiftReg0Debug[46:0], Mosi0_i};
+        end
+        else begin 
+            shiftReg0Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg1Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg1Debug <= {shiftReg1Debug[46:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg1Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg2Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg2Debug <= {shiftReg2Debug[46:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg2Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg3Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg3Debug <= {shiftReg3Debug[46:0], Mosi3_i};
+        end
+        else begin 
+            shiftReg3Debug <= 48'h0;
+        end
+    end
+end
+
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         Addr_o <= 8'h0;

sources_1/new/S5443_3Top.v

@@ -25,7 +25,7 @@ module S5443_3Top
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
     parameter STAGES = 3,
-    parameter SpiNum = 1
+    parameter SpiNum = 7
 
 )
 (
@@ -46,12 +46,13 @@ module S5443_3Top
     output  [SpiNum-1:0] Mosi0_o, 
     inout   [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; 
     output  [SpiNum-1:0] Mosi2_o,
-    output  [SpiNum-1:0] Mosi3_o,
+    output  [SpiNum-2:0] Mosi3_o,
     output  [SpiNum-1:0] Ss_o,
     output  [SpiNum-1:0] SsFlash_o,
     output  [SpiNum-1:0] Sck_o,
     output  [SpiNum-1:0] SpiRst_o,
     output  [SpiNum-1:0] SpiDir_o,
+    output LoCsReg_o,
     output  LD_o
 
 );
@@ -306,15 +307,23 @@ module S5443_3Top
     assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz;
     assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
     assign Mosi2_o = mosi2;
-    assign Mosi3_o = mosi3;
-
-    assign Ss_o[0] = (assel[0]) ? (chipSelFpga[0] ? ssMuxed[0] : 1'b1) : chipSelFpga[0];
-    assign Ss_o[1] = (assel[1]) ? (chipSelFpga[1] ? ssMuxed[1] : 1'b1) : chipSelFpga[1];
-    assign Ss_o[2] = (assel[2]) ? (chipSelFpga[2] ? ssMuxed[2] : 1'b1) : chipSelFpga[2];
-    assign Ss_o[3] = (assel[3]) ? (chipSelFpga[3] ? ssMuxed[3] : 1'b1) : chipSelFpga[3];
-    assign Ss_o[4] = (assel[4]) ? (chipSelFpga[4] ? ssMuxed[4] : 1'b1) : chipSelFpga[4];
-    assign Ss_o[5] = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
-    assign Ss_o[6] = (assel[6]) ? (chipSelFpga[6] ? ssMuxed[6] : 1'b1) : chipSelFpga[6];
+    assign Mosi3_o[0] = mosi3[0];
+    assign Mosi3_o[1] = mosi3[1];
+    assign Mosi3_o[2] = mosi3[2];
+    assign Mosi3_o[3] = mosi3[3];
+    assign Mosi3_o[4] = mosi3[4];
+    // assign Mosi3_o[5] = mosi3[5];
+    assign Mosi3_o[5] = mosi3[6];// Mosi6 
+
+
+    assign Ss_o[0]       = (assel[0]) ? (chipSelFpga[0] ? ssMuxed[0] : 1'b1) : chipSelFpga[0];
+    assign Ss_o[1]       = (assel[1]) ? (chipSelFpga[1] ? ssMuxed[1] : 1'b1) : chipSelFpga[1];
+    assign Ss_o[2]       = (assel[2]) ? (chipSelFpga[2] ? ssMuxed[2] : 1'b1) : chipSelFpga[2];
+    assign Ss_o[3]       = (assel[3]) ? (chipSelFpga[3] ? ssMuxed[3] : 1'b1) : chipSelFpga[3];
+    assign Ss_o[4]       = (assel[4]) ? (chipSelFpga[4] ? ssMuxed[4] : 1'b1) : chipSelFpga[4];
+    assign Ss_o[5]       = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
+    assign Ss_o[6]       = (assel[6]) ? (chipSelFpga[6] ? ssMuxed[6] : 1'b1) : chipSelFpga[6];
+    assign LoCsReg_o     = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
 
     assign SsFlash_o[0] = (assel[0]) ? (chipSelFlash[0] ? ssMuxed[0] : 1'b1) : chipSelFlash[0];
     assign SsFlash_o[1] = (assel[1]) ? (chipSelFlash[1] ? ssMuxed[1] : 1'b1) : chipSelFlash[1];
@@ -949,6 +958,17 @@ module S5443_3Top
             );
         end
     endgenerate
+
+    QuadSPIs QuadSPIs (
+        .Clk_i(spiClkBus[0]),
+        .Rst_i(initRstGen[0] | !spiMode[0]),
+        .Sck_i(sckQ[0]),
+        .Ss_i(ssQ[0]),
+        .Mosi0_i(mosi0Q[0]),
+        .Mosi1_i(mosi1[0]),
+        .Mosi2_i(mosi2[0]),
+        .Mosi3_i(mosi3[0])
+    );
     
     InitRst InitRst_inst
      (

sources_1/new/S5443_3_tb.v

@@ -48,7 +48,7 @@ localparam ClockPolarity0 = 1'b0;//0 for active high, 1 for active low
 localparam Assel0 = 1'b1;//0 for software control, 1 for hardware control
 localparam SelSt0 = 1'b1; //1 - assert slave select(low), 0 - deassert slave select(high)
 localparam Size0 = 2'd2; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
-localparam Mode0 = 1'b0; // 1 - 4 Mosi, 0 - 1 Mosi
+localparam Mode0 = 1'b1; // 1 - 4 Mosi, 0 - 1 Mosi
 localparam LSBF0 = 1'b0; // 1 - LSB first, 0 - MSB first
 
 localparam [15:0] Spi0CtrlRegData = {8'h0,LSBF0, Mode0, Size0, SelSt0, Assel0, ClockPolarity0, ClockPhase0, SpiEn0};
@@ -360,7 +360,8 @@ always @(posedge Clk_i) begin
             endcase
         end
         else begin 
-                SmcData_i <= $urandom_range(0, 8'hFF);
+                // SmcData_i <= $urandom_range(0, 8'hFF);
+                SmcData_i <= 16'hffaa;
             end
     end
 end

sources_1/new/SpiR/SPIs.v

@@ -13,6 +13,7 @@ module SPIs (
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
     output [31:0] DataToRxFifo_o,
+    output reg [191:0] DebugData_o,
     output reg Val_o
 );
 
@@ -23,8 +24,9 @@ module SPIs (
     reg ssReg;
     reg ssRegR;  
     reg [31:0] shiftReg;
-    
-    reg [31:0] shiftRegM; 
+    reg [31:0] shiftRegM;
+
+    reg [255:0] shiftRegDebug; 
  
 
 //===============================================================================
@@ -100,6 +102,31 @@ module SPIs (
         end
     end
 
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftRegDebug <= 0;
+        end
+        else begin
+            if (!Ss_i) begin  
+                shiftRegDebug <= {shiftRegDebug[190:0],Mosi0_i};
+                // shiftRegDebug <= {Mosi0_i, shiftRegDebug[191:1]};
+            end
+            else begin
+                shiftRegDebug <= 192'h0;
+            end
+        end
+    end
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            DebugData_o <= 192'h0;
+        end
+        else begin 
+            if (ssReg && !ssRegR) begin 
+                DebugData_o <= shiftRegDebug;
+            end
+        end
+    end
+
     always @(posedge Sck_i) begin 
         if (Rst_i) begin 
             shiftReg<= 32'h0;