Отладка вычитывания

sources_1/new/DataFifo/DataOutMux.v

@@ -10,6 +10,7 @@ module DataOutMux#(
     input SmcAre_i,
     input [AddrRegWidth-1:0] Addr_i,
     input [AddrRegWidth-1:0] ToRegMapAddr_i,
+    input ToFifoVal_i,
     input [CmdRegWidth/2-1:0] DataFromRegMap_i,
     input [CmdRegWidth-1:0] DataFromRxFifo1_i,
     input [CmdRegWidth-1:0] DataFromRxFifo2_i,

sources_1/new/DspSmc/SmcRx.v

@@ -65,7 +65,7 @@ module	SmcRx
 	assign	Val_o	=	valReg;
 	assign	Be_o	=	beReg;
 	
-	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
+	assign	SmcD_i	=	(!SmcAre_i && !SmcAoe_i)?AnsData_i:16'bz;
 //================================================================================
 //  CODING
 	
@@ -81,7 +81,7 @@ always	@(posedge	Clk_i)	begin
 				valReg	<=	0;
 			end
 			
-			if	(!SmcAoe_i)	begin
+			if	(!SmcAre_i && !SmcAoe_i)	begin
 				addrReg		<=	{SmcA_i,1'b0};
 				outDataReg	<=	AnsData_i;
 			end	

sources_1/new/S5443_3Top.v

@@ -537,7 +537,7 @@ assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 
 
 
-
+	// assign	SmcD_i	=	(!SmcAre_i)?muxedData:16'bz;
 
 //================================================================================
 //  CODING
@@ -550,7 +550,7 @@ DataOutMux DataOutMuxer
     // .Rst_i	(initRst),
     .Addr_i  (smcAddr),
     .ToRegMapAddr_i (toRegMapAddr),
-    .DataFromRegMap_i (ansDataRR),
+    .DataFromRegMap_i (ansData),
     .SmcAre_i (SmcAre_i),
     .DataFromRxFifo1_i (dataFromRxFifo[0]),
     .DataFromRxFifo2_i (dataFromRxFifo[1]),
@@ -618,7 +618,7 @@ RegMap_inst
     .Data_i(toRegMapData),
     .Addr_i(toRegMapAddr),
     .Val_i(toRegMapVal),
-    .SmcBe_i(smcBe),
+    .SmcBe_i(SmcBe_i),
     .TxFifoCtrlReg0_i(spi0TxFifoCtrlReg),
     .TxFifoCtrlReg1_i(spi1TxFifoCtrlReg),
     .TxFifoCtrlReg2_i(spi2TxFifoCtrlReg),

sources_1/new/SRAM/RegMap.v

@@ -111,6 +111,22 @@ reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi0TxFifoReg;
 reg [CmdRegWidth/2-1:0] Spi0RxFifoReg;
 
+(* dont_touch = "yes" *) reg [CmdRegWidth-1:0] TxFifoCtrlReg0Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg0Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg1Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg1Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg2Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg2Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg3Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg3Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg4Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg4Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg5Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg5Reg;
+reg [CmdRegWidth-1:0] TxFifoCtrlReg6Reg;
+reg [CmdRegWidth-1:0] RxFifoCtrlReg6Reg;
+
+
 reg [CmdRegWidth/2-1:0] Spi1CtrlReg;
 reg [CmdRegWidth/2-1:0] Spi1ClkReg;
 reg [CmdRegWidth/2-1:0] Spi1CsDelayReg;
@@ -340,6 +356,46 @@ localparam GPIOCtrlAddrS = 12'hFF2;
 localparam Debug0Addr = 12'hFF8;
 localparam Debug1Addr = 12'hFFC;
 //================================================================================
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        TxFifoCtrlReg0Reg <= 0;
+        RxFifoCtrlReg0Reg <= 0;
+        TxFifoCtrlReg1Reg <= 0;
+        RxFifoCtrlReg1Reg <= 0;
+        TxFifoCtrlReg2Reg <= 0;
+        RxFifoCtrlReg2Reg <= 0;
+        TxFifoCtrlReg3Reg <= 0;
+        RxFifoCtrlReg3Reg <= 0;
+        TxFifoCtrlReg4Reg <= 0;
+        RxFifoCtrlReg4Reg <= 0;
+        TxFifoCtrlReg5Reg <= 0;
+        RxFifoCtrlReg5Reg <= 0;
+        TxFifoCtrlReg6Reg <= 0;
+        RxFifoCtrlReg6Reg <= 0;
+    end
+    else begin 
+        TxFifoCtrlReg0Reg <= TxFifoCtrlReg0_i;
+        RxFifoCtrlReg0Reg <= RxFifoCtrlReg0_i;
+        TxFifoCtrlReg1Reg <= TxFifoCtrlReg1_i;
+        RxFifoCtrlReg1Reg <= RxFifoCtrlReg1_i;
+        TxFifoCtrlReg2Reg <= TxFifoCtrlReg2_i;
+        RxFifoCtrlReg2Reg <= RxFifoCtrlReg2_i;
+        TxFifoCtrlReg3Reg <= TxFifoCtrlReg3_i;
+        RxFifoCtrlReg3Reg <= RxFifoCtrlReg3_i;
+        TxFifoCtrlReg4Reg <= TxFifoCtrlReg4_i;
+        RxFifoCtrlReg4Reg <= RxFifoCtrlReg4_i;
+        TxFifoCtrlReg5Reg <= TxFifoCtrlReg5_i;
+        RxFifoCtrlReg5Reg <= RxFifoCtrlReg5_i;
+        TxFifoCtrlReg6Reg <= TxFifoCtrlReg6_i;
+        RxFifoCtrlReg6Reg <= RxFifoCtrlReg6_i;
+    end
+end
+
+
+
+
+
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		beReg	<=	2'b0;
@@ -976,7 +1032,6 @@ always @(*) begin
     if (Rst_i) begin 
         ansReg = 0;
     end	else begin
-		if	(Val_i)	begin
 			case(beReg) 
 				0 : begin 
 					case (Addr_i)
@@ -993,16 +1048,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg;
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0_i[15:0];
+							ansReg = TxFifoCtrlReg0Reg[15:0];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0_i[31:16];
+                            ansReg = TxFifoCtrlReg0Reg[31:16];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0_i[15:0];
+							ansReg = RxFifoCtrlReg0Reg[15:0];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0_i[31:16];
+                            ansReg = RxFifoCtrlReg0Reg[31:16];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg;
@@ -1023,16 +1078,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg;
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1_i[15:0];
+							ansReg = TxFifoCtrlReg1Reg[15:0];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1_i[31:16];
+                            ansReg = TxFifoCtrlReg1Reg[31:16];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1_i[15:0];
+							ansReg = RxFifoCtrlReg1Reg[15:0];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1_i[31:16];
+                            ansReg = RxFifoCtrlReg1Reg[31:16];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg;
@@ -1053,16 +1108,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg;
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2_i[15:0];
+							ansReg = TxFifoCtrlReg2Reg[15:0];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2_i[31:16];
+                            ansReg = TxFifoCtrlReg2Reg[31:16];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2_i[15:0];
+							ansReg = RxFifoCtrlReg2Reg[15:0];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2_i[31:16];
+                            ansReg = RxFifoCtrlReg2Reg[31:16];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg;
@@ -1083,16 +1138,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg;
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3_i[15:0];
+							ansReg = TxFifoCtrlReg3Reg[15:0];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3_i[31:16];
+                            ansReg = TxFifoCtrlReg3Reg[31:16];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3_i[15:0];
+							ansReg = RxFifoCtrlReg3Reg[15:0];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3_i[31:16];
+                            ansReg = RxFifoCtrlReg3Reg[31:16];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg;
@@ -1113,16 +1168,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg;
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4_i[15:0];
+							ansReg = TxFifoCtrlReg4Reg[15:0];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4_i[31:16];
+                            ansReg = TxFifoCtrlReg4Reg[31:16];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4_i[15:0];
+							ansReg = RxFifoCtrlReg4Reg[15:0];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4_i[31:16];
+                            ansReg = RxFifoCtrlReg4Reg[31:16];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg;
@@ -1143,16 +1198,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg;
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5_i[15:0];
+							ansReg = TxFifoCtrlReg5Reg[15:0];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5_i[31:16];
+                            ansReg = TxFifoCtrlReg5Reg[31:16];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5_i[15:0];
+							ansReg = RxFifoCtrlReg5Reg[15:0];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5_i[31:16];
+                            ansReg = RxFifoCtrlReg5Reg[31:16];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg;
@@ -1173,16 +1228,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg;
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6_i[15:0];
+							ansReg = TxFifoCtrlReg6Reg[15:0];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6_i[31:16];
+                            ansReg = TxFifoCtrlReg6Reg[31:16];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6_i[15:0];
+							ansReg = RxFifoCtrlReg6Reg[15:0];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6_i[31:16];
+                            ansReg = RxFifoCtrlReg6Reg[31:16];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg;
@@ -1219,16 +1274,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg[15:8];
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0_i[15:8];
+							ansReg = TxFifoCtrlReg0Reg[15:8];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0_i[31:24];
+                            ansReg = TxFifoCtrlReg0Reg[31:24];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0_i[15:8];
+							ansReg = RxFifoCtrlReg0Reg[15:8];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0_i[31:24];
+                            ansReg = RxFifoCtrlReg0Reg[31:24];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg[15:8];
@@ -1249,16 +1304,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg[15:8];
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1_i[15:8];
+							ansReg = TxFifoCtrlReg1Reg[15:8];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1_i[31:24];
+                            ansReg = TxFifoCtrlReg1Reg[31:24];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1_i[15:8];
+							ansReg = RxFifoCtrlReg1Reg[15:8];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1_i[31:24];
+                            ansReg = RxFifoCtrlReg1Reg[31:24];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg[15:8];
@@ -1279,16 +1334,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg[15:8];
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2_i[15:8];
+							ansReg = TxFifoCtrlReg2Reg[15:8];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2_i[31:24];
+                            ansReg = TxFifoCtrlReg2Reg[31:24];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2_i[15:8];
+							ansReg = RxFifoCtrlReg2Reg[15:8];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2_i[31:24];
+                            ansReg = RxFifoCtrlReg2Reg[31:24];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg[15:8];
@@ -1309,16 +1364,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg[15:8];
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3_i[15:8];
+							ansReg = TxFifoCtrlReg3Reg[15:8];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3_i[31:24];
+                            ansReg = TxFifoCtrlReg3Reg[31:24];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3_i[15:8];
+							ansReg = RxFifoCtrlReg3Reg[15:8];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3_i[31:24];
+                            ansReg = RxFifoCtrlReg3Reg[31:24];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg[15:8];
@@ -1339,16 +1394,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg[15:8];
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4_i[15:8];
+							ansReg = TxFifoCtrlReg4Reg[15:8];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4_i[31:24];
+                            ansReg = TxFifoCtrlReg4Reg[31:24];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4_i[15:8];
+							ansReg = RxFifoCtrlReg4Reg[15:8];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4_i[31:24];
+                            ansReg = RxFifoCtrlReg4Reg[31:24];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg[15:8];
@@ -1369,16 +1424,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg[15:8];
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5_i[15:8];
+							ansReg = TxFifoCtrlReg5Reg[15:8];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5_i[31:24];
+                            ansReg = TxFifoCtrlReg5Reg[31:24];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5_i[15:8];
+							ansReg = RxFifoCtrlReg5Reg[15:8];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5_i[31:24];
+                            ansReg = RxFifoCtrlReg5Reg[31:24];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg[15:8];
@@ -1399,16 +1454,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg[15:8];
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6_i[15:8];
+							ansReg = TxFifoCtrlReg6Reg[15:8];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6_i[31:24];
+                            ansReg = TxFifoCtrlReg6Reg[31:24];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6_i[15:8];
+							ansReg = RxFifoCtrlReg6Reg[15:8];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6_i[31:24];
+                            ansReg = RxFifoCtrlReg6Reg[31:24];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg[15:8];
@@ -1445,16 +1500,16 @@ always @(*) begin
 							ansReg = Spi0CsCtrlReg[7:0];
 						end
 						Spi0TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg0_i[7:0];
+							ansReg = TxFifoCtrlReg0Reg[7:0];
 						end
                         Spi0TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg0_i[23:16];
+                            ansReg = TxFifoCtrlReg0Reg[23:16];
                         end
 						Spi0RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg0_i[7:0];
+							ansReg = RxFifoCtrlReg0Reg[7:0];
 						end
                         Spi0RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg0_i[23:16];
+                            ansReg = RxFifoCtrlReg0Reg[23:16];
                         end
 						Spi0TxFifo : begin 
 							ansReg = Spi0TxFifoReg[7:0];
@@ -1475,16 +1530,16 @@ always @(*) begin
 							ansReg = Spi1CsCtrlReg[7:0];
 						end
 						Spi1TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg1_i[7:0];
+							ansReg = TxFifoCtrlReg1Reg[7:0];
 						end
                         Spi1TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg1_i[23:16];
+                            ansReg = TxFifoCtrlReg1Reg[23:16];
                         end
 						Spi1RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg1_i[7:0];
+							ansReg = RxFifoCtrlReg1Reg[7:0];
 						end
                         Spi1RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg1_i[23:16];
+                            ansReg = RxFifoCtrlReg1Reg[23:16];
                         end
 						Spi1TxFifo : begin 
 							ansReg = Spi1TxFifoReg[7:0];
@@ -1505,16 +1560,16 @@ always @(*) begin
 							ansReg = Spi2CsCtrlReg[7:0];
 						end
 						Spi2TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg2_i[7:0];
+							ansReg = TxFifoCtrlReg2Reg[7:0];
 						end
                         Spi2TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg2_i[23:16];
+                            ansReg = TxFifoCtrlReg2Reg[23:16];
                         end
 						Spi2RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg2_i[7:0];
+							ansReg = RxFifoCtrlReg2Reg[7:0];
 						end
                         Spi2RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg2_i[23:16];
+                            ansReg = RxFifoCtrlReg2Reg[23:16];
                         end
 						Spi2TxFifo : begin 
 							ansReg = Spi2TxFifoReg[7:0];
@@ -1535,16 +1590,16 @@ always @(*) begin
 							ansReg = Spi3CsCtrlReg[7:0];
 						end
 						Spi3TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg3_i[7:0];
+							ansReg = TxFifoCtrlReg3Reg[7:0];
 						end
                         Spi3TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg3_i[23:16];
+                            ansReg = TxFifoCtrlReg3Reg[23:16];
                         end
 						Spi3RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg3_i[7:0];
+							ansReg = RxFifoCtrlReg3Reg[7:0];
 						end
                         Spi3RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg3_i[23:16];
+                            ansReg = RxFifoCtrlReg3Reg[23:16];
                         end
 						Spi3TxFifo : begin 
 							ansReg = Spi3TxFifoReg[7:0];
@@ -1565,16 +1620,16 @@ always @(*) begin
 							ansReg = Spi4CsCtrlReg[7:0];
 						end
 						Spi4TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg4_i[7:0];
+							ansReg = TxFifoCtrlReg4Reg[7:0];
 						end
                         Spi4TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg4_i[23:16];
+                            ansReg = TxFifoCtrlReg4Reg[23:16];
                         end
 						Spi4RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg4_i[7:0];
+							ansReg = RxFifoCtrlReg4Reg[7:0];
 						end
                         Spi4RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg4_i[23:16];
+                            ansReg = RxFifoCtrlReg4Reg[23:16];
                         end
 						Spi4TxFifo : begin 
 							ansReg = Spi4TxFifoReg[7:0];
@@ -1595,16 +1650,16 @@ always @(*) begin
 							ansReg = Spi5CsCtrlReg[7:0];
 						end
 						Spi5TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg5_i[7:0];
+							ansReg = TxFifoCtrlReg5Reg[7:0];
 						end
                         Spi5TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg5_i[23:16];
+                            ansReg = TxFifoCtrlReg5Reg[23:16];
                         end
 						Spi5RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg5_i[7:0];
+							ansReg = RxFifoCtrlReg5Reg[7:0];
 						end
                         Spi5RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg5_i[23:16];
+                            ansReg = RxFifoCtrlReg5Reg[23:16];
                         end
 						Spi5TxFifo : begin 
 							ansReg = Spi5TxFifoReg[7:0];
@@ -1625,16 +1680,16 @@ always @(*) begin
 							ansReg = Spi6CsCtrlReg[7:0];
 						end
 						Spi6TxFifoCtrlAddrLsb : begin 
-							ansReg = TxFifoCtrlReg6_i[7:0];
+							ansReg = TxFifoCtrlReg6Reg[7:0];
 						end
                         Spi6TxFifoCtrlAddrMsb : begin 
-                            ansReg = TxFifoCtrlReg6_i[23:16];
+                            ansReg = TxFifoCtrlReg6Reg[23:16];
                         end
 						Spi6RxFifoCtrlAddrLsb : begin 
-							ansReg = RxFifoCtrlReg6_i[7:0];
+							ansReg = RxFifoCtrlReg6Reg[7:0];
 						end
                         Spi6RxFifoCtrlAddrMsb : begin 
-                            ansReg = RxFifoCtrlReg6_i[23:16];
+                            ansReg = RxFifoCtrlReg6Reg[23:16];
                         end
 						Spi6TxFifo : begin 
 							ansReg = Spi6TxFifoReg[7:0];
@@ -1663,7 +1718,6 @@ always @(*) begin
                     ansReg = 0;
                 end
 			endcase
-		end
     end
 end