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@@ -17,15 +17,218 @@ wire [1:0] SmcBe_i;
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reg SmcAoe_i;
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reg [31:0] tb_cnt;
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-
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wire [15:0] smcData;
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+reg mosi1reg;
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+//***********************************************
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+// SPI0 Adresses
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+//***********************************************
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+// Address map for SPI0
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+localparam [10:0] BaseAddr0 = 11'h0;
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+localparam [10:0] Spi0CtrlAddr = BaseAddr0;
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+localparam [10:0] Spi0ClkAddr = (BaseAddr0 + 4)>>1;
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+localparam [10:0] Spi0CsDelayAddr = (BaseAddr0 + 8)>>1;
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+localparam [10:0] Spi0CsCtrlAddr = (BaseAddr0 + 12)>>1;
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+localparam [10:0] Spi0TxFifoCtrlAddr = (BaseAddr0 + 16)>>1;
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+localparam [10:0] Spi0RxFifoCtrlAddr = (BaseAddr0 + 20)>>1;
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+localparam [10:0] Spi0TxFifoAddrL = (BaseAddr0 + 24)>>1;
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+localparam [10:0] Spi0TxFifoAddrM = (BaseAddr0 + 26)>>1;
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+localparam [10:0] Spi0RxFifoAddrL = (BaseAddr0 + 28)>>1;
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+localparam [10:0] Spi0RxFifoAddrM = (BaseAddr0 + 30)>>1;
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+
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+// Data for SPI0CtrlReg
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+
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+
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+//***********************************************
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+// SPI0 Ctrl Reg Data
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+//***********************************************
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+localparam SpiEn0 = 1'b1;//1 for enable, 0 for disable
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+localparam ClockPhase0 = 1'b0;//
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+localparam ClockPolarity0 = 1'b0;//0 for active high, 1 for active low
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+localparam Assel0 = 1'b1;//0 for software control, 1 for hardware control
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+localparam SelSt0 = 1'b1; //1 - assert slave select(low), 0 - deassert slave select(high)
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+localparam Size0 = 2'd2; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
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+localparam Mode0 = 1'b0; // 1 - 4 Mosi, 0 - 1 Mosi
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+localparam LSBF0 = 1'b0; // 1 - LSB first, 0 - MSB first
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+
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+localparam [15:0] Spi0CtrlRegData = {8'h0,LSBF0, Mode0, Size0, SelSt0, Assel0, ClockPolarity0, ClockPhase0, SpiEn0};
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+
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+
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+//***********************************************
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+// SPI0 Clk Reg Data
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+//***********************************************
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+
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+localparam Div = 4'd1; // Custom divider value(input clock frequency = 80 MHz)
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+localparam Mux0 = 1'b1; // 0 - input clock, 1 - MMCM output clock
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+localparam Mux1 = 3'd0; // MMCM output clock number
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+
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+localparam Spi0ClkRegData = {8'h0, Mux1, Mux0, Div};
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+
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+
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+//***********************************************
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+// SPI0 Cs Delay Reg Data
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+//***********************************************
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+localparam Lag0 = 1'b0; //Extended SPI clock lag control, 0 - Disable, 1 - Enable
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+localparam Lead0 = 1'b0; //Extended SPI clock lead control, 0 - Disable, 1 - Enable
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+localparam Stop0 = 6'd0; //Number of clock cycles to wait after CS is deasserted
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+
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+localparam [15:0] Spi0CsDelayRegData = {8'h0, Stop0, Lead0, Lag0};
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+
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+//***********************************************
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+// SPI0 Cs Ctrl Reg Data
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+//***********************************************
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+localparam CS0 = 1'b1; // 1 - device selected, 0 - device deselected
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+localparam CS1 = 1'b1; // 1 - device selected, 0 - device deselected
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+
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+localparam [15:0] Spi0CsCtrlRegData = {14'h0, CS1, CS0};
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+
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+//***********************************************
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+// SPI0 Tx Fifo Ctrl Reg Data
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+//***********************************************
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+localparam RstTxFifo0 = 1'b1; // 1 - Reset Tx FIFO, 0 - Normal operation
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+// at least 5 clock cycles of a slow clock
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+
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+localparam [15:0] Spi0TxFifoCtrlRegDataRstOn = {15'h0, RstTxFifo0};
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+localparam [15:0] Spi0TxFifoCtrlRegDataRstOff = {15'h0, 1'b0};
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+
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+//***********************************************
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+// SPI0 Rx Fifo Ctrl Reg Data
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+//***********************************************
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+localparam RstRxFifo0 = 1'b1; // 1 - Reset Rx FIFO, 0 - Normal operation
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+
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+localparam [15:0] Spi0RxFifoCtrlRegDataRstOn = {15'h0, RstRxFifo0};
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+localparam [15:0] Spi0RxFifoCtrlRegDataRstOff = {15'h0, 1'b0};
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+
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+//***********************************************
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+// SPITXRX Enable Register
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+//***********************************************
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+localparam SpiTxRxEn0 = 1'b1;
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+localparam SpiTxRxEn1 = 1'b0;
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+localparam SpiTxRxEn2 = 1'b0;
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+localparam SpiTxRxEn3 = 1'b0;
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+localparam SpiTxRxEn4 = 1'b0;
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+localparam SpiTxRxEn5 = 1'b0;
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+localparam SpiTxRxEn6 = 1'b0;
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+
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+localparam [15:0] SpiTxRxEnRegData = {8'h0, SpiTxRxEn6, SpiTxRxEn5, SpiTxRxEn4, SpiTxRxEn3, SpiTxRxEn2, SpiTxRxEn1, SpiTxRxEn0};
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+
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+
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+
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+//***********************************************
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+// GPIO Reg Data
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+//***********************************************
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+localparam RstForSbTmsg = 1'b1; // 1 - Reset for SB TMSG, 0 - Normal operation
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+
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+
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+localparam [15:0] GPIORegDataRstOn = {15'h0, RstForSbTmsg};
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+localparam [15:0] GPIORegDataRstOff = {15'h0, 1'b0};
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+
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+
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+//***********************************************
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+// SPI1HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr1 = 11'h50;
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+localparam [10:0] Spi1CtrlAddr = BaseAddr1;
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+localparam [10:0] Spi1ClkAddr = BaseAddr1 + 4;
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+localparam [10:0] Spi1CsDelayAddr = BaseAddr1 + 8;
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+localparam [10:0] Spi1CsCtrlAddr = BaseAddr1 + 12;
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+localparam [10:0] Spi1TxFifoCtrlAddr = BaseAddr1 + 16;
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+localparam [10:0] Spi1RxFifoCtrlAddr = BaseAddr1 + 20;
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+localparam [10:0] Spi1TxFifoAddr = BaseAddr1 + 24;
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+localparam [10:0] Spi1RxFifoAddr = BaseAddr1 + 28;
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+
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+//***********************************************
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+// SPI2HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr2 = 11'hF0;
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+localparam [10:0] Spi2CtrlAddr = BaseAddr2;
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+localparam [10:0] Spi2ClkAddr = BaseAddr2 + 4;
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+localparam [10:0] Spi2CsDelayAddr = BaseAddr2 + 8;
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+localparam [10:0] Spi2CsCtrlAddr = BaseAddr2 + 12;
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+localparam [10:0] Spi2TxFifoCtrlAddr = BaseAddr2 + 16;
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+localparam [10:0] Spi2RxFifoCtrlAddr = BaseAddr2 + 20;
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+localparam [10:0] Spi2TxFifoAddr = BaseAddr2 + 24;
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+localparam [10:0] Spi2RxFifoAddr = BaseAddr2 + 28;
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+
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+//***********************************************
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+// SPI3HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr3 = 11'h140;
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+localparam [10:0] Spi3CtrlAddr = BaseAddr3;
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+localparam [10:0] Spi3ClkAddr = BaseAddr3 + 4;
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+localparam [10:0] Spi3CsDelayAddr = BaseAddr3 + 8;
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+localparam [10:0] Spi3CsCtrlAddr = BaseAddr3 + 12;
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+localparam [10:0] Spi3TxFifoCtrlAddr = BaseAddr3 + 16;
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+localparam [10:0] Spi3RxFifoCtrlAddr = BaseAddr3 + 20;
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+localparam [10:0] Spi3TxFifoAddr = BaseAddr3 + 24;
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+localparam [10:0] Spi3RxFifoAddr = BaseAddr3 + 28;
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+
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+//***********************************************
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+// SPI4HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr4 = 11'h190;
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+localparam [10:0] Spi4CtrlAddr = BaseAddr4;
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+localparam [10:0] Spi4ClkAddr = BaseAddr4 + 4;
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+localparam [10:0] Spi4CsDelayAddr = BaseAddr4 + 8;
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+localparam [10:0] Spi4CsCtrlAddr = BaseAddr4 + 12;
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+localparam [10:0] Spi4TxFifoCtrlAddr = BaseAddr4 + 16;
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+localparam [10:0] Spi4RxFifoCtrlAddr = BaseAddr4 + 20;
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+localparam [10:0] Spi4TxFifoAddr = BaseAddr4 + 24;
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+localparam [10:0] Spi4RxFifoAddr = BaseAddr4 + 28;
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+
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+//***********************************************
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+// SPI5HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr5 = 11'h1E0;
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+localparam [10:0] Spi5CtrlAddr = BaseAddr5;
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+localparam [10:0] Spi5ClkAddr = BaseAddr5 + 4;
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+localparam [10:0] Spi5CsDelayAddr = BaseAddr5 + 8;
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+localparam [10:0] Spi5CsCtrlAddr = BaseAddr5 + 12;
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+localparam [10:0] Spi5TxFifoCtrlAddr = BaseAddr5 + 16;
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+localparam [10:0] Spi5RxFifoCtrlAddr = BaseAddr5 + 20;
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+localparam [10:0] Spi5TxFifoAddr = BaseAddr5 + 24;
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+localparam [10:0] Spi5RxFifoAddr = BaseAddr5 + 28;
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+
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+
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+//***********************************************
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+// SPI5HEADERS
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+//***********************************************
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+localparam [10:0] BaseAddr6 = 11'h230;
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+localparam [10:0] Spi6CtrlAddr = BaseAddr6;
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+localparam [10:0] Spi6ClkAddr = BaseAddr6 + 4;
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+localparam [10:0] Spi6CsDelayAddr = BaseAddr6 + 8;
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+localparam [10:0] Spi6CsCtrlAddr = BaseAddr6 + 12;
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+localparam [10:0] Spi6TxFifoCtrlAddr = BaseAddr6 + 16;
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+localparam [10:0] Spi6RxFifoCtrlAddr = BaseAddr6 + 20;
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+localparam [10:0] Spi6TxFifoAddr = BaseAddr6 + 24;
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+localparam [10:0] Spi6RxFifoAddr = BaseAddr6 + 28;
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+
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+
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+//***********************************************
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+// SPITXRX Enable Reg Adress
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+//***********************************************
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+
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+localparam SpiTxRxEnAddr = 11'h780;
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+
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+//***********************************************
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+// GPIO Reg Adress
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+//***********************************************
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+
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+localparam GPIOAddr = 11'hFF0;
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+
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+//***********************************************
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+// ASSIGNS
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+//***********************************************
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assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
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assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
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assign smcData = SmcData_i;
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+assign mosi1_io = (!Mode0) ? mosi0_o : 1'bz;
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-always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
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+//***********************************************
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+// CLOCK GENERATION
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+//***********************************************
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+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
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S5443_3Top uut (
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.Clk123_i(Clk_i),
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@@ -37,8 +240,8 @@ always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
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.SmcBe_i(SmcBe_i),
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.SmcAoe_i(SmcAoe_i),
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.Led_o(),
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- .Mosi0_o(),
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- .Mosi1_io(),
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+ .Mosi0_o(mosi0_o),
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+ .Mosi1_io(mosi1_io),
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.Mosi2_o(),
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.Mosi3_o(),
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.Ss_o(),
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@@ -56,249 +259,113 @@ always @(posedge Clk_i) begin
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SmcAwe_i <= 1'b1;
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end
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else begin
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- case (tb_cnt)
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- 0: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 1: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 2: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 3: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 4: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 5: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 6: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 7: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 8: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 9: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 10: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 11: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 12: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 13: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 14: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 15: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 16: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 17: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 18: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 19: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 20: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 21: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 22: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 23: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 24: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 25: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 26: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 27: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 28: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 29: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 30: begin
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- SmcAwe_i <= 1'b1;
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+ if (tb_cnt > 0 && tb_cnt <= 44) begin
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+ if (tb_cnt % 2 != 0) begin
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+ SmcAwe_i <= 1'b1;
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+ end
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+ else begin
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+ SmcAwe_i <= 1'b0;
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+ end
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end
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- 31: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 32: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 33: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 34: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 35: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 36: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 37: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 38: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 39: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 40: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 41: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 42: begin
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- SmcAwe_i <= 1'b1;
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- end
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- 43: begin
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- SmcAwe_i <= 1'b0;
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- end
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- 44: begin
|
|
|
- SmcAwe_i <= 1'b1;
|
|
|
- end
|
|
|
- endcase
|
|
|
end
|
|
|
end
|
|
|
|
|
|
+
|
|
|
+
|
|
|
|
|
|
|
|
|
|
|
|
always @(posedge Clk_i) begin
|
|
|
if (Rst_i) begin
|
|
|
SmcAddr_i <= 0;
|
|
|
- SmcData_i <= 0;
|
|
|
end
|
|
|
else begin
|
|
|
+ if (tb_cnt < 27) begin
|
|
|
case (tb_cnt)
|
|
|
0: begin
|
|
|
- SmcAddr_i <= 12'h00f;
|
|
|
- SmcData_i <= 16'h0000;
|
|
|
+ SmcAddr_i <= BaseAddr0;
|
|
|
end
|
|
|
3: begin
|
|
|
- SmcAddr_i <= 12'h7fc;
|
|
|
- SmcData_i <= 16'h0001;
|
|
|
+ SmcAddr_i <= Spi0ClkAddr;
|
|
|
end
|
|
|
5: begin
|
|
|
- SmcAddr_i <= 12'h7fd;
|
|
|
- SmcData_i <= 16'h0000;
|
|
|
+ SmcAddr_i <= Spi0CsDelayAddr;
|
|
|
end
|
|
|
7: begin
|
|
|
- SmcAddr_i <= 12'h7fe;
|
|
|
- SmcAddr_i <= 16'h0000;
|
|
|
- end
|
|
|
- 8: begin
|
|
|
- SmcAddr_i <= 12'h0;
|
|
|
- SmcData_i <= 16'h7f;
|
|
|
- end
|
|
|
- 10: begin
|
|
|
- SmcAddr_i <= 12'h1;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
- end
|
|
|
- 12: begin
|
|
|
- SmcAddr_i <= 12'h2;
|
|
|
- SmcData_i <= 16'hd1;
|
|
|
- end
|
|
|
- 14: begin
|
|
|
- SmcAddr_i <= 12'h3;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ SmcAddr_i <= Spi0CsCtrlAddr;
|
|
|
end
|
|
|
- 16: begin
|
|
|
- SmcAddr_i <= 12'h4;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
- end
|
|
|
- 18: begin
|
|
|
- SmcAddr_i <= 12'h5;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
- end
|
|
|
- 20: begin
|
|
|
- SmcAddr_i <= 12'h6;
|
|
|
- SmcData_i <= 16'h3;
|
|
|
- end
|
|
|
- 22: begin
|
|
|
- SmcAddr_i <= 12'h7;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
- end
|
|
|
- 24: begin
|
|
|
- SmcAddr_i <= 12'h8;
|
|
|
- SmcData_i <= 16'h1;
|
|
|
- end
|
|
|
- 26: begin
|
|
|
- SmcAddr_i <= 12'h9;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
- end
|
|
|
- 28: begin
|
|
|
- SmcAddr_i <= 12'ha;
|
|
|
- SmcData_i <= 16'h1;
|
|
|
- end
|
|
|
- 30: begin
|
|
|
- SmcAddr_i <= 12'hb;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ 9: begin
|
|
|
+ SmcAddr_i <= Spi0TxFifoCtrlAddr;
|
|
|
end
|
|
|
- 32: begin
|
|
|
- SmcAddr_i <= 12'h780;
|
|
|
- SmcData_i <= 16'h1;
|
|
|
+ 11: begin
|
|
|
+ SmcAddr_i <= Spi0RxFifoCtrlAddr;
|
|
|
end
|
|
|
- 34: begin
|
|
|
- SmcAddr_i <= 12'h781;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ 19 : begin
|
|
|
+ SmcAddr_i <= Spi0TxFifoCtrlAddr;
|
|
|
end
|
|
|
- 36: begin
|
|
|
- SmcAddr_i <= 12'h7f8;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ 21 : begin
|
|
|
+ SmcAddr_i <= Spi0RxFifoCtrlAddr;
|
|
|
end
|
|
|
- 38: begin
|
|
|
- SmcAddr_i <= 12'h7f9;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ 23 : begin
|
|
|
+ SmcAddr_i <= SpiTxRxEnAddr;
|
|
|
end
|
|
|
- 40: begin
|
|
|
- SmcAddr_i <= 12'h00c;
|
|
|
- SmcData_i <= 16'h1;
|
|
|
+ endcase
|
|
|
end
|
|
|
- 42: begin
|
|
|
- SmcAddr_i <= 12'h00d;
|
|
|
- SmcData_i <= 16'h0;
|
|
|
+ else begin
|
|
|
+ if (tb_cnt % 2 != 0) begin
|
|
|
+ SmcAddr_i <= Spi0TxFifoAddrL;
|
|
|
+ end
|
|
|
+ else begin
|
|
|
+ SmcAddr_i <= Spi0TxFifoAddrM;
|
|
|
+ end
|
|
|
end
|
|
|
- endcase
|
|
|
end
|
|
|
end
|
|
|
|
|
|
|
|
|
+always @(posedge Clk_i) begin
|
|
|
+ if (Rst_i) begin
|
|
|
+ SmcData_i <= 16'h0;
|
|
|
+ end
|
|
|
+ else begin
|
|
|
+ if (tb_cnt < 27 ) begin
|
|
|
+ case (tb_cnt)
|
|
|
+ 0 : begin
|
|
|
+ SmcData_i <= Spi0CtrlRegData;
|
|
|
+ end
|
|
|
+ 3 : begin
|
|
|
+ SmcData_i <= Spi0ClkRegData;
|
|
|
+ end
|
|
|
+ 5 : begin
|
|
|
+ SmcData_i <= Spi0CsDelayRegData;
|
|
|
+ end
|
|
|
+ 7 : begin
|
|
|
+ SmcData_i <= Spi0CsCtrlRegData;
|
|
|
+ end
|
|
|
+ 9 : begin
|
|
|
+ SmcData_i <= Spi0TxFifoCtrlRegDataRstOn;
|
|
|
+ end
|
|
|
+ 11 : begin
|
|
|
+ SmcData_i <= Spi0RxFifoCtrlRegDataRstOn;
|
|
|
+ end
|
|
|
+ 19 : begin
|
|
|
+ SmcData_i <= Spi0TxFifoCtrlRegDataRstOff;
|
|
|
+ end
|
|
|
+ 21 : begin
|
|
|
+ SmcData_i <= Spi0RxFifoCtrlRegDataRstOff;
|
|
|
+ end
|
|
|
+ 23 : begin
|
|
|
+ SmcData_i <= SpiTxRxEnRegData;
|
|
|
+ end
|
|
|
+ endcase
|
|
|
+ end
|
|
|
+ else begin
|
|
|
+ else begin
|
|
|
+ SmcData_i <= $urandom_range(0, 8'hFF);
|
|
|
+ end
|
|
|
+ end
|
|
|
+ end
|
|
|
+end
|
|
|
|
|
|
always @(posedge Clk_i) begin
|
|
|
if (Rst_i) begin
|
|
|
@@ -309,34 +376,12 @@ always @(posedge Clk_i) begin
|
|
|
end
|
|
|
end
|
|
|
|
|
|
-
|
|
|
-// always @(*) begin
|
|
|
-// txNextState = IDLE;
|
|
|
-// case(txCurrState)
|
|
|
-// IDLE : begin
|
|
|
-// if (txWork) begin
|
|
|
-// txNextState = CMD;
|
|
|
-// end
|
|
|
-// else begin
|
|
|
-// txNextState = IDLE;
|
|
|
-// end
|
|
|
-// end
|
|
|
-// WRITE : begin
|
|
|
-// if () begin
|
|
|
-// txNextState = WRITE;
|
|
|
-// end
|
|
|
-// else begin
|
|
|
-// txNextState = IDLE;
|
|
|
-// end
|
|
|
-// end
|
|
|
-
|
|
|
-
|
|
|
initial begin
|
|
|
Clk_i = 1'b0;
|
|
|
Rst_i = 1'b1;
|
|
|
SmcAre_i = 1'b1;
|
|
|
SmcAoe_i = 1'b1;
|
|
|
- #(CLK_PERIOD*10) Rst_i = 1'b0;
|
|
|
+ #(CLK_PERIOD*300) Rst_i = 1'b0;
|
|
|
|
|
|
|
|
|
|
Anatoliy Chigirinskiy