Рефакторинг топ модуля

sources_1/new/S5443_3Top.v

@@ -18,20 +18,17 @@
 // Additional Comments:
 // 
 //////////////////////////////////////////////////////////////////////////////////
-
-
 module S5443_3Top 
 #(
-	parameter CmdRegWidth = 32,
-	parameter AddrRegWidth = 12,
+	parameter CMD_REG_WIDTH = 32,
+	parameter ADDR_REG_WIDTH = 12,
 	parameter STAGES = 3,
-	parameter SpiNum = 7
-
+	parameter SPI_NUM = 7
 )
 (
 	input Clk123_i,
-	input [AddrRegWidth-2:0] SmcAddr_i,
-	inout [CmdRegWidth/2-1:0] SmcData_io,
+	input [ADDR_REG_WIDTH-2:0] SmcAddr_i,
+	inout [CMD_REG_WIDTH/2-1:0] SmcData_io,
 	
 	input SmcAwe_i,
 	input SmcAmsN_i,
@@ -39,219 +36,218 @@ module S5443_3Top
 	input SmcAre_i,
 	input [1:0] SmcBe_i,
 	input SmcAoe_i,
-	input [SpiNum-1:0] Ld_i,
-
-	output  Led_o,
-   
-	output  [SpiNum-1:0] Mosi0_o, 
-	inout   [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; 
-	output  [SpiNum-1:0] Mosi2_o,
-	output  [SpiNum-2:0] Mosi3_o,
-	output  [SpiNum-1:0] Ss_o,
-	output  [SpiNum-1:0] SsFlash_o,
-	output  [SpiNum-1:0] Sck_o,
-	output  [SpiNum-1:0] SpiRst_o,
-	output  [SpiNum-1:0] SpiDir_o,
+	input [SPI_NUM-1:0] Ld_i,
+
+	output Led_o,
+
+	output [SPI_NUM-1:0] Mosi0_o, 
+	inout  [SPI_NUM-1:0] Mosi1_io,	//inout: when RSPI mode, input; when QSPI mode output; 
+	output [SPI_NUM-1:0] Mosi2_o,
+	output [SPI_NUM-2:0] Mosi3_o,
+	output [SPI_NUM-1:0] Ss_o,
+	output [SPI_NUM-1:0] SsFlash_o,
+	output [SPI_NUM-1:0] Sck_o,
+	output [SPI_NUM-1:0] SpiRst_o,
+	output [SPI_NUM-1:0] SpiDir_o,
 	output LoCsReg_o,
-	output  LD_o
-
+	output LD_o
 );
 
 //================================================================================
 //  REG/WIRE
 //================================================================================
 	wire clk80;
-	wire [AddrRegWidth-1:0] addrExt;
+	wire [ADDR_REG_WIDTH-1:0] addrExt;
 
-	wire [SpiNum-1:0] mosi3;
-	wire [SpiNum-1:0] txEn;
+	wire [SPI_NUM-1:0] mosi3;
+	wire [SPI_NUM-1:0] txEn;
 
 	wire initRst;
 	wire gclk;
 
-	wire [0:7] baudRate [SpiNum-1:0];
+	wire [0:7] baudRate [SPI_NUM-1:0];
 	
-	wire [0:31] txFifoCtrlReg [SpiNum-1:0];
-	wire [0:31] rxFifoCtrlReg [SpiNum-1:0];
+	wire [0:31] txFifoCtrlReg [SPI_NUM-1:0];
+	wire [0:31] rxFifoCtrlReg [SPI_NUM-1:0];
 	
 	//InitRst
 	wire rst80;
 
 	//SPI0
-	wire [CmdRegWidth-1:0] spi0Ctrl;
-	wire [CmdRegWidth-1:0] spi0Clk;
-	wire [CmdRegWidth-1:0] spi0CsDelay;
-	wire [CmdRegWidth-1:0] spi0CsCtrl;
-	wire [CmdRegWidth-1:0] spi0TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi0RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi0TxFifo;
-	wire [CmdRegWidth-1:0] spi0RxFifo;
-	wire [CmdRegWidth-1:0] spi0TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi0RxFifoCtrlReg;
-	
-	wire [CmdRegWidth-1:0] spi0CtrlRR;
-	wire [CmdRegWidth-1:0] spi0ClkRR;
-	wire [CmdRegWidth-1:0] spi0CsDelayRR;
-	wire [CmdRegWidth-1:0] spi0CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi0TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi0RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi0Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi0Clk;
+	wire [CMD_REG_WIDTH-1:0] spi0CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi0CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi0TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi0RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi0TxFifo;
+	wire [CMD_REG_WIDTH-1:0] spi0RxFifo;
+	wire [CMD_REG_WIDTH-1:0] spi0TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi0RxFifoCtrlReg;
+	
+	wire [CMD_REG_WIDTH-1:0] spi0CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi0ClkRR;
+	wire [CMD_REG_WIDTH-1:0] spi0CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi0CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi0TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi0RxFifoCtrlRR;
 	
 	//SPI1
-	wire [CmdRegWidth-1:0] spi1Ctrl;
-	wire [CmdRegWidth-1:0] spi1Clk;
-	wire [CmdRegWidth-1:0] spi1CsDelay;
-	wire [CmdRegWidth-1:0] spi1CsCtrl;
-	wire [CmdRegWidth-1:0] spi1TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi1RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi1TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi1RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi1CtrlRR;
-	wire [CmdRegWidth-1:0] spi1CsDelayRR;
-	wire [CmdRegWidth-1:0] spi1CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi1TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi1RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi1Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi1Clk;
+	wire [CMD_REG_WIDTH-1:0] spi1CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi1CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi1TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi1RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi1TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi1RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi1CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi1CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi1CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi1TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi1RxFifoCtrlRR;
 
 	//SPI2
-	wire [CmdRegWidth-1:0] spi2Ctrl;
-	wire [CmdRegWidth-1:0] spi2Clk;
-	wire [CmdRegWidth-1:0] spi2CsDelay;
-	wire [CmdRegWidth-1:0] spi2CsCtrl;
-	wire [CmdRegWidth-1:0] spi2TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi2RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi2TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi2RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi2CtrlRR;
-	wire [CmdRegWidth-1:0] spi2CsDelayRR;
-	wire [CmdRegWidth-1:0] spi2CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi2TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi2RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi2Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi2Clk;
+	wire [CMD_REG_WIDTH-1:0] spi2CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi2CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi2TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi2RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi2TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi2RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi2CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi2CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi2CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi2TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi2RxFifoCtrlRR;
 
 	//SPI3
-	wire [CmdRegWidth-1:0] spi3Ctrl;
-	wire [CmdRegWidth-1:0] spi3Clk;
-	wire [CmdRegWidth-1:0] spi3CsDelay;
-	wire [CmdRegWidth-1:0] spi3CsCtrl;
-	wire [CmdRegWidth-1:0] spi3TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi3RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi3TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi3RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi3CtrlRR;
-	wire [CmdRegWidth-1:0] spi3ClkRR;
-	wire [CmdRegWidth-1:0] spi3CsDelayRR;
-	wire [CmdRegWidth-1:0] spi3CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi3TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi3RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi3Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi3Clk;
+	wire [CMD_REG_WIDTH-1:0] spi3CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi3CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi3TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi3RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi3TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi3RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi3CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi3ClkRR;
+	wire [CMD_REG_WIDTH-1:0] spi3CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi3CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi3TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi3RxFifoCtrlRR;
 
 	//SPI4
-	wire [CmdRegWidth-1:0] spi4Ctrl;
-	wire [CmdRegWidth-1:0] spi4Clk;
-	wire [CmdRegWidth-1:0] spi4CsDelay;
-	wire [CmdRegWidth-1:0] spi4CsCtrl;
-	wire [CmdRegWidth-1:0] spi4TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi4RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi4TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi4RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi4CtrlRR;
-	wire [CmdRegWidth-1:0] spi4ClkRR;
-	wire [CmdRegWidth-1:0] spi4CsDelayRR;
-	wire [CmdRegWidth-1:0] spi4CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi4TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi4RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi4Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi4Clk;
+	wire [CMD_REG_WIDTH-1:0] spi4CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi4CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi4TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi4RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi4TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi4RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi4CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi4ClkRR;
+	wire [CMD_REG_WIDTH-1:0] spi4CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi4CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi4TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi4RxFifoCtrlRR;
 	
 	//SPI5
-	wire [CmdRegWidth-1:0] spi5Ctrl;
-	wire [CmdRegWidth-1:0] spi5Clk;
-	wire [CmdRegWidth-1:0] spi5CsDelay;
-	wire [CmdRegWidth-1:0] spi5CsCtrl;
-	wire [CmdRegWidth-1:0] spi5TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi5RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi5TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi5RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi5CtrlRR;
-	wire [CmdRegWidth-1:0] spi5ClkRR;
-	wire [CmdRegWidth-1:0] spi5CsDelayRR;
-	wire [CmdRegWidth-1:0] spi5CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi5TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi5RxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi5Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi5Clk;
+	wire [CMD_REG_WIDTH-1:0] spi5CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi5CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi5TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi5RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi5TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi5RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi5CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi5ClkRR;
+	wire [CMD_REG_WIDTH-1:0] spi5CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi5CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi5TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi5RxFifoCtrlRR;
 
 	//SPI6
-	wire [CmdRegWidth-1:0] spi6Ctrl;
-	wire [CmdRegWidth-1:0] spi6Clk;
-	wire [CmdRegWidth-1:0] spi6CsDelay;
-	wire [CmdRegWidth-1:0] spi6CsCtrl;
-	wire [CmdRegWidth-1:0] spi6TxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi6RxFifoCtrl;
-	wire [CmdRegWidth-1:0] spi6TxFifoCtrlReg;
-	wire [CmdRegWidth-1:0] spi6RxFifoCtrlReg;
-
-	wire [CmdRegWidth-1:0] spi6CtrlRR;
-	wire [CmdRegWidth-1:0] spi6ClkRR;
-	wire [CmdRegWidth-1:0] spi6CsDelayRR;
-	wire [CmdRegWidth-1:0] spi6CsCtrlRR;
-	wire [CmdRegWidth-1:0] spi6TxFifoCtrlRR;
-	wire [CmdRegWidth-1:0] spi6RxFifoCtrlRR;
-	
-	wire [CmdRegWidth-1:0] spiTxRxEn;
-	wire [CmdRegWidth-1:0] Gpio;
-	
-	wire [AddrRegWidth-1:0]	toRegMapAddr;
-	wire [CmdRegWidth/2-1:0]	toRegMapData;
+	wire [CMD_REG_WIDTH-1:0] spi6Ctrl;
+	wire [CMD_REG_WIDTH-1:0] spi6Clk;
+	wire [CMD_REG_WIDTH-1:0] spi6CsDelay;
+	wire [CMD_REG_WIDTH-1:0] spi6CsCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi6TxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi6RxFifoCtrl;
+	wire [CMD_REG_WIDTH-1:0] spi6TxFifoCtrlReg;
+	wire [CMD_REG_WIDTH-1:0] spi6RxFifoCtrlReg;
+
+	wire [CMD_REG_WIDTH-1:0] spi6CtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi6ClkRR;
+	wire [CMD_REG_WIDTH-1:0] spi6CsDelayRR;
+	wire [CMD_REG_WIDTH-1:0] spi6CsCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi6TxFifoCtrlRR;
+	wire [CMD_REG_WIDTH-1:0] spi6RxFifoCtrlRR;
+	
+	wire [CMD_REG_WIDTH-1:0] spiTxRxEn;
+	wire [CMD_REG_WIDTH-1:0] Gpio;
+	
+	wire [ADDR_REG_WIDTH-1:0]	toRegMapAddr;
+	wire [CMD_REG_WIDTH/2-1:0]	toRegMapData;
 	wire toRegMapVal;
 	
-	wire [SpiNum-1:0]	toFifoVal;
-	wire [CmdRegWidth*SpiNum-1:0]	toFifoData;
+	wire [SPI_NUM-1:0]	toFifoVal;
+	wire [CMD_REG_WIDTH*SPI_NUM-1:0] toFifoData;
 	
-	wire [SpiNum-1:0]	toSpiVal;
-	wire [0:31]	toSpiData [SpiNum-1:0];
+	wire [SPI_NUM-1:0]	toSpiVal;
+	wire [0:31]	toSpiData [SPI_NUM-1:0];
 	
-	wire [0:1] widthSel [SpiNum-1:0];
-	wire [SpiNum-1:0] clockPol;
-	wire [SpiNum-1:0] clockPhase;
-	wire [SpiNum-1:0] endianSel;
-	wire [SpiNum-1:0] selSt;
-	wire [SpiNum-1:0] spiMode;
+	wire [0:1] widthSel [SPI_NUM-1:0];
+	wire [SPI_NUM-1:0] clockPol;
+	wire [SPI_NUM-1:0] clockPhase;
+	wire [SPI_NUM-1:0] endianSel;
+	wire [SPI_NUM-1:0] selSt;
+	wire [SPI_NUM-1:0] spiMode;
 	
-	wire [0:5] stopDelay [SpiNum-1:0];
-	wire [SpiNum-1:0] leadx;
-	wire [SpiNum-1:0] lag; 
-	wire [SpiNum-1:0] fifoRxRst;
-	wire [SpiNum-1:0] fifoTxRst;
-	wire [SpiNum-1:0] fifoRxRstRdPtr;
-	wire [SpiNum-1:0] fifoTxRstWrPtr;
-	wire [0:7]  wordCntTx [SpiNum-1:0];
-	wire [0:7]  wordCntRx [SpiNum-1:0];
+	wire [0:5] stopDelay [SPI_NUM-1:0];
+	wire [SPI_NUM-1:0] leadx;
+	wire [SPI_NUM-1:0] lag; 
+	wire [SPI_NUM-1:0] fifoRxRst;
+	wire [SPI_NUM-1:0] fifoTxRst;
+	wire [SPI_NUM-1:0] fifoRxRstRdPtr;
+	wire [SPI_NUM-1:0] fifoTxRstWrPtr;
+	wire [0:7]  wordCntTx [SPI_NUM-1:0];
+	wire [0:7]  wordCntRx [SPI_NUM-1:0];
 	
-	wire [SpiNum-1:0] chipSelFpga;
-	wire [SpiNum-1:0] chipSelFlash;
+	wire [SPI_NUM-1:0] chipSelFpga;
+	wire [SPI_NUM-1:0] chipSelFlash;
 	
-	wire [SpiNum-1:0] assel;
+	wire [SPI_NUM-1:0] assel;
 	
-	wire	[SpiNum-1:0]	spiClkBus;
+	wire	[SPI_NUM-1:0]	spiClkBus;
 
 	//RxFifo 
-	wire [0:31] dataFromRxFifo [SpiNum-1:0];
+	wire [0:31] dataFromRxFifo [SPI_NUM-1:0];
 	
-	wire [CmdRegWidth/2-1:0] muxedData;
+	wire [CMD_REG_WIDTH/2-1:0] muxedData;
 	
 	wire smcValComb; 
-	wire [CmdRegWidth/2-1:0]	ansData;
+	wire [CMD_REG_WIDTH/2-1:0]	ansData;
 
 	wire requestToFifo;
 
-	wire [SpiNum-1:0] spiEn;
+	wire [SPI_NUM-1:0] spiEn;
 
-	wire [SpiNum-1:0] ldReg;
+	wire [SPI_NUM-1:0] ldReg;
 
-	wire [SpiNum-1:0] ssW;
+	wire [SPI_NUM-1:0] ssW;
 
-	//================================================================================
-	//  ASSIGNMENTS
-	//================================================================================
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 	assign addrExt = {SmcAddr_i, 1'b0};
 	assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
 	assign txEn = spiTxRxEn[6:0];
@@ -264,8 +260,8 @@ module S5443_3Top
 	// assign Mosi3_o[5] = mosi3[5];
 	assign Mosi3_o[5] = mosi3[6];// Mosi6 
 
-	assign Ss_o			= ssW;
-	assign LoCsReg_o	= ssW[5];
+	assign Ss_o		 = ssW;
+	assign LoCsReg_o = ssW[5];
 	
 	assign widthSel[0] = spi0CtrlRR[6:5];
 	assign widthSel[1] = spi1CtrlRR[6:5];
@@ -437,13 +433,13 @@ module S5443_3Top
 	assign chipSelFlash[5] = spi5CsCtrlRR[1];
 	assign chipSelFlash[6] = spi6CsCtrlRR[1];
 	
-	assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ;
-	assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ;
-	assign SpiDir_o[2] = (spiMode[2])? 1'b1 : 1'b0 ;
-	assign SpiDir_o[3] = (spiMode[3])? 1'b1 : 1'b0 ;
-	assign SpiDir_o[4] = (spiMode[4])? 1'b1 : 1'b0 ;
+	assign SpiDir_o[0] = (spiMode[0]) ? 1'b1 : 1'b0 ;
+	assign SpiDir_o[1] = (spiMode[1]) ? 1'b1 : 1'b0 ;
+	assign SpiDir_o[2] = (spiMode[2]) ? 1'b1 : 1'b0 ;
+	assign SpiDir_o[3] = (spiMode[3]) ? 1'b1 : 1'b0 ;
+	assign SpiDir_o[4] = (spiMode[4]) ? 1'b1 : 1'b0 ;
 	assign SpiDir_o[5] = 1'b1;
-	assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
+	assign SpiDir_o[6] = (spiMode[6]) ? 1'b1 : 1'b0 ;
 	
 	assign spi0TxFifoCtrlReg = txFifoCtrlReg[0];
 	assign spi1TxFifoCtrlReg = txFifoCtrlReg[1];
@@ -463,10 +459,9 @@ module S5443_3Top
 	
 	assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i) ? muxedData : 16'bz;
 	
-	//================================================================================
-	//  CODING
-	//================================================================================	
-	
+//================================================================================
+//  CODING
+//================================================================================	
 	SmcAnsMux SmcAnsMux
 	(
 		.Clk_i				(gclk),
@@ -490,8 +485,8 @@ module S5443_3Top
 	);
 	
 	BUFG BUFG_inst (
-	   .O	(gclk), // 1-bit output: Clock output
-	   .I	(Clk123_i)  // 1-bit input: Clock input
+		.O	(gclk),		// 1-bit output: Clock output
+		.I	(Clk123_i)	// 1-bit input: Clock input
 	);
 	
 	SmcInDataMux SmcInDataMux
@@ -514,9 +509,9 @@ module S5443_3Top
 	);
 	
 	CDC #(
-		.WIDTH				(CmdRegWidth),
+		.WIDTH				(CMD_REG_WIDTH),
 		.STAGES				(STAGES),
-		.SPI_NUM			(SpiNum)
+		.SPI_NUM			(SPI_NUM)
 
 	) synchronizer(
 		.ClkFast_i			(gclk),
@@ -697,118 +692,117 @@ module S5443_3Top
 	);
 	
 	ClkManager #(
-		.SpiNum(SpiNum),
+		.SPI_NUM(SPI_NUM),
 		.STAGES(STAGES) 
 	) ClkManager
 	(
-		.Clk_i(gclk),
-		.Rst_i(initRst),
-		.Rst80_i(rst80),
-		.BaudRate0_i(baudRate[0]),
-		.BaudRate1_i(baudRate[1]),
-		.BaudRate2_i(baudRate[2]),
-		.BaudRate3_i(baudRate[3]),
-		.BaudRate4_i(baudRate[4]),
-		.BaudRate5_i(baudRate[5]),
-		.BaudRate6_i(baudRate[6]),
-		.Clk80_o(clk80),
-		.SpiClk_o(spiClkBus)
+		.Clk_i			(gclk),
+		.Rst_i			(initRst),
+		.Rst80_i		(rst80),
+		.BaudRate0_i	(baudRate[0]),
+		.BaudRate1_i	(baudRate[1]),
+		.BaudRate2_i	(baudRate[2]),
+		.BaudRate3_i	(baudRate[3]),
+		.BaudRate4_i	(baudRate[4]),
+		.BaudRate5_i	(baudRate[5]),
+		.BaudRate6_i	(baudRate[6]),
+		.Clk80_o		(clk80),
+		.SpiClk_o		(spiClkBus)
 	);
 	 
 	genvar i;
 	generate 
-		for (i = 0; i < SpiNum; i = i+1) begin : SpiSubSystem
+		for (i = 0; i < SPI_NUM; i = i + 1) begin : SpiSubSystem
 
 			SpiSubSystem #(
-				.STAGES(STAGES),
-				.CMD_REG_WIDTH(CmdRegWidth),
-				.ADDR_REG_WIDTH(AddrRegWidth),
-				.WIDTH(1),
-				.FIFO_NUM(SpiNum)
+				.STAGES				(STAGES),
+				.CMD_REG_WIDTH		(CMD_REG_WIDTH),
+				.ADDR_REG_WIDTH		(ADDR_REG_WIDTH),
+				.WIDTH				(1),
+				.FIFO_NUM			(SPI_NUM)
 			) SpiSubSystem(
-				.Clk123_i(gclk),
-				.SpiClk_i(spiClkBus[i]),
-
-				.TxEn_i(txEn[i]),
-
-				.FifoRxRst_i(fifoRxRst[i]),
-				.FifoTxRst_i(fifoTxRst[i]),
-				.FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]),
-				.FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]),
-				.SmcAre_i(SmcAre_i),
-				.SmcAwe_i(SmcAwe_i),
-				.SmcAddr_i(addrExt),
-				.ToFifoVal_i(toFifoVal[i]),
-				.ToFifoData_i(toFifoData[32*i+:32]),
-				.WidthSel_i(widthSel[i]),
-				.PulsePol_i(clockPol[i]),
-				.ClockPhase_i(clockPhase[i]),
-				.EndianSel_i(endianSel[i]),
-				.ChipSelFlash_i(chipSelFlash[i]),
-				.ChipSelFpga_i(chipSelFpga[i]),
-				.Assel_i(assel[i]),
-				.Lag_i(lag[i]),
-				.Lead_i(leadx[i]),
-				.SelSt_i(selSt[i]),
-				.Stop_i(stopDelay[i]),
-				.SpiMode_i(spiMode[i]),
-				.SpiEn_i(spiEn[i]),
+				.Clk123_i			(gclk),
+				.SpiClk_i			(spiClkBus[i]),
+
+				.TxEn_i				(txEn[i]),
+
+				.FifoRxRst_i		(fifoRxRst[i]),
+				.FifoTxRst_i		(fifoTxRst[i]),
+				.FifoRxRstRdPtr_i	(fifoRxRstRdPtr[i]),
+				.FifoTxRstWrPtr_i	(fifoTxRstWrPtr[i]),
+				.SmcAre_i			(SmcAre_i),
+				.SmcAwe_i			(SmcAwe_i),
+				.SmcAddr_i			(addrExt),
+				.ToFifoVal_i		(toFifoVal[i]),
+				.ToFifoData_i		(toFifoData[32*i+:32]),
+				.WidthSel_i			(widthSel[i]),
+				.PulsePol_i			(clockPol[i]),
+				.ClockPhase_i		(clockPhase[i]),
+				.EndianSel_i		(endianSel[i]),
+				.ChipSelFlash_i		(chipSelFlash[i]),
+				.ChipSelFpga_i		(chipSelFpga[i]),
+				.Assel_i			(assel[i]),
+				.Lag_i				(lag[i]),
+				.Lead_i				(leadx[i]),
+				.SelSt_i			(selSt[i]),
+				.Stop_i				(stopDelay[i]),
+				.SpiMode_i			(spiMode[i]),
+				.SpiEn_i			(spiEn[i]),
 				
-				.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
-				.RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
-				.DataFromRxFifo_o(dataFromRxFifo[i]),
-
-				.Sck_o(Sck_o[i]),
-				.Ss_o(ssW[i]),
-				.SsFlash_o(SsFlash_o[i]),
-				.Mosi0_o(Mosi0_o[i]),
-				.Mosi1_io(Mosi1_io[i]),
-				.Mosi2_o(Mosi2_o[i]),
-				.Mosi3_o(mosi3[i])
+				.TxFifoCtrlReg_o	(txFifoCtrlReg[i]),
+				.RxFifoCtrlReg_o	(rxFifoCtrlReg[i]),
+				.DataFromRxFifo_o	(dataFromRxFifo[i]),
+
+				.Sck_o				(Sck_o[i]),
+				.Ss_o				(ssW[i]),
+				.SsFlash_o			(SsFlash_o[i]),
+				.Mosi0_o			(Mosi0_o[i]),
+				.Mosi1_io			(Mosi1_io[i]),
+				.Mosi2_o			(Mosi2_o[i]),
+				.Mosi3_o			(mosi3[i])
 			);
 			
 			xpm_cdc_single #(
-				.DEST_SYNC_FF(3),
-				.INIT_SYNC_FF(0),
-				.SIM_ASSERT_CHK(0),
-				.SRC_INPUT_REG(1)
+				.DEST_SYNC_FF		(3),
+				.INIT_SYNC_FF		(0),
+				.SIM_ASSERT_CHK		(0),
+				.SRC_INPUT_REG		(1)
 			)
 			xpm_cdc_single_inst(
-				.dest_out(ldReg[i]),
+				.dest_out	(ldReg[i]),
 
-				.dest_clk(gclk),
-				.src_clk(spiClkBus[i]),
-				.src_in(Ld_i[i])
+				.dest_clk	(gclk),
+				.src_clk	(spiClkBus[i]),
+				.src_in		(Ld_i[i])
 			);
 		end
 	endgenerate
-  //================================================================================
-	//  FOR DEBUG 
-	//================================================================================	
-	// QuadSPIs QuadSPIs (
-	//     .Clk_i(spiClkBus[0]),
-	//     .Rst_i(initRstGen[0] | !spiMode[0]),
-	//     .Sck_i(sckQ[0]),
-	//     .Ss_i(ssQ[0]),
-	//     .Mosi0_i(mosi0Q[0]),
-	//     .Mosi1_i(mosi1[0]),
-	//     .Mosi2_i(mosi2[0]),
-	//     .Mosi3_i(mosi3[0]),
-	//     .WidthSel_i(widthSel[0]),
-	//     .SELST_i(selSt[0]),
-	//     .EndianSel_i(endianSel[0])
-	// );
+	
+	/////////////FOR DEBUG///////////// 
+	/* QuadSPIs QuadSPIs (
+		.Clk_i(spiClkBus[0]),
+		.Rst_i(initRstGen[0] | !spiMode[0]),
+		.Sck_i(sckQ[0]),
+		.Ss_i(ssQ[0]),
+		.Mosi0_i(mosi0Q[0]),
+		.Mosi1_i(mosi1[0]),
+		.Mosi2_i(mosi2[0]),
+		.Mosi3_i(mosi3[0]),
+		.WidthSel_i(widthSel[0]),
+		.SELST_i(selSt[0]),
+		.EndianSel_i(endianSel[0])
+	);*/
 	
 	InitRst InitRst_inst
-	 (
+	(
 		.clk_i(gclk),
 		.signal_o(initRst)
 	);
 
-	 InitRst Rst80_inst
-	 (
+	InitRst Rst80_inst
+	(
 		.clk_i(clk80),
 		.signal_o(rst80)
 	);
 	
-	endmodule
+endmodule