Исправлен SPIm, в xdc-файл добавлен сигнал управления MOSI1/MISO0

.gitignore

@@ -0,0 +1,33 @@
+/sources_1/new/MMCM/cmake-build-debug/
+
+#Ignore thumbnails created by Windows
+Thumbs.db
+#Ignore files built by Visual Studio
+*.obj
+*.exe
+*.pdb
+*.user
+*.aps
+*.pch
+*.vspscc
+*_i.c
+*_p.c
+*.ncb
+*.suo
+*.tlb
+*.tlh
+*.bak
+*.cache
+*.ilk
+*.log
+[Bb]in
+[Dd]ebug*/
+*.lib
+*.sbr
+obj/
+[Rr]elease*/
+_ReSharper*/
+[Tt]est[Rr]esult*
+.vs/
+#Nuget packages folder
+packages/

QuadSPI/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

QuadSPI/QuadSPIs.v

@@ -0,0 +1,221 @@
+module QuadSPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input Mosi1_i,
+    input Mosi2_i,
+    input Mosi3_i,
+
+    input [1:0] WidthSel_i,
+    input EnEdge_i,
+    input PulsePol_i,
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR; 
+reg SckReg; 
+reg [7:0] addrReg;
+reg [7:0] shiftReg0;
+reg [7:0] shiftReg1;
+reg [7:0] shiftReg2;
+
+reg [7:0] shiftReg0M;
+reg [7:0] shiftReg1M;
+reg [7:0] shiftReg2M;
+reg [7:0] addrRegM;
+
+reg Sck;
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(*) begin 
+    if (PulsePol_i) begin 
+        if (EnEdge_i) begin 
+            assign Sck = ~Sck_i;
+        end
+        else begin 
+            assign Sck = Sck_i;
+        end
+    end
+    else begin 
+        if (EnEdge_i) begin 
+            assign Sck = Sck_i;
+        end
+        else begin 
+            assign Sck = ~Sck_i;
+        end
+    end
+end
+always @(posedge Sck) begin 
+    if (Rst_i) begin 
+        SckReg <= 1'b0;
+    end
+    else begin 
+        SckReg <= Sck;
+    end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin
+        addrRegM = 8'h0; 
+        shiftReg0M = 8'h0;
+        shiftReg1M = 8'h0;
+        shiftReg2M = 8'h0;
+    end
+    else begin 
+        case(WidthSel_i)  
+             0: begin 
+                addrRegM   = addrReg  [1:0];
+                shiftReg0M = shiftReg0[1:0];
+                shiftReg1M = shiftReg1[1:0];
+                shiftReg2M = shiftReg2[1:0];
+            end
+            1: begin 
+                addrRegM   = addrReg  [3:0];
+                shiftReg0M = shiftReg0[3:0];
+                shiftReg1M = shiftReg1[3:0];
+                shiftReg2M = shiftReg2[3:0];
+            end
+            2: begin 
+                addrRegM   = addrReg  [5:0];
+                shiftReg0M = shiftReg0[5:0];
+                shiftReg1M = shiftReg1[5:0];
+                shiftReg2M = shiftReg2[5:0];
+            end
+            3: begin 
+                addrRegM   = addrReg  [7:0];
+                shiftReg0M = shiftReg0[7:0];
+                shiftReg1M = shiftReg1[7:0];
+                shiftReg2M = shiftReg2[7:0];
+            end
+        endcase
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 24'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+        end
+        else begin 
+            Data_o <= 24'h0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 8'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Addr_o <= addrRegM;
+        end
+    end
+end
+
+
+always @(posedge Sck) begin 
+    if (Rst_i) begin 
+        shiftReg0 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+        end
+        else begin 
+            shiftReg0 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        shiftReg1 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg1 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        shiftReg2 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg2 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        addrReg <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            addrReg <= {addrReg[6:0], Mosi3_i};
+        end
+        else begin 
+            addrReg <= 8'h0;
+        end
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (ssReg && !ssRegR) begin 
+        Val_o <= 1'b1;
+    end
+    else begin 
+        Val_o <= 1'b0;
+    end
+end
+
+
+
+
+endmodule

QuadSPI/QuadSPIs_tb.v

@@ -0,0 +1,275 @@
+`timescale 1ns / 1ps
+module QuadSPIs_tb ();
+
+reg Clk70_i;
+reg Clk50_i;
+wire Sck_i;
+wire Rst_i;
+
+reg[7:0] mosiReg0_tb;
+reg[7:0] mosiReg1_tb;
+reg[7:0] mosiReg2_tb;
+reg[7:0] mosiReg3_tb;
+
+
+reg [7:0] Mosi0_i;
+reg [7:0] Mosi1_i;
+reg [7:0] Mosi2_i;
+reg [7:0] Mosi3_i;
+reg EnEdge_i;
+reg Ss;
+reg SSr;
+reg SSm;
+reg Start_i;
+reg startFlag;
+reg [5:0] ssCnt; 
+reg [3:0] ssNum;
+reg [1:0] WidthSel_i;
+
+reg [31:0] SPIdata;
+
+
+// assign Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
+// assign Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
+// assign Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
+// assign Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
+assign Sck_i = (!Ss) ? (Clk70_i) : 1'b0;
+
+
+
+
+// always #(24.390243902439/2) Clk70_i = ~Clk70_i;// 41Mhz
+always #(14.285714285714/2) Clk70_i = ~Clk70_i;// 70Mhz
+// always #10 Clk70_i = ~Clk70_i;// 50 Mhz
+
+always #10 Clk50_i = ~Clk50_i;
+
+
+
+
+always @(*) begin 
+    case (WidthSel_i) 
+        0 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[1]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[1]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[1]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[1]):1'b0;
+        end
+        1 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[3]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[3]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[3]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[3]):1'b0;
+        end
+        2 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[5]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[5]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[5]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[5]):1'b0;
+        end
+        3 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
+        end
+    endcase
+end
+
+
+
+
+
+
+
+initial begin 
+    Clk70_i = 1'b1;
+    // Clk70_i = 1'b0;//50 Mhz out of phase with src clk
+    Clk50_i = 1'b1;
+    Start_i = 1'b0;
+    EnEdge_i = 1'b1;
+    SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
+    WidthSel_i = 2'b11;
+    #100Start_i = 1'b1;
+    #500 Start_i = 1'b0;
+    #600 Start_i = 1'b1;
+     SPIdata = {1'h1, 7'h29, 24'd520050};
+    #100 Start_i = 1'b0;
+    #1500 Start_i = 1'b1;
+     SPIdata = {1'h0, 7'h2a, 24'd10};
+    #100 Start_i = 1'b0;
+
+end
+
+
+always @(posedge Clk70_i) begin
+    if (Rst_i) begin
+        SSr <=1'b0;
+    end
+    else begin 
+        SSr <= Ss;
+    end
+end
+
+
+always @(posedge Clk70_i) begin 
+    if (Rst_i) begin 
+        startFlag <= 1'b0;
+    end
+    else begin 
+        if (!Start_i) begin 
+            startFlag <= 1'b1;
+        end
+        else begin 
+            startFlag <= 1'b0;
+        end
+    end
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        ssNum = 1'b0;
+    end
+    else begin 
+        case (WidthSel_i) 
+            0 : begin 
+                ssNum = 2;
+            end
+            1 : begin 
+                ssNum = 4;
+            end
+            2 : begin 
+                ssNum = 6;
+            end
+            3 : begin 
+                ssNum = 8;
+            end
+        endcase
+    end
+end
+
+
+always @(posedge Clk70_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 1'b0;
+    end
+    else if (ssCnt < ssNum && startFlag  ) begin 
+        ssCnt <= ssCnt + 1'b1;
+    end
+    else begin
+        if (ssCnt == ssNum-1 || !startFlag) begin 
+            ssCnt <= 1'b0;
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        Ss <= 1'b1;
+    end
+    else begin 
+        if (ssCnt < ssNum && startFlag ) begin 
+            Ss <= 1'b0;
+        end
+        else begin 
+            Ss <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg0_tb <= SPIdata[31:24];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg0_tb <= { mosiReg0_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg0_tb <= SPIdata[31:24];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg1_tb <= SPIdata[23:16];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg1_tb <= { mosiReg1_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg1_tb <= SPIdata[23:16];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg2_tb <= SPIdata[15:8];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg2_tb <= { mosiReg2_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg2_tb <= SPIdata[15:8];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg3_tb <= SPIdata[7:0];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg3_tb <= { mosiReg3_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg3_tb <= SPIdata[7:0];
+        end
+    end
+end
+
+
+
+
+
+
+QuadSPIs QuadSPI_inst (
+    .Sck_i(Sck_i),
+    .Clk_i(Clk50_i),
+    .Rst_i(Rst_i),
+    .Ss_i(Ss),
+    .WidthSel_i(WidthSel_i),
+    .Mosi0_i(Mosi0_i),
+    .Mosi1_i(Mosi1_i),
+    .Mosi2_i(Mosi2_i),
+    .Mosi3_i(Mosi3_i),
+    .EnEdge_i(EnEdge_i),
+    .PulsePol_i(1'b0)
+
+);
+
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk50_i),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+
+
+
+
+
+endmodule

SRAM/QuadSPIm.v

@@ -35,6 +35,8 @@ reg lineBusy;
 reg [5:0] ssCnt;
 reg Ss;
 reg SSr;
+reg [31:0] spiDataR;
+reg oldDataFlag;
 reg [7:0] mosiReg0;
 reg [7:0] mosiReg1;
 reg [7:0] mosiReg2;
@@ -81,9 +83,12 @@ always @(posedge Clk_i) begin
         trCnt <= 1'b0;
     end
     else begin 
-        if ( ssCnt == (ssNum + LEAD_i + LAG_i)-1) begin 
+        if ( ssCnt == (ssNum + LEAD_i + LAG_i)) begin 
             trCnt <= trCnt + 1'b1;
         end
+        else if (oldDataFlag) begin 
+            trCnt <= 1'b0;
+        end
     end
 end
 
@@ -298,7 +303,7 @@ always @(*) begin
                     Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg0[0]):1'b0;
                     Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
                     Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
                 end
                 1 : begin 
                     Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
@@ -323,28 +328,28 @@ always @(*) begin
         else begin 
             case (WidthSel_i)
                 0 : begin
-                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
                 end
                 1 : begin
-                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
                 end
                 2 : begin
-                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
                     Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
                 end
                 3 : begin
-                    Mosi0_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
                 end
             endcase
         end
@@ -381,28 +386,28 @@ always @(*) begin
         else begin 
             case (WidthSel_i)
                 0 : begin
-                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
                 end
                 1 : begin
-                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
                 end
                 2 : begin
-                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
                 end
                 3 : begin
-                    Mosi0_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
                 end
             endcase
         end
@@ -436,13 +441,35 @@ always @(*) begin
 end
 
 
+always @(posedge Clk_i) begin
+    if (valReg) begin  
+        spiDataR <= SPIdata;
+    end
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        oldDataFlag = 1'b0;
+    end
+    else begin 
+        if (spiDataR == SPIdata) begin 
+            oldDataFlag = 1'b1;
+        end
+        else begin 
+            oldDataFlag = 1'b0;
+        end
+    end
+end
+
+
 
 always @(*) begin 
     if (Rst_i) begin 
         startFlag = 1'b0;
     end
     else begin 
-        if (Start_i&& !stopFlag && SPIdata != 0) begin 
+        if (Start_i&& !stopFlag && SPIdata != 0 && !oldDataFlag ) begin 
             startFlag = 1'b1;
         end
         else begin 

SRAM/RegMap.v

@@ -1491,6 +1491,9 @@ always @(*) begin
 						Debug0Addr : begin 
 							ansReg = LedReg[7:0];
 						end
+                        default : begin
+                            ansReg = 0;
+                        end
 					endcase
 				end
 			endcase

sources_1/new/CDC/Cdc.v

@@ -0,0 +1,82 @@
+module  Cdc#(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12
+)(
+    input Clk_i,
+    input [CmdRegWidth-1:0] Spi0CtrlReg_i,
+    input [CmdRegWidth-1:0] Spi0ClkReg_i,
+    input [CmdRegWidth-1:0] Spi0CsDelayReg_i,
+    input [CmdRegWidth-1:0] Spi0CsCtrlReg_i,
+    input [CmdRegWidth-1:0] Spi0TxFifoCtrlReg_i,
+    input [CmdRegWidth-1:0] Spi0RxFifoCtrlReg_i,
+    input [CmdRegWidth-1:0] AnsData_i,
+
+
+    output reg [CmdRegWidth-1:0] Spi0CtrlRR_o,
+    output reg [CmdRegWidth-1:0] Spi0ClkRR_o,
+    output reg [CmdRegWidth-1:0] Spi0CsDelayRR_o,
+    output reg [CmdRegWidth-1:0] Spi0CsCtrlRR_o,
+    output reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR_o,
+    output reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR_o,
+    output reg [CmdRegWidth-1:0] AnsDataRR_o
+
+);
+
+
+reg [CmdRegWidth-1:0] Spi0CtrlR;
+reg [CmdRegWidth-1:0] Spi0ClkRegR;
+reg [CmdRegWidth-1:0] Spi0CsDelayR;
+reg [CmdRegWidth-1:0] Spi0CsCtrlR;
+reg [CmdRegWidth-1:0] Spi0TxFifoCtrlR;
+reg [CmdRegWidth-1:0] Spi0RxFifoCtrlR;
+reg [CmdRegWidth-1:0] ansDataR;
+
+reg [CmdRegWidth-1:0] Spi0CtrlRR;
+reg [CmdRegWidth-1:0] Spi0ClkRegRR;
+reg [CmdRegWidth-1:0] Spi0CsDelayRR;
+reg [CmdRegWidth-1:0] Spi0CsCtrlRR;
+reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR;
+reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR;
+reg [CmdRegWidth-1:0] ansDataRR;
+
+
+
+
+
+
+
+
+always @(posedge Clk_i) begin
+    Spi0CtrlR <= Spi0CtrlReg_i;
+    Spi0ClkRegR <= Spi0ClkReg_i;
+    Spi0CsDelayR <= Spi0CsDelayReg_i;
+    Spi0CsCtrlR  <= Spi0CsCtrlReg_i;
+    Spi0TxFifoCtrlR <= Spi0TxFifoCtrlReg_i;
+    Spi0RxFifoCtrlR <= Spi0RxFifoCtrlReg_i;
+    ansDataR <= AnsData_i;
+    Spi0CtrlRR <= Spi0CtrlR;
+    Spi0ClkRegRR <= Spi0ClkRegR;
+    Spi0CsDelayRR <= Spi0CsDelayR;
+    Spi0CsCtrlRR  <= Spi0CsCtrlR;
+    Spi0TxFifoCtrlRR <= Spi0TxFifoCtrlR;
+    Spi0RxFifoCtrlRR <= Spi0RxFifoCtrlR;
+    ansDataRR <= ansDataR;
+    Spi0CtrlRR_o <=Spi0CtrlRR;
+    Spi0ClkRR_o <= Spi0ClkRegRR;
+    Spi0CsDelayRR_o <= Spi0CsDelayRR;
+    Spi0CsCtrlRR_o  <= Spi0CsCtrlRR;
+    Spi0TxFifoCtrlRR_o <= Spi0TxFifoCtrlRR;
+    Spi0RxFifoCtrlRR_o <= Spi0RxFifoCtrlRR;
+    AnsDataRR_o <= ansDataRR;
+end
+    
+
+
+
+
+
+
+
+
+endmodule
+

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -52,7 +52,7 @@ module DataFifoWrapper
 //================================================================================
 
 FifoCtrl FifoCtrl_inst (
-	.ToFifoTxWriteVal_i	(!SmcAwe_i && ToFifoVal_i),
+	.ToFifoTxWriteVal_i	(ToFifoVal_i),
 	.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
 	.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
 	.ToFifoRxReadVal_i	(!SmcAre_i),
@@ -60,6 +60,10 @@ FifoCtrl FifoCtrl_inst (
 	.FifoTxEmpty_i		(emptyFlagTx),
 	.FifoRxFull_i		(fullFlagRx),
 	.FifoRxEmpty_i		(emptyFlagRx),
+	.FifoTxWrClock_i	(WrClk_i),
+	.FifoTxRdClock_i	(RdClk_i),
+	.FifoRxWrClock_i	(RdClk_i),
+	.FifoRxRdClock_i	(WrClk_i),
 	.FifoTxWriteEn_o	(txFifoWrEn),
 	.FifoTxReadEn_o		(txFifoRdEn),
 	.FifoRxWriteEn_o	(rxFifoWrEn),

sources_1/new/DataFifo/DataOutMux.v

@@ -80,6 +80,9 @@ always @(*) begin
             12'h24e: begin 
                 dataFromRxFifoR = DataFromRxFifo7_i[31:16];
             end
+            default: begin
+                dataFromRxFifoR = 16'h0;
+            end
         endcase
     end
 

sources_1/new/DataFifo/FifoCtrl.v

@@ -10,6 +10,11 @@ module FifoCtrl (
     input FifoRxEmpty_i,
 
 
+    input FifoTxWrClock_i,
+    input FifoTxRdClock_i,
+    input FifoRxWrClock_i,
+    input FifoRxRdClock_i,
+
     output FifoTxWriteEn_o,
     output FifoTxReadEn_o,
     output FifoRxWriteEn_o,
@@ -39,39 +44,39 @@ assign FifoRxReadEn_o = FifoRxReadEn;
 
 
 
-always @(*) begin 
-    if (ToFifoTxWriteVal_i && ~FifoTxFull_i) begin 
-        FifoTxWriteEn = 1'b1;
+always @(posedge FifoTxWrClock_i) begin 
+    if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+        FifoTxWriteEn <= 1'b1;
     end
     else begin 
-        FifoTxWriteEn = 1'b0;
+        FifoTxWriteEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoTxReadVal_i && ~FifoTxEmpty_i) begin 
-        FifoTxReadEn = 1'b1;
+always @(posedge FifoTxRdClock_i ) begin 
+    if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+        FifoTxReadEn <= 1'b1;
     end
     else begin 
-        FifoTxReadEn = 1'b0;
+        FifoTxReadEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoRxWriteVal_i && ~FifoRxFull_i) begin 
-        FifoRxWriteEn = 1'b1;
+always @(posedge FifoRxWrClock_i) begin 
+    if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+        FifoRxWriteEn <= 1'b1;
     end
     else begin 
-        FifoRxWriteEn = 1'b0;
+        FifoRxWriteEn <= 1'b0;
     end
 end
 
-always @(*) begin 
-    if (ToFifoRxReadVal_i && ~FifoRxEmpty_i) begin 
-        FifoRxReadEn = 1'b1;
+always @(posedge FifoRxRdClock_i) begin 
+    if (ToFifoRxReadVal_i && !FifoRxEmpty_i) begin 
+        FifoRxReadEn <= 1'b1;
     end
     else begin 
-        FifoRxReadEn = 1'b0;
+        FifoRxReadEn <= 1'b0;
     end
 end
 

sources_1/new/DspSmc/SmcRx.v

@@ -62,11 +62,11 @@ module	SmcRx
 	assign	Addr_o	=	addrReg;
 	assign	Val_o	=	valReg;
 	
-	assign	SmcD_i	=	(!SmcAre_i)?	outDataReg:16'bz;
+	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
 //================================================================================
 //  CODING
 	
-always	@(posedge	Clk_i	or	negedge	Rst_i)	begin
+always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		if	(!SmcAmsN_i)	begin
 			if	(!SmcAwe_i)	begin
@@ -82,6 +82,9 @@ always	@(posedge	Clk_i	or	negedge	Rst_i)	begin
 				outDataReg	<=	AnsData_i;
 			end	
 		end
+		else	begin
+			valReg	<=	0;
+		end
 	end	else	begin
 		inDataReg	<=	0;
 		outDataReg	<=	0;

sources_1/new/MMCM/Division.c

@@ -6,13 +6,11 @@ int main() {
     double quotient, fractional_part;
     int whole_part, count_0125;
 
-    // Запрос ввода чисел у пользователя
     printf("Введите делимое: ");
     scanf("%lf", &dividend);
     printf("Введите делитель: ");
     scanf("%lf", &divisor);
 
-    // Проверка деления на ноль
     if (divisor == 0) {
         printf("Ошибка: Деление на ноль!\n");
         return 1;

sources_1/new/Mux/DataMuxer.v

@@ -35,7 +35,7 @@ module SmcDataMux
     input	Rst_i,
 
 	input	SmcVal_i,
-	input	[CmdRegWidth/2-1:0]	SmcData_i,
+	input	[CmdRegWidth-1:0]	SmcData_i,
     input	[AddrRegWidth-1:0]	SmcAddr_i,
 
 	output	reg	ToRegMapVal_o,
@@ -147,6 +147,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 			ToRegMapAddr_o	<=	0;
 		end	else	begin
 			ToRegMapVal_o	<=	SmcVal_i;
+			ToFifoVal_o		<=	7'h0;
 			ToRegMapData_o	<=	SmcData_i;
 			ToRegMapAddr_o	<=	SmcAddr_i;
 		end

sources_1/new/S5443_3Top.v

@@ -25,7 +25,7 @@ module S5443_3Top
 #(
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
-    parameter SpiNum = 7
+    parameter SpiNum = 1
 
 )
 (
@@ -43,14 +43,15 @@ module S5443_3Top
 
     output  Led_o,
    
-    output  [SpiNum-1:0] Mosi0_o,
-    output  [SpiNum-1:0] Mosi1_o,
+    output  [SpiNum-1:0] Mosi0_o, 
+    output  [SpiNum-1:0] Mosi1_o,//inout: when RSPI mode, input; when QSPI mode output; 
     output  [SpiNum-1:0] Mosi2_o,
     output  [SpiNum-1:0] Mosi3_o,
     output  [SpiNum-1:0] Ss_o,
     output  [SpiNum-1:0] SsFlash_o,
     output  [SpiNum-1:0] Sck_o,
     output  [SpiNum-1:0] SpiRst_o,
+    output  [SpiNum-1:0] SpiDir_o,
     output  LD_o
 
 );
@@ -74,6 +75,16 @@ wire gclk;
 wire [0:7] baudRate [SpiNum-1:0];
 
 
+
+
+
+
+//InitRst
+
+wire [SpiNum-1:0] initRstGen;
+
+
+
 //SPI0
 wire [CmdRegWidth-1:0] spi0Ctrl;
 wire [CmdRegWidth-1:0] spi0Clk;
@@ -83,6 +94,15 @@ wire [CmdRegWidth-1:0] spi0TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi0RxFifoCtrl;
 wire [CmdRegWidth-1:0] spi0TxFifo;
 wire [CmdRegWidth-1:0] spi0RxFifo;
+
+wire [CmdRegWidth-1:0] spi0CtrlRR;
+wire [CmdRegWidth-1:0] spi0ClkRR;
+wire [CmdRegWidth-1:0] spi0CsDelayRR;
+wire [CmdRegWidth-1:0] spi0CsCtrlRR;
+wire [CmdRegWidth-1:0] spi0TxFifoCtrlRR;
+wire [CmdRegWidth-1:0] spi0RxFifoCtrlRR;
+wire [CmdRegWidth-1:0] ansDataRR;
+
 //SPI1
 wire [CmdRegWidth-1:0] spi1Ctrl;
 wire [CmdRegWidth-1:0] spi1Clk;
@@ -241,7 +261,7 @@ assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
 assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
 assign Sck_o = Sck;
 
-assign widthSel[0] = spi0Ctrl[6:5];
+assign widthSel[0] = spi0CtrlRR[6:5];
 assign widthSel[1] = spi1Ctrl[6:5];
 assign widthSel[2] = spi2Ctrl[6:5];
 assign widthSel[3] = spi3Ctrl[6:5];
@@ -249,7 +269,7 @@ assign widthSel[4] = spi4Ctrl[6:5];
 assign widthSel[5] = spi5Ctrl[6:5];
 assign widthSel[6] = spi6Ctrl[6:5];
 
-assign spiMode[0] = spi0Ctrl[7];
+assign spiMode[0] = spi0CtrlRR[7];
 assign spiMode[1] = spi1Ctrl[7];
 assign spiMode[2] = spi2Ctrl[7];
 assign spiMode[3] = spi3Ctrl[7];
@@ -258,7 +278,7 @@ assign spiMode[5] = spi5Ctrl[7];
 assign spiMode[6] = spi6Ctrl[7];
 
 
-assign CPOL[0] = spi0Ctrl[2];
+assign CPOL[0] = spi0CtrlRR[2];
 assign CPOL[1] = spi1Ctrl[2];
 assign CPOL[2] = spi2Ctrl[2];
 assign CPOL[3] = spi3Ctrl[2];
@@ -266,7 +286,7 @@ assign CPOL[4] = spi4Ctrl[2];
 assign CPOL[5] = spi5Ctrl[2];
 assign CPOL[6] = spi6Ctrl[2];
 
-assign CPHA[0] = spi0Ctrl[1];
+assign CPHA[0] = spi0CtrlRR[1];
 assign CPHA[1] = spi1Ctrl[1];
 assign CPHA[2] = spi2Ctrl[1];
 assign CPHA[3] = spi3Ctrl[1];
@@ -274,7 +294,7 @@ assign CPHA[4] = spi4Ctrl[1];
 assign CPHA[5] = spi5Ctrl[1];
 assign CPHA[6] = spi6Ctrl[1];
 
-assign endianSel[0] = spi0Ctrl[8];
+assign endianSel[0] = spi0CtrlRR[8];
 assign endianSel[1] = spi1Ctrl[8];
 assign endianSel[2] = spi2Ctrl[8];
 assign endianSel[3] = spi3Ctrl[8];
@@ -282,7 +302,7 @@ assign endianSel[4] = spi4Ctrl[8];
 assign endianSel[5] = spi5Ctrl[8];
 assign endianSel[6] = spi6Ctrl[8];
 
-assign selSt[0] = spi0Ctrl[4];
+assign selSt[0] = spi0CtrlRR[4];
 assign selSt[1] = spi1Ctrl[4];
 assign selSt[2] = spi2Ctrl[4];
 assign selSt[3] = spi3Ctrl[4];
@@ -290,7 +310,7 @@ assign selSt[4] = spi4Ctrl[4];
 assign selSt[5] = spi5Ctrl[4];
 assign selSt[6] = spi6Ctrl[4];
 
-assign Assel[0] = spi0Ctrl[3];
+assign Assel[0] = spi0CtrlRR[3];
 assign Assel[1] = spi1Ctrl[3];
 assign Assel[2] = spi2Ctrl[3];
 assign Assel[3] = spi3Ctrl[3];
@@ -298,7 +318,7 @@ assign Assel[4] = spi4Ctrl[3];
 assign Assel[5] = spi5Ctrl[3];
 assign Assel[6] = spi6Ctrl[3];
 
-assign stopDelay[0] = spi0CsDelay[7:2];
+assign stopDelay[0] = spi0CsDelayRR[7:2];
 assign stopDelay[1] = spi1CsDelay[7:2];
 assign stopDelay[2] = spi2CsDelay[7:2];
 assign stopDelay[3] = spi3CsDelay[7:2];
@@ -306,7 +326,7 @@ assign stopDelay[4] = spi4CsDelay[7:2];
 assign stopDelay[5] = spi5CsDelay[7:2];
 assign stopDelay[6] = spi6CsDelay[7:2];
 
-assign leadx[0] = spi0CsDelay[1];
+assign leadx[0] = spi0CsDelayRR[1];
 assign leadx[1] = spi1CsDelay[1];
 assign leadx[2] = spi2CsDelay[1];
 assign leadx[3] = spi3CsDelay[1];
@@ -314,7 +334,7 @@ assign leadx[4] = spi4CsDelay[1];
 assign leadx[5] = spi5CsDelay[1];
 assign leadx[6] = spi6CsDelay[1];
 
-assign lag[0] = spi0CsDelay[0];
+assign lag[0] = spi0CsDelayRR[0];
 assign lag[1] = spi1CsDelay[0];
 assign lag[2] = spi2CsDelay[0];
 assign lag[3] = spi3CsDelay[0];
@@ -322,7 +342,7 @@ assign lag[4] = spi4CsDelay[0];
 assign lag[5] = spi5CsDelay[0];
 assign lag[6] = spi6CsDelay[0];
 
-assign baudRate[0] = spi0Clk[7:0];
+assign baudRate[0] = spi0ClkRR[7:0];
 assign baudRate[1] = spi1Clk[7:0];
 assign baudRate[2] = spi2Clk[7:0];
 assign baudRate[3] = spi3Clk[7:0];
@@ -339,7 +359,7 @@ assign SpiRst_o[4] = GPIOA[4];
 assign SpiRst_o[5] = GPIOA[5];
 assign SpiRst_o[6] = GPIOA[6];
 
-assign fifoRxRst[0] = spi0RxFifoCtrl[0];
+assign fifoRxRst[0] = spi0RxFifoCtrlRR[0];
 assign fifoRxRst[1] = spi1RxFifoCtrl[0];
 assign fifoRxRst[2] = spi2RxFifoCtrl[0];
 assign fifoRxRst[3] = spi3RxFifoCtrl[0];
@@ -347,7 +367,7 @@ assign fifoRxRst[4] = spi4RxFifoCtrl[0];
 assign fifoRxRst[5] = spi5RxFifoCtrl[0];
 assign fifoRxRst[6] = spi6RxFifoCtrl[0];
 
-assign fifoTxRst[0] = spi0TxFifoCtrl[0];
+assign fifoTxRst[0] = spi0TxFifoCtrlRR[0];
 assign fifoTxRst[1] = spi1TxFifoCtrl[0];
 assign fifoTxRst[2] = spi2TxFifoCtrl[0];
 assign fifoTxRst[3] = spi3TxFifoCtrl[0];
@@ -364,7 +384,7 @@ assign Ld_i[5] = GPIOA[21];
 assign Ld_i[6] = GPIOA[22];
 assign LD_o = Ld_i[0]&Ld_i[1]&Ld_i[2]&Ld_i[3]&Ld_i[4]&Ld_i[5]&Ld_i[6];
 
-assign wordCntRx[0] = spi0RxFifoCtrl[15:8];
+assign wordCntRx[0] = spi0RxFifoCtrlRR[15:8];
 assign wordCntRx[1] = spi1RxFifoCtrl[15:8];
 assign wordCntRx[2] = spi2RxFifoCtrl[15:8];
 assign wordCntRx[3] = spi3RxFifoCtrl[15:8];
@@ -372,7 +392,7 @@ assign wordCntRx[4] = spi4RxFifoCtrl[15:8];
 assign wordCntRx[5] = spi5RxFifoCtrl[15:8];
 assign wordCntRx[6] = spi6RxFifoCtrl[15:8];
 
-assign wordCntTx[0] = spi0TxFifoCtrl[15:8];
+assign wordCntTx[0] = spi0TxFifoCtrlRR[15:8];
 assign wordCntTx[1] = spi1TxFifoCtrl[15:8];
 assign wordCntTx[2] = spi2TxFifoCtrl[15:8];
 assign wordCntTx[3] = spi3TxFifoCtrl[15:8];
@@ -381,7 +401,7 @@ assign wordCntTx[5] = spi5TxFifoCtrl[15:8];
 assign wordCntTx[6] = spi6TxFifoCtrl[15:8];
 
 
-assign CS0[0] = spi0CsCtrl[0];
+assign CS0[0] = spi0CsCtrlRR[0];
 assign CS0[1] = spi1CsCtrl[0];
 assign CS0[2] = spi2CsCtrl[0];
 assign CS0[3] = spi3CsCtrl[0];
@@ -389,7 +409,7 @@ assign CS0[4] = spi4CsCtrl[0];
 assign CS0[5] = spi5CsCtrl[0];
 assign CS0[6] = spi6CsCtrl[0];
 
-assign CS1[0] = spi0CsCtrl[1];
+assign CS1[0] = spi0CsCtrlRR[1];
 assign CS1[1] = spi1CsCtrl[1];
 assign CS1[2] = spi2CsCtrl[1];
 assign CS1[3] = spi3CsCtrl[1];
@@ -398,56 +418,72 @@ assign CS1[5] = spi5CsCtrl[1];
 assign CS1[6] = spi6CsCtrl[1];
 
 
-assign Ss[0] = (spiMode)? SsQ[0]:SsR[0];
-assign Ss[1] = (spiMode)? SsQ[1]:SsR[1];
-assign Ss[2] = (spiMode)? SsQ[2]:SsR[2];
-assign Ss[3] = (spiMode)? SsQ[3]:SsR[3];
-assign Ss[4] = (spiMode)? SsQ[4]:SsR[4];
-assign Ss[5] = (spiMode)? SsQ[5]:SsR[5];
-assign Ss[6] = (spiMode)? SsQ[6]:SsR[6];
-
-assign Sck[0] = (spiMode)? SckQ[0]:SckR[0];
-assign Sck[1] = (spiMode)? SckQ[1]:SckR[1];
-assign Sck[2] = (spiMode)? SckQ[2]:SckR[2];
-assign Sck[3] = (spiMode)? SckQ[3]:SckR[3];
-assign Sck[4] = (spiMode)? SckQ[4]:SckR[4];
-assign Sck[5] = (spiMode)? SckQ[5]:SckR[5];
-assign Sck[6] = (spiMode)? SckQ[6]:SckR[6];
-
-assign Mosi0[0] = (spiMode)? Mosi0Q[0]:Mosi0R[0];
-assign Mosi0[1] = (spiMode)? Mosi0Q[1]:Mosi0R[1];
-assign Mosi0[2] = (spiMode)? Mosi0Q[2]:Mosi0R[2];
-assign Mosi0[3] = (spiMode)? Mosi0Q[3]:Mosi0R[3];
-assign Mosi0[4] = (spiMode)? Mosi0Q[4]:Mosi0R[4];
-assign Mosi0[5] = (spiMode)? Mosi0Q[5]:Mosi0R[5];
-assign Mosi0[6] = (spiMode)? Mosi0Q[6]:Mosi0R[6];
-
-assign valToTxFifoRead[0] = (spiMode)? valToTxQ[0]:valToTxR[0];
-assign valToTxFifoRead[1] = (spiMode)? valToTxQ[1]:valToTxR[1];
-assign valToTxFifoRead[2] = (spiMode)? valToTxQ[2]:valToTxR[2];
-assign valToTxFifoRead[3] = (spiMode)? valToTxQ[3]:valToTxR[3];
-assign valToTxFifoRead[4] = (spiMode)? valToTxQ[4]:valToTxR[4];
-assign valToTxFifoRead[5] = (spiMode)? valToTxQ[5]:valToTxR[5];
-assign valToTxFifoRead[6] = (spiMode)? valToTxQ[6]:valToTxR[6];
-
-assign valToRxFifo[0] = (spiMode)? valToRxQ[0]:valToRxR[0];
-assign valToRxFifo[1] = (spiMode)? valToRxQ[1]:valToRxR[1];
-assign valToRxFifo[2] = (spiMode)? valToRxQ[2]:valToRxR[2];
-assign valToRxFifo[3] = (spiMode)? valToRxQ[3]:valToRxR[3];
-assign valToRxFifo[4] = (spiMode)? valToRxQ[4]:valToRxR[4];
-assign valToRxFifo[5] = (spiMode)? valToRxQ[5]:valToRxR[5];
-assign valToRxFifo[6] = (spiMode)? valToRxQ[6]:valToRxR[6];
-
-assign dataToRxFifo[0] = (spiMode)? dataToRxFifoQ[0]:dataToRxFifoR[0];
-assign dataToRxFifo[1] = (spiMode)? dataToRxFifoQ[1]:dataToRxFifoR[1];
-assign dataToRxFifo[2] = (spiMode)? dataToRxFifoQ[2]:dataToRxFifoR[2];
-assign dataToRxFifo[3] = (spiMode)? dataToRxFifoQ[3]:dataToRxFifoR[3];
-assign dataToRxFifo[4] = (spiMode)? dataToRxFifoQ[4]:dataToRxFifoR[4];
-assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
-assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
-
-
-// assign SmcData_i = (!SmcAoe_i)?muxedData:16'bz;
+assign Ss[0] = (spiMode[0])? SsQ[0]:SsR[0];
+assign Ss[1] = (spiMode[1])? SsQ[1]:SsR[1];
+assign Ss[2] = (spiMode[2])? SsQ[2]:SsR[2];
+assign Ss[3] = (spiMode[3])? SsQ[3]:SsR[3];
+assign Ss[4] = (spiMode[4])? SsQ[4]:SsR[4];
+assign Ss[5] = (spiMode[5])? SsQ[5]:SsR[5];
+assign Ss[6] = (spiMode[6])? SsQ[6]:SsR[6];
+
+assign SpiDir_o[0] = (spiMode[0])? 1'b0 : 1'b1 ;
+assign SpiDir_o[1] = (spiMode[1])? 1'b0 : 1'b1 ;
+assign SpiDir_o[2] = (spiMode[2])? 1'b0 : 1'b1 ;
+assign SpiDir_o[3] = (spiMode[3])? 1'b0 : 1'b1 ;
+assign SpiDir_o[4] = (spiMode[4])? 1'b0 : 1'b1 ;
+assign SpiDir_o[5] = (spiMode[5])? 1'b0 : 1'b1 ;
+assign SpiDir_o[6] = (spiMode[6])? 1'b0 : 1'b1 ;
+
+
+assign Sck[0] =  (spiMode[0])?SckQ[0]:SckR[0];
+assign Sck[1] =  (spiMode[1])?SckQ[1]:SckR[1];
+assign Sck[2] =  (spiMode[2])?SckQ[2]:SckR[2];
+assign Sck[3] =  (spiMode[3])?SckQ[3]:SckR[3];
+assign Sck[4] =  (spiMode[4])?SckQ[4]:SckR[4];
+assign Sck[5] =  (spiMode[5])?SckQ[5]:SckR[5];
+assign Sck[6] =  (spiMode[6])?SckQ[6]:SckR[6];
+
+assign Mosi0[0] =  (spiMode[0])?Mosi0Q[0]:Mosi0R[0];
+assign Mosi0[1] =  (spiMode[1])?Mosi0Q[1]:Mosi0R[1];
+assign Mosi0[2] =  (spiMode[2])?Mosi0Q[2]:Mosi0R[2];
+assign Mosi0[3] =  (spiMode[3])?Mosi0Q[3]:Mosi0R[3];
+assign Mosi0[4] =  (spiMode[4])?Mosi0Q[4]:Mosi0R[4];
+assign Mosi0[5] =  (spiMode[5])?Mosi0Q[5]:Mosi0R[5];
+assign Mosi0[6] =  (spiMode[6])?Mosi0Q[6]:Mosi0R[6];
+
+assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
+assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
+assign valToTxFifoRead[2] =  (spiMode[2])?valToTxQ[2]:valToTxR[2];
+assign valToTxFifoRead[3] =  (spiMode[3])?valToTxQ[3]:valToTxR[3];
+assign valToTxFifoRead[4] =  (spiMode[4])?valToTxQ[4]:valToTxR[4];
+assign valToTxFifoRead[5] =  (spiMode[5])?valToTxQ[5]:valToTxR[5];
+assign valToTxFifoRead[6] =  (spiMode[6])?valToTxQ[6]:valToTxR[6];
+
+assign valToRxFifo[0] = valToRxR[0];
+assign valToRxFifo[1] = valToRxR[1];
+assign valToRxFifo[2] = valToRxR[2];
+assign valToRxFifo[3] = valToRxR[3];
+assign valToRxFifo[4] = valToRxR[4];
+assign valToRxFifo[5] = valToRxR[5];
+assign valToRxFifo[6] = valToRxR[6];
+
+// assign dataToRxFifo[0] = (spiMode)? dataToRxFifoQ[0]:dataToRxFifoR[0];
+// assign dataToRxFifo[1] = (spiMode)? dataToRxFifoQ[1]:dataToRxFifoR[1];
+// assign dataToRxFifo[2] = (spiMode)? dataToRxFifoQ[2]:dataToRxFifoR[2];
+// assign dataToRxFifo[3] = (spiMode)? dataToRxFifoQ[3]:dataToRxFifoR[3];
+// assign dataToRxFifo[4] = (spiMode)? dataToRxFifoQ[4]:dataToRxFifoR[4];
+// assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
+// assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
+
+assign dataToRxFifo[0] = dataToRxFifoR[0];
+assign dataToRxFifo[1] = dataToRxFifoR[1];
+assign dataToRxFifo[2] = dataToRxFifoR[2];
+assign dataToRxFifo[3] = dataToRxFifoR[3];
+assign dataToRxFifo[4] = dataToRxFifoR[4];
+assign dataToRxFifo[5] = dataToRxFifoR[5];
+assign dataToRxFifo[6] = dataToRxFifoR[6];
+
+
 
 //================================================================================
 //  CODING
@@ -460,7 +496,7 @@ DataOutMux DataOutMuxer
     // .Rst_i	(initRst),
     .Addr_i  (smcAddr),
     .ToRegMapAddr_i (toRegMapAddr),
-    .DataFromRegMap_i (ansData),
+    .DataFromRegMap_i (ansDataRR),
     .DataFromRxFifo1_i (dataFromRxFifo[0]),
     .DataFromRxFifo2_i (dataFromRxFifo[1]),
     .DataFromRxFifo3_i (dataFromRxFifo[2]),
@@ -598,6 +634,29 @@ RegMap_inst
     .GPIOAReg_o(GPIOA)
 );
 
+
+Cdc Sync (
+    .Clk_i(gclk),
+    .Spi0CtrlReg_i(spi0Ctrl),
+    .Spi0ClkReg_i(spi0Clk),
+    .Spi0CsDelayReg_i(spi0CsDelay),
+    .Spi0CsCtrlReg_i(spi0CsCtrl),
+    .Spi0TxFifoCtrlReg_i(spi0TxFifoCtrl),
+    .Spi0RxFifoCtrlReg_i(spi0RxFifoCtrl),
+    .AnsData_i(ansData),
+    .Spi0CtrlRR_o(spi0CtrlRR),
+    .Spi0ClkRR_o(spi0ClkRR),
+    .Spi0CsDelayRR_o(spi0CsDelayRR),
+    .Spi0CsCtrlRR_o(spi0CsCtrlRR),
+    .Spi0TxFifoCtrlRR_o(spi0TxFifoCtrlRR),
+    .Spi0RxFifoCtrlRR_o(spi0RxFifoCtrlRR),
+    .AnsDataRR_o(ansDataRR)
+
+
+);
+
+
+
 MmcmWrapper MainMmcm
 (
 	.Clk_i		(gclk),
@@ -621,14 +680,14 @@ genvar i;
 generate
     for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
 		
-		// RstSync SpiRstSync
-		// (
-			// .Clk_i	(spiClkBus[i]),
-			// .Rst_i	(initRst),
+        InitRst InitRst_inst
+ (
+    .clk_i(Clk40_o),
+    .signal_o(initRstGen[i])
+);
+
+
 
-			// .Rst_o	(spiSyncRst[i])
-		// );
-		
 		DataFifoWrapper DataFifoWrapper
 		(
 			.WrClk_i	(gclk),
@@ -656,7 +715,7 @@ generate
         SPIm SPIm_inst (
             .Clk_i(Clk40_o),
             .Start_i(ten[i]),
-            .Rst_i(initRst| spiMode[i]),
+            .Rst_i(initRstGen[i]| spiMode[i]),
             .SPIdata(toSpiData[i]),
             .Sck_o(SckR[i]),
             .Ss_o(SsR[i]),
@@ -681,7 +740,7 @@ generate
 
         SPIs SPIs_inst (
             .Clk_i(Clk40_o),
-            .Rst_i(initRst|SpiRst_o[i]| spiMode[i]),
+            .Rst_i(initRstGen[i]|SpiRst_o[i]| spiMode[i]),
             .Sck_i(SckR[i]),
             .Ss_i(SsR[i]),
             .Mosi0_i(Mosi0R[i]),
@@ -695,7 +754,7 @@ generate
         QuadSPIm QuadSPIm_inst (
             .Clk_i(Clk40_o),
             .Start_i(ten[i]),
-            .Rst_i(initRst| !spiMode[i]),
+            .Rst_i(initRstGen[i]| !spiMode[i]),
 			.SpiDataVal_i	(toSpiVal),
             // .SPIdata(32'h2aaa00aa),
             .SPIdata(toSpiData[i]),
@@ -715,20 +774,20 @@ generate
             .SELST_i(selSt[i]),
             .Val_o(valToTxQ[i])
         );
-        QuadSPIs QuadSPIs_inst (
-            .Clk_i(Clk40_o),
-            .Rst_i(initRst|SpiRst_o[i]| !spiMode[i]),
-            .Sck_i(SckQ[i]),
-            .Ss_i(SsQ[i]),
-            .Mosi0_i(Mosi0Q[i]),
-            .Mosi1_i(Mosi1[i]),
-            .Mosi2_i(Mosi2[i]),
-            .Mosi3_i(Mosi3[i]),
-            .WidthSel_i(widthSel[i]),
-            .SELST_i(selSt[i]),
-            .DataToRxFifo_o(dataToRxFifoQ[i]),
-            .Val_o(valToRxQ[i])
-        );
+        // QuadSPIs QuadSPIs_inst (
+        //     .Clk_i(Clk40_o),
+        //     .Rst_i(initRstGen[i]|SpiRst_o[i]| !spiMode[i]),
+        //     .Sck_i(SckQ[i]),
+        //     .Ss_i(SsQ[i]),
+        //     .Mosi0_i(Mosi0Q[i]),
+        //     .Mosi1_i(Mosi1[i]),
+        //     .Mosi2_i(Mosi2[i]),
+        //     .Mosi3_i(Mosi3[i]),
+        //     .WidthSel_i(widthSel[i]),
+        //     .SELST_i(selSt[i]),
+        //     .DataToRxFifo_o(dataToRxFifoQ[i]),
+        //     .Val_o(valToRxQ[i])
+        // );
 
     end
 endgenerate

sources_1/new/S5443_3_tb.v

@@ -0,0 +1,348 @@
+`timescale 1ns / 1ps
+module S5443_3_tb;
+
+parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+
+
+
+reg Clk_i;
+reg Rst_i;
+reg [10:0] SmcAddr_i;
+reg [15:0]SmcData_i;
+reg SmcAre_i;
+reg SmcAwe_i;
+wire SmcAmsN_i;
+wire [1:0] SmcBe_i;
+reg SmcAoe_i;
+
+reg [31:0] tb_cnt;
+
+wire [15:0] smcData;
+
+assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
+assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
+assign smcData = SmcData_i;
+
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+
+
+    S5443_3Top uut (
+        .Clk123_i(Clk_i), 
+        .SmcAddr_i(SmcAddr_i), 
+        .SmcData_i(smcData), 
+        .SmcAwe_i(SmcAwe_i), 
+        .SmcAmsN_i(SmcAmsN_i), 
+        .SmcAre_i(SmcAre_i), 
+        .SmcBe_i(SmcBe_i), 
+        .SmcAoe_i(SmcAoe_i), 
+        .Ld_i(Ld_i), 
+        .Led_o(), 
+        .Mosi0_o(), 
+        .Mosi1_o(), 
+        .Mosi2_o(), 
+        .Mosi3_o(), 
+        .Ss_o(), 
+        .SsFlash_o(), 
+        .Sck_o(), 
+        .SpiRst_o(), 
+        .LD_o()
+    );
+
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin
+        SmcAwe_i <= 1'b1;
+    end
+    else begin 
+        case (tb_cnt)
+        0: begin 
+            SmcAwe_i <= 1'b1;
+        end 
+        1: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        2: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        3: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        4: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        5: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        6: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        7: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        8: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        9: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        10: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        11: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        12: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        13: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        14: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        15: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        16: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        17: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        18: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        19: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        20: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        21: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        22: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        23: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        24: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        25: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        26: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        27: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        28: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        29: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        30: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        31: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        32: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        33: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        34: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        35: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        36: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        37: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        38: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        39: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        40: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        41: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        42: begin 
+            SmcAwe_i <= 1'b1;
+        end
+        43: begin 
+            SmcAwe_i <= 1'b0;
+        end
+        44: begin 
+            SmcAwe_i <= 1'b1;
+        end
+    endcase
+    end
+end
+
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        SmcAddr_i <= 0;
+        SmcData_i <= 0;
+    end
+    else begin
+        case (tb_cnt)
+        0: begin 
+            SmcAddr_i <= 12'h00f;
+            SmcData_i <= 16'h0000;
+        end
+        2: begin 
+            SmcAddr_i <= 12'h7fc;
+            SmcData_i <= 16'h0001;
+        end
+        4: begin 
+            SmcAddr_i <= 12'h7fd;
+            SmcData_i <= 16'h0000;
+        end
+        6: begin 
+            SmcAddr_i <= 12'h7fe;
+            SmcAddr_i <= 16'h0000;
+        end
+        8: begin 
+            SmcAddr_i <= 12'h0;
+            SmcData_i <= 16'hef;
+        end
+        10: begin 
+            SmcAddr_i <= 12'h1;
+            SmcData_i <= 16'h1;
+        end
+        12: begin 
+             SmcAddr_i <= 12'h2;
+             SmcData_i <= 16'h0;
+        end
+        14: begin 
+            SmcAddr_i <= 12'h3;
+            SmcData_i <= 16'h0;
+        end
+        16: begin 
+            SmcAddr_i <= 12'h4;
+            SmcData_i <= 16'hc;
+        end
+        18: begin 
+            SmcAddr_i <= 12'h5;
+            SmcData_i <= 16'h0;
+        end
+        20: begin 
+             SmcAddr_i <= 12'h6;
+             SmcData_i <= 16'h0;
+        end
+        22:  begin 
+            SmcAddr_i <= 12'h7;
+            SmcData_i <= 16'h0;
+        end
+        24: begin
+             SmcAddr_i <= 12'h8;
+             SmcData_i <= 16'h0;
+        end
+        26: begin 
+            SmcAddr_i <= 12'h9;
+            SmcData_i <= 16'h0;
+        end
+        28: begin 
+             SmcAddr_i <= 12'ha;
+             SmcData_i <= 16'h0;
+        end
+        30: begin 
+             SmcAddr_i <= 12'hb;
+             SmcData_i <= 16'h0;
+        end
+        32: begin 
+             SmcAddr_i <= 12'h780;
+             SmcData_i <= 16'h1;
+        end
+        34: begin
+             SmcAddr_i <= 12'h781;
+             SmcData_i <= 16'h0;
+        end
+        36: begin
+             SmcAddr_i <= 12'h7f8;
+             SmcData_i <= 16'h0;
+        end
+        38: begin 
+             SmcAddr_i <= 12'h7f9;
+             SmcData_i <= 16'h0;
+        end
+        40: begin 
+            SmcAddr_i <= 12'h00c;
+            SmcData_i <= 16'h1;
+        end
+        42: begin 
+            SmcAddr_i <= 12'h00d;
+            SmcData_i <= 16'h0;
+        end
+    endcase
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        tb_cnt <= 0;
+    end
+    else begin 
+        tb_cnt <= tb_cnt + 1;
+    end
+end
+
+
+// always @(*) begin 
+//     txNextState = IDLE;
+//     case(txCurrState)
+//     IDLE : begin 
+//             if (txWork) begin 
+//                 txNextState = CMD;
+//             end
+//             else begin 
+//                 txNextState = IDLE;
+//             end
+//         end
+//     WRITE : begin 
+//             if () begin 
+//                 txNextState = WRITE;
+//             end
+//             else begin 
+//                 txNextState = IDLE;
+//             end
+//         end
+
+
+initial begin 
+    Clk_i = 1'b0;
+    Rst_i = 1'b1;
+    SmcAre_i = 1'b1;
+    SmcAoe_i = 1'b1;
+    #(CLK_PERIOD*10) Rst_i = 1'b0;
+
+
+
+
+end
+
+endmodule
+

sources_1/new/SpiR/SPIm.v

@@ -29,9 +29,13 @@ reg startFlag;
 reg startR;
 reg [31:0] trCnt;
 reg valReg;
+reg valToRxFifo1;
 reg lineBusy;
 reg [5:0] ssCnt;
 reg Ss;
+reg [31:0]spiDataR;
+reg oldDataFlag;
+
 reg SSr;
 reg SSR;
 reg [31:0] mosiReg0;
@@ -58,7 +62,7 @@ assign Val_o = (trCnt < 1 ) ?!lineBusy:valReg;
 
 always @(*) begin 
     if (SELST_i) begin 
-        if (!Ss) begin 
+        if (!Ss_o) begin 
             lineBusy = 1'b1;
         end
         else begin 
@@ -66,7 +70,7 @@ always @(*) begin
         end
     end
     else begin 
-        if (Ss) begin 
+        if (Ss_o) begin 
             lineBusy = 1'b1;
         end
         else begin 
@@ -75,19 +79,68 @@ always @(*) begin
     end
 end
 
+
+
+always @(posedge Clk_i) begin
+    if (valReg) begin  
+        spiDataR <= SPIdata;
+    end
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        oldDataFlag = 1'b0;
+    end
+    else begin 
+        if (spiDataR == SPIdata) begin 
+            oldDataFlag = 1'b1;
+        end
+        else begin 
+            oldDataFlag = 1'b0;
+        end
+    end
+end
+
+
+
+
+
+always @(posedge Clk_i) begin 
+    startR <= Start_i;
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        valToRxFifo1 = 1'b0;
+    end
+    else begin 
+        if (Start_i && !startR) begin 
+            valToRxFifo1 = 1'b1;
+        end
+        else begin 
+            valToRxFifo1 = 1'b0;
+        end
+    end
+end
+
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         trCnt <= 1'b0;
     end
     else begin 
-        if ( ssCnt == (ssNum + LEAD_i + LAG_i)-1) begin 
+        if ( ssCnt == (ssNum + LEAD_i + LAG_i)) begin 
             trCnt <= trCnt + 1'b1;
         end
+        else if (oldDataFlag) begin 
+            trCnt <= 1'b0;
+        end
     end
 end
 
 
 
+
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         delayCnt <= 1'b0;
@@ -299,32 +352,32 @@ always @(*) begin
             if (!EndianSel_i) begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
                     end
                 endcase
             end
             else begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                 endcase
             end
@@ -333,32 +386,32 @@ always @(*) begin
             if (!EndianSel_i) begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
                     end
                 endcase
             end
             else begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (SsPol&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                 endcase
             end
@@ -379,7 +432,7 @@ always @(*) begin
         startFlag = 1'b0;
     end
     else begin 
-        if (Start_i && !stopFlag && SPIdata != 0 ) begin 
+        if (Start_i&& !stopFlag && SPIdata != 0 && !oldDataFlag ) begin 
             startFlag = 1'b1;
         end
         else begin 
@@ -390,7 +443,7 @@ end
 
 always @(*) begin
     if (SELST_i) begin 
-        if (Ss && !SSr) begin 
+        if (Ss_o && !SSr) begin 
             valReg = 1'b1;
         end
         else begin 
@@ -398,7 +451,7 @@ always @(*) begin
         end
     end
     else begin 
-        if (!Ss&& SSr) begin 
+        if (!Ss_o&& SSr) begin 
             valReg = 1'b1;
         end
         else begin 
@@ -407,6 +460,7 @@ always @(*) begin
     end
 end
 
+
 always @(*) begin 
     if (Rst_i) begin 
         ssNum = 1'b0;