Добавлен файл SpiLinesMuxer

sources_1/new/DataFifo/FifoCtrl.v

@@ -114,29 +114,6 @@ module FifoCtrl #(
         .RxFifoWrPtr_o(rxFifoWrPtrSync)
     );
 
-    // TxFifoPtrSync #(
-    //     .WIDTH(8),
-    //     .STAGES(3)
-    // )
-    // txFifoPtrSync (
-    //     .ClkFast_i(FifoTxWrClock_i),
-    //     .ClkSlow_i(FifoTxRdClock_i),
-    //     .TxFifoWrPtr_i(txFifoWrPtr),
-    //     .TxFifoWrPtr_o(txFifoWrPtrSync)
-    // );
-
-    // RxFifoRstSync #(
-    //     .WIDTH(1),
-    //     .STAGES(3)
-    // )
-    // rxFifoRstSync (
-    //     .ClkFast_i(FifoRxWrClock_i),
-    //     .ClkSlow_i(FifoRxRdClock_i),
-    //     .RxFifoRst_i(FifoRxRst_i),
-    //     .RxFifoRst_o(rxFifoRstSync)
-    // );
-
-
     TxFifoPtrSync #(
         .WIDTH(8),
         .STAGES(3)
@@ -147,7 +124,6 @@ module FifoCtrl #(
         .TxFifoWrPtr_i(txFifoRdPtr),
         .TxFifoWrPtr_o(txFifoRdPtrSync)
     );
-
     
     always @(posedge FifoRxRdClock_i) begin 
         if (FifoRxRstRdPtr_i) begin 
@@ -163,8 +139,6 @@ module FifoCtrl #(
         end
     end
     
-    
-    
     always @(posedge FifoTxWrClock_i) begin 
         if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
             fifoTxWriteEn <= 1'b1;
@@ -174,7 +148,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoTxRdClock_i ) begin 
         if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
             fifoTxReadEn <= 1'b1;
@@ -184,7 +157,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoRxWrClock_i) begin 
         if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
             fifoRxWriteEn <= 1'b1;
@@ -194,7 +166,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoRxRdClock_i) begin 
         if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
             fifoRxReadEn <= 1'b1;
@@ -204,7 +175,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoTxWrClock_i ) begin 
         if (FifoTxRstWrPtr_i) begin 
             txFifoWrPtr <= 8'h0;
@@ -227,7 +197,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoRxWrClock_i) begin 
         if (FifoRxRst_i) begin 
             rxFifoWrPtr <= 8'h0;
@@ -250,7 +219,6 @@ module FifoCtrl #(
         end
     end
     
-    
     always @(posedge FifoRxRdClock_i) begin 
         if (FifoRxRstRdPtr_i) begin 
             rxFifoUpDnCnt <= 8'h0;

sources_1/new/S5443_3Top.v

@@ -297,7 +297,7 @@ module S5443_3Top
     assign addrExt = {SmcAddr_i, 1'b0};
     assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
     assign txEn = spiTxRxEn[6:0];
-     assign Mosi0_o = mosi0;
+
     assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz;
     assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz;
     assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz;
@@ -305,27 +305,7 @@ module S5443_3Top
     assign Mosi1_io[4] =(SpiDir_o[4])?mosi1[4]:1'bz;
     assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz;
     assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
-    assign Mosi2_o = mosi2;
-    assign Mosi3_o = mosi3;
-
-    assign Ss_o[0] = (assel[0]) ? (chipSelFpga[0] ? ssMuxed[0] : 1'b1) : chipSelFpga[0];
-    assign Ss_o[1] = (assel[1]) ? (chipSelFpga[1] ? ssMuxed[1] : 1'b1) : chipSelFpga[1];
-    assign Ss_o[2] = (assel[2]) ? (chipSelFpga[2] ? ssMuxed[2] : 1'b1) : chipSelFpga[2];
-    assign Ss_o[3] = (assel[3]) ? (chipSelFpga[3] ? ssMuxed[3] : 1'b1) : chipSelFpga[3];
-    assign Ss_o[4] = (assel[4]) ? (chipSelFpga[4] ? ssMuxed[4] : 1'b1) : chipSelFpga[4];
-    assign Ss_o[5] = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
-    assign Ss_o[6] = (assel[6]) ? (chipSelFpga[6] ? ssMuxed[6] : 1'b1) : chipSelFpga[6];
-
-    assign SsFlash_o[0] = (assel[0]) ? (chipSelFlash[0] ? ssMuxed[0] : 1'b1) : chipSelFlash[0];
-    assign SsFlash_o[1] = (assel[1]) ? (chipSelFlash[1] ? ssMuxed[1] : 1'b1) : chipSelFlash[1];
-    assign SsFlash_o[2] = (assel[2]) ? (chipSelFlash[2] ? ssMuxed[2] : 1'b1) : chipSelFlash[2];
-    assign SsFlash_o[3] = (assel[3]) ? (chipSelFlash[3] ? ssMuxed[3] : 1'b1) : chipSelFlash[3];
-    assign SsFlash_o[4] = (assel[4]) ? (chipSelFlash[4] ? ssMuxed[4] : 1'b1) : chipSelFlash[4];
-    assign SsFlash_o[5] = (assel[5]) ? (chipSelFlash[5] ? ssMuxed[5] : 1'b1) : chipSelFlash[5];
-    assign SsFlash_o[6] = (assel[6]) ? (chipSelFlash[6] ? ssMuxed[6] : 1'b1) : chipSelFlash[6];
-
-    assign Sck_o = sckMuxed;
-
+  
     assign widthSel[0] = spi0CtrlRR[6:5];
     assign widthSel[1] = spi1CtrlRR[6:5];
     assign widthSel[2] = spi2CtrlRR[6:5];
@@ -510,31 +490,7 @@ module S5443_3Top
     assign SpiDir_o[4] = (spiMode[4])? 1'b1 : 1'b0 ;
     assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ;
     assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
-    
-    assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
-    assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
-    assign valToTxFifoRead[2] =  (spiMode[2])?valToTxQ[2]:valToTxR[2];
-    assign valToTxFifoRead[3] =  (spiMode[3])?valToTxQ[3]:valToTxR[3];
-    assign valToTxFifoRead[4] =  (spiMode[4])?valToTxQ[4]:valToTxR[4];
-    assign valToTxFifoRead[5] =  (spiMode[5])?valToTxQ[5]:valToTxR[5];
-    assign valToTxFifoRead[6] =  (spiMode[6])?valToTxQ[6]:valToTxR[6];
-    
-    assign valToRxFifo[0] = valToRxR[0];
-    assign valToRxFifo[1] = valToRxR[1];
-    assign valToRxFifo[2] = valToRxR[2];
-    assign valToRxFifo[3] = valToRxR[3];
-    assign valToRxFifo[4] = valToRxR[4];
-    assign valToRxFifo[5] = valToRxR[5];
-    assign valToRxFifo[6] = valToRxR[6];
-    
-    assign dataToRxFifo[0] = dataToRxFifoR[0];
-    assign dataToRxFifo[1] = dataToRxFifoR[1];
-    assign dataToRxFifo[2] = dataToRxFifoR[2];
-    assign dataToRxFifo[3] = dataToRxFifoR[3];
-    assign dataToRxFifo[4] = dataToRxFifoR[4];
-    assign dataToRxFifo[5] = dataToRxFifoR[5];
-    assign dataToRxFifo[6] = dataToRxFifoR[6];
-    
+          
     assign spi0TxFifoCtrlReg = txFifoCtrlReg[0];
     assign spi1TxFifoCtrlReg = txFifoCtrlReg[1];
     assign spi2TxFifoCtrlReg = txFifoCtrlReg[2];
@@ -828,6 +784,9 @@ module S5443_3Top
                 .PulsePol_i(clockPol[i]),
                 .ClockPhase_i(clockPhase[i]),
                 .EndianSel_i(endianSel[i]),
+                .ChipSelFlash_i(chipSelFlash[i]),
+                .ChipSelFpga_i(chipSelFpga[i]),
+                .Assel_i(assel[i]),
                 .Lag_i(lag[i]),
                 .Lead_i(leadx[i]),
                 .SelSt_i(selSt[i]),
@@ -839,12 +798,13 @@ module S5443_3Top
                 .RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
                 .DataFromRxFifo_o(dataFromRxFifo[i]),
 
-                .Sck_o(sckMuxed[i]),
-                .Ss_o(ssMuxed[i]),
-                .Mosi0_o(mosi0[i]),
+                .Sck_o(Sck_o[i]),
+                .Ss_o(Ss_o[i]),
+                .SsFlash_o(SsFlash_o[i]),
+                .Mosi0_o(Mosi0_o[i]),
                 .Mosi1_o(mosi1[i]),
-                .Mosi2_o(mosi2[i]),
-                .Mosi3_o(mosi3[i])
+                .Mosi2_o(Mosi2_o[i]),
+                .Mosi3_o(Mosi3_o[i])
             );
         end
     endgenerate

sources_1/new/SpiSubSystem/SpiLinesMuxer.v

@@ -32,12 +32,7 @@ assign mosi0Muxed = (SpiMode_i) ? Mosi0Q_i : Mosi0R_i;
 
 assign Ss_o = (Assel_i) ? (ChipSelFpga_i ? ssMuxed : 1'b1) : ChipSelFpga_i;
 assign SsFlash_o = (Assel_i) ? (ChipSelFlash_i ? ssMuxed:1'b1) : ChipSelFlash_i;
-//================================================================================
-//	CODING
-//================================================================================
-
-
-
-
+assign Sck_o = sckMuxed;
+assign Mosi0_o = mosi0Muxed;
 
 endmodule

sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -27,6 +27,10 @@ module SpiSubSystem #(
     input Lead_i,
     input SelSt_i,
     input [5:0] Stop_i,
+    input Assel_i,
+
+    input ChipSelFpga_i,
+    input ChipSelFlash_i,
 
     input SpiMode_i,
     input SpiEn_i,
@@ -37,6 +41,7 @@ module SpiSubSystem #(
 
     output Sck_o,
     output Ss_o,
+    output SsFlash_o,
     output Mosi0_o,
     output Mosi1_o,
     output Mosi2_o,
@@ -62,14 +67,11 @@ wire valToTxQ;
 
 wire valToTxFifoRead;
 wire valToRxFifoWrite;
+wire [CmdRegWidth-1:0] dataToRxFifo;
 
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-assign  Sck_o   =   (SpiMode_i) ? sckQ : sckR;
-assign  Mosi0_o =   (SpiMode_i) ? mosi0Q : mosi0R;
-assign  Ss_o    =   (SpiMode_i) ? ssQ : ssR;
-
 assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;
 
 //================================================================================
@@ -169,11 +171,28 @@ QuadSPIm QuadSPIm_inst (
     .SelSt_i(SelSt_i),
     .Sck_o(sckQ),
     .Ss_o(ssQ),
-    .Mosi0_o(mosi0_q),
+    .Mosi0_o(mosi0Q),
     .Mosi1_o(Mosi1_o),
     .Mosi2_o(Mosi2_o),
     .Mosi3_o(Mosi3_o),
     .Val_o(valToTxQ)
 );
 
+SpiLinesMuxer SpiLinesMuxer (
+    .SsR_i(ssR),
+    .SsQ_i(ssQ),
+    .SckR_i(sckR),
+    .SckQ_i(sckQ),
+    .Mosi0R_i(mosi0R),
+    .Mosi0Q_i(mosi0Q),
+    .ChipSelFpga_i(ChipSelFpga_i),
+    .ChipSelFlash_i(ChipSelFlash_i),
+    .Assel_i(Assel_i),
+    .SpiMode_i(SpiMode_i),
+    .Ss_o(Ss_o),
+    .SsFlash_o(SsFlash_o),
+    .Sck_o(Sck_o),
+    .Mosi0_o(Mosi0_o)
+);
+
 endmodule