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sources_1/new/QuadSPI/QuadSPIm.v

@@ -118,22 +118,26 @@ module QuadSPIm(
             stopFlag <= 1'b0;
         end
         else begin
-            if (SelSt_i) begin 
-                if (ss && !ssR) begin 
-                    stopFlag <= 1'b1;
-                end
-                else if ( delayCnt == Stop_i) begin 
-                    stopFlag <= 1'b0;
-                end
-            end
-            else begin 
-                if (!ss && ssR) begin 
-                    stopFlag <= 1'b1;
-                end
-                else if (delayCnt == Stop_i) begin 
-                    stopFlag <= 1'b0;
-                end
-            end
+			if (Stop_i != 0) begin
+				if (SelSt_i) begin 
+					if (ss && !ssR) begin 
+						stopFlag <= 1'b1;
+					end
+					else if ( delayCnt == Stop_i) begin 
+						stopFlag <= 1'b0;
+					end
+				end
+				else begin 
+					if (!ss && ssR) begin 
+						stopFlag <= 1'b1;
+					end
+					else if (delayCnt == Stop_i) begin 
+						stopFlag <= 1'b0;
+					end
+				end
+			end else begin
+				stopFlag <= 1'b0;
+			end
         end
     end
     
@@ -505,21 +509,33 @@ module QuadSPIm(
         end
     end
     
+    wire [31:0] test = ssNum+Lag_i+Lead_i;
+	
+    // always @(negedge Clk_i) begin 
+        // if (Rst_i) begin 
+            // ssCnt <= 1'b0;
+        // end
+        // else if (ssCnt < (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            // ssCnt <= ssCnt + 1'b1;
+        // end
+        // else begin
+            // if (ssCnt == ssNum-1 || !startFlag) begin 
+                // ssCnt <= 1'b0;
+            // end
+        // end
+    // end
     
-    always @(negedge Clk_i) begin 
+	 always @(negedge Clk_i) begin 
         if (Rst_i) begin 
             ssCnt <= 1'b0;
         end
         else if (ssCnt < (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
             ssCnt <= ssCnt + 1'b1;
-        end
-        else begin
-            if (ssCnt == ssNum-1 || !startFlag) begin 
-                ssCnt <= 1'b0;
-            end
+        end else begin
+            ssCnt <= 1'b0;
         end
     end
-    
+	
     
     
     

sources_1/new/QuadSPI/QuadSPImTb.v

@@ -0,0 +1,82 @@
+`timescale 1ns / 1ps
+
+module QuadSPImTb ();
+
+
+parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+reg rst;
+reg clk;
+
+wire [31:0] data = 32'hFAFA_0101;
+
+wire [1:0] widthSel  = 2'h2;
+wire clockPol = 1'b0;
+wire clockPhase = 1'b0;
+wire endianSel = 1'b0;
+wire lag = 1'b0;
+wire leadx = 1'b0;
+wire [5:0] stopDelay = 6'h0;
+wire selSt = 1'b1;
+
+reg [31:0] tbCnt;
+
+wire start = (tbCnt>=100);
+
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+
+//================================================================================
+//  CODING
+//================================================================================	
+
+always #(CLK_PERIOD/2) clk = ~clk;
+
+initial begin
+	clk = 0;
+	rst = 0;
+	#40
+	rst = 1;
+	#100
+	rst = 0;
+end
+
+always @(posedge clk) begin
+	if (rst) begin
+		tbCnt <= 0;
+	end else begin
+		tbCnt <= tbCnt+1;
+	end
+end
+
+QuadSPIm QuadSPIm
+(
+	.Clk_i(clk),
+	.Start_i(start),
+	.Rst_i(rst),
+	.EmptyFlag_i(1'b0),
+	.SpiData_i(data),
+	.Sck_o(),
+	.Ss_o(),
+	.Mosi0_o(),
+	.Mosi1_o(),
+	.Mosi2_o(),
+	.Mosi3_o(),
+	.WidthSel_i(widthSel),
+	.PulsePol_i(clockPol),
+	.ClockPhase_i(clockPhase),
+	.EndianSel_i(endianSel),
+	.Lag_i(lag),
+	.Lead_i(leadx),
+	.Stop_i(stopDelay),
+	.SelSt_i(selSt),
+	.Val_o()
+);
+			
+endmodule