Repo init

QuadSPI/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

QuadSPI/QuadSPIs.v

@@ -0,0 +1,221 @@
+module QuadSPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input Mosi1_i,
+    input Mosi2_i,
+    input Mosi3_i,
+
+    input [1:0] WidthSel_i,
+    input EnEdge_i,
+    input PulsePol_i,
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR; 
+reg SckReg; 
+reg [7:0] addrReg;
+reg [7:0] shiftReg0;
+reg [7:0] shiftReg1;
+reg [7:0] shiftReg2;
+
+reg [7:0] shiftReg0M;
+reg [7:0] shiftReg1M;
+reg [7:0] shiftReg2M;
+reg [7:0] addrRegM;
+
+reg Sck;
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(*) begin 
+    if (PulsePol_i) begin 
+        if (EnEdge_i) begin 
+            assign Sck = ~Sck_i;
+        end
+        else begin 
+            assign Sck = Sck_i;
+        end
+    end
+    else begin 
+        if (EnEdge_i) begin 
+            assign Sck = Sck_i;
+        end
+        else begin 
+            assign Sck = ~Sck_i;
+        end
+    end
+end
+always @(posedge Sck) begin 
+    if (Rst_i) begin 
+        SckReg <= 1'b0;
+    end
+    else begin 
+        SckReg <= Sck;
+    end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin
+        addrRegM = 8'h0; 
+        shiftReg0M = 8'h0;
+        shiftReg1M = 8'h0;
+        shiftReg2M = 8'h0;
+    end
+    else begin 
+        case(WidthSel_i)  
+             0: begin 
+                addrRegM   = addrReg  [1:0];
+                shiftReg0M = shiftReg0[1:0];
+                shiftReg1M = shiftReg1[1:0];
+                shiftReg2M = shiftReg2[1:0];
+            end
+            1: begin 
+                addrRegM   = addrReg  [3:0];
+                shiftReg0M = shiftReg0[3:0];
+                shiftReg1M = shiftReg1[3:0];
+                shiftReg2M = shiftReg2[3:0];
+            end
+            2: begin 
+                addrRegM   = addrReg  [5:0];
+                shiftReg0M = shiftReg0[5:0];
+                shiftReg1M = shiftReg1[5:0];
+                shiftReg2M = shiftReg2[5:0];
+            end
+            3: begin 
+                addrRegM   = addrReg  [7:0];
+                shiftReg0M = shiftReg0[7:0];
+                shiftReg1M = shiftReg1[7:0];
+                shiftReg2M = shiftReg2[7:0];
+            end
+        endcase
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 24'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+        end
+        else begin 
+            Data_o <= 24'h0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 8'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Addr_o <= addrRegM;
+        end
+    end
+end
+
+
+always @(posedge Sck) begin 
+    if (Rst_i) begin 
+        shiftReg0 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+        end
+        else begin 
+            shiftReg0 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        shiftReg1 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg1 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        shiftReg2 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg2 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck ) begin 
+    if (Rst_i) begin 
+        addrReg <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            addrReg <= {addrReg[6:0], Mosi3_i};
+        end
+        else begin 
+            addrReg <= 8'h0;
+        end
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (ssReg && !ssRegR) begin 
+        Val_o <= 1'b1;
+    end
+    else begin 
+        Val_o <= 1'b0;
+    end
+end
+
+
+
+
+endmodule

QuadSPI/QuadSPIs_tb.v

@@ -0,0 +1,275 @@
+`timescale 1ns / 1ps
+module QuadSPIs_tb ();
+
+reg Clk70_i;
+reg Clk50_i;
+wire Sck_i;
+wire Rst_i;
+
+reg[7:0] mosiReg0_tb;
+reg[7:0] mosiReg1_tb;
+reg[7:0] mosiReg2_tb;
+reg[7:0] mosiReg3_tb;
+
+
+reg [7:0] Mosi0_i;
+reg [7:0] Mosi1_i;
+reg [7:0] Mosi2_i;
+reg [7:0] Mosi3_i;
+reg EnEdge_i;
+reg Ss;
+reg SSr;
+reg SSm;
+reg Start_i;
+reg startFlag;
+reg [5:0] ssCnt; 
+reg [3:0] ssNum;
+reg [1:0] WidthSel_i;
+
+reg [31:0] SPIdata;
+
+
+// assign Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
+// assign Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
+// assign Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
+// assign Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
+assign Sck_i = (!Ss) ? (Clk70_i) : 1'b0;
+
+
+
+
+// always #(24.390243902439/2) Clk70_i = ~Clk70_i;// 41Mhz
+always #(14.285714285714/2) Clk70_i = ~Clk70_i;// 70Mhz
+// always #10 Clk70_i = ~Clk70_i;// 50 Mhz
+
+always #10 Clk50_i = ~Clk50_i;
+
+
+
+
+always @(*) begin 
+    case (WidthSel_i) 
+        0 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[1]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[1]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[1]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[1]):1'b0;
+        end
+        1 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[3]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[3]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[3]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[3]):1'b0;
+        end
+        2 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[5]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[5]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[5]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[5]):1'b0;
+        end
+        3 : begin 
+            Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
+            Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
+            Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
+            Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
+        end
+    endcase
+end
+
+
+
+
+
+
+
+initial begin 
+    Clk70_i = 1'b1;
+    // Clk70_i = 1'b0;//50 Mhz out of phase with src clk
+    Clk50_i = 1'b1;
+    Start_i = 1'b0;
+    EnEdge_i = 1'b1;
+    SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
+    WidthSel_i = 2'b11;
+    #100Start_i = 1'b1;
+    #500 Start_i = 1'b0;
+    #600 Start_i = 1'b1;
+     SPIdata = {1'h1, 7'h29, 24'd520050};
+    #100 Start_i = 1'b0;
+    #1500 Start_i = 1'b1;
+     SPIdata = {1'h0, 7'h2a, 24'd10};
+    #100 Start_i = 1'b0;
+
+end
+
+
+always @(posedge Clk70_i) begin
+    if (Rst_i) begin
+        SSr <=1'b0;
+    end
+    else begin 
+        SSr <= Ss;
+    end
+end
+
+
+always @(posedge Clk70_i) begin 
+    if (Rst_i) begin 
+        startFlag <= 1'b0;
+    end
+    else begin 
+        if (!Start_i) begin 
+            startFlag <= 1'b1;
+        end
+        else begin 
+            startFlag <= 1'b0;
+        end
+    end
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        ssNum = 1'b0;
+    end
+    else begin 
+        case (WidthSel_i) 
+            0 : begin 
+                ssNum = 2;
+            end
+            1 : begin 
+                ssNum = 4;
+            end
+            2 : begin 
+                ssNum = 6;
+            end
+            3 : begin 
+                ssNum = 8;
+            end
+        endcase
+    end
+end
+
+
+always @(posedge Clk70_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 1'b0;
+    end
+    else if (ssCnt < ssNum && startFlag  ) begin 
+        ssCnt <= ssCnt + 1'b1;
+    end
+    else begin
+        if (ssCnt == ssNum-1 || !startFlag) begin 
+            ssCnt <= 1'b0;
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        Ss <= 1'b1;
+    end
+    else begin 
+        if (ssCnt < ssNum && startFlag ) begin 
+            Ss <= 1'b0;
+        end
+        else begin 
+            Ss <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg0_tb <= SPIdata[31:24];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg0_tb <= { mosiReg0_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg0_tb <= SPIdata[31:24];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg1_tb <= SPIdata[23:16];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg1_tb <= { mosiReg1_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg1_tb <= SPIdata[23:16];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg2_tb <= SPIdata[15:8];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg2_tb <= { mosiReg2_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg2_tb <= SPIdata[15:8];
+        end
+    end
+end
+
+always @(negedge Clk70_i) begin 
+    if (Rst_i) begin 
+        mosiReg3_tb <= SPIdata[7:0];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg3_tb <= { mosiReg3_tb[6:0],1'b0 };
+        end
+        else begin 
+            mosiReg3_tb <= SPIdata[7:0];
+        end
+    end
+end
+
+
+
+
+
+
+QuadSPIs QuadSPI_inst (
+    .Sck_i(Sck_i),
+    .Clk_i(Clk50_i),
+    .Rst_i(Rst_i),
+    .Ss_i(Ss),
+    .WidthSel_i(WidthSel_i),
+    .Mosi0_i(Mosi0_i),
+    .Mosi1_i(Mosi1_i),
+    .Mosi2_i(Mosi2_i),
+    .Mosi3_i(Mosi3_i),
+    .EnEdge_i(EnEdge_i),
+    .PulsePol_i(1'b0)
+
+);
+
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk50_i),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+
+
+
+
+
+endmodule